== Series Details ==
Series: TGL TC enabling v2-CI (rev2)
URL : https://patchwork.freedesktop.org/series/67022/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6932 -> Patchwork_14486
Summary
---
**SUCCESS**
No regr
On Fri, 2019-09-20 at 14:44 -0700, Lucas De Marchi wrote:
> On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
> wrote:
> > From: Clinton A Taylor
> >
> > Added DKL Phy sequences and helpers functions to program voltage
> > swing, clock gating and dp mode.
> >
> > It is not written in DP ena
The expectation for bonded submission is that they are run concurrently,
in parallel on multiple engines. However, given a lack of constraints in
the scheduler's selection combined with timeslicing could mean that the
bonded requests could be run in opposite order on the same engine. With
just the
== Series Details ==
Series: TGL TC enabling v2-CI
URL : https://patchwork.freedesktop.org/series/67022/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6932 -> Patchwork_14485
Summary
---
**FAILURE**
Serious unknow
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Clinton A Taylor
>
> Added DKL Phy sequences and helpers functions to program voltage
> swing, clock gating and dp mode.
>
> It is not written in DP enabling sequence but "PHY Clockgating
> programming" states that clock gatin
On Fri, 2019-09-20 at 22:29 +0100, Chris Wilson wrote:
> Quoting Summers, Stuart (2019-09-20 22:09:46)
> > On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote:
> > > On 18/09/2019 18:31, Stuart Summers wrote:
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> > >
> > > Unl
Quoting Summers, Stuart (2019-09-20 22:09:46)
> On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote:
> > On 18/09/2019 18:31, Stuart Summers wrote:
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> >
> > Unless there was some discussion I missed we can't just turn it on
> >
Quoting Patchwork (2019-09-20 22:08:48)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/selftests: Verify the LRC
> register layout between init and HW
> URL : https://patchwork.freedesktop.org/series/67018/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes f
On Wed, 2019-09-18 at 13:39 -0700, Daniele Ceraolo Spurio wrote:
>
> On 9/18/19 10:31 AM, Stuart Summers wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> >
>
> What's the planned usage here? TGL HW only supports slice-level
> power-gating and with only 1 slice on TGL w
On Thu, 2019-09-19 at 08:00 +0100, Tvrtko Ursulin wrote:
> On 18/09/2019 18:31, Stuart Summers wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
>
> Unless there was some discussion I missed we can't just turn it on
> to
> work around a SKIP in IGT. Feature was deliberately
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Verify the LRC register
layout between init and HW
URL : https://patchwork.freedesktop.org/series/67018/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6932 -> Patchwork_14484
=
On Fri, Sep 20, 2019 at 1:54 PM Lucas De Marchi
wrote:
>
> On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
> wrote:
> >
> > From: Clinton A Taylor
> >
> > Add a helper function to return pin map for use during dkl phy
> > DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it
If platform supports and has modular FIA is enabled, the registers
bits also change, example: reading TC3 registers with modular FIA
enabled, driver should read from FIA2 but with TC1 bits offsets.
It is described in BSpec 50231 for DFLEXDPSP, other registers don't
have the BSpec description but t
From: Clinton A Taylor
Step 4.b was complete missed because it is only required to TC and TBT.
Bspec: 49190
Reviewed-by: Imre Deak
Reviewed-by: Lucas De Marchi
Signed-off-by: Clinton A Taylor
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 -
1 file
Patches from https://patchwork.freedesktop.org/series/66695/#rev2
that got rv-b and don't have dependencies over other patches, for
CI testing.
Clinton A Taylor (2):
drm/i915/tgl: Add missing ddi clock select during DP init sequence
drm/i915/tgl/pll: Set update_active_dpll
José Roberto de Sou
Adding a enable parameters allow us to share most of the code between
enable and disable functions.
v3:
Renamed icl_phy_clock_gating() to icl_phy_set_clock_gating()
Reviewed-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 73 -
From: Clinton A Taylor
Commit 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the
port is active") added this new hook while in parallel TGL upstream was
happening and this was missed.
Without this driver will crash when TC DDI is added and driver is
preparing to do a full modeset.
From: Vandita Kulkarni
These are the registers needed to program Dekel phy. Some register
definitions will be reused from MG PHY definitions, so adding a
comment on those.
Bspec: 49295
Reviewed-by: Lucas De Marchi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Clinton A Taylor
Signed-off-by:
New step added for TGL, required for us to check the TC
microcontroller health after power on TC aux.
BSpec: 49294
Reviewed-by: Imre Deak
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 13 +
1 file changed, 13 insertions(+)
diff --git
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Clinton A Taylor
>
> Add a helper function to return pin map for use during dkl phy
> DP_MODE settings, PORT_TX_DFLEXPA1 exist on ICL but we don't need it.
>
> The user of this function will come in future TC patches.
>
> Sign
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> From: Vandita Kulkarni
>
> Add a new function to write to dkl phy pll registers. As per the
> bspec all the registers are read modify write.
>
> Signed-off-by: Vandita Kulkarni
> Signed-off-by: José Roberto de Souza
> Signed-off-b
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Verify the LRC register
layout between init and HW
URL : https://patchwork.freedesktop.org/series/67018/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2b9117e29756 drm/i915/selftests: Verify the LRC re
== Series Details ==
Series: series starting with [v2,1/6] drm/i915: add i915_driver_modeset_remove()
URL : https://patchwork.freedesktop.org/series/67013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6931 -> Patchwork_14483
===
Disable rc6 to re-enable all engines. It seems that the multi-engine
machine lockup is tied to rc6; disabling it makes a gem-sync --run
basic-store-all survive for a few hours, whereas without we expect it to
die within seconds. The only question is how does CI fare with the
exchange?
For testing
Before we submit the first context to HW, we need to construct a valid
image of the register state. This layout is defined by the HW and should
match the layout generated by HW when it saves the context image.
Asserting that this should be equivalent should help avoid any undefined
behaviour and ve
== Series Details ==
Series: series starting with [v2,1/6] drm/i915: add i915_driver_modeset_remove()
URL : https://patchwork.freedesktop.org/series/67013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4f0318a8e293 drm/i915: add i915_driver_modeset_remove()
78b6e3b96f95 drm/i91
Quoting Patchwork (2019-09-20 20:52:03)
> == Series Details ==
>
> Series: drm/i915/tgl: Swap engines for rc6/powersaving
> URL : https://patchwork.freedesktop.org/series/67010/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6931 -> Patchwork_14482
> =
== Series Details ==
Series: drm/i915/tgl: Swap engines for rc6/powersaving
URL : https://patchwork.freedesktop.org/series/67010/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6931 -> Patchwork_14482
Summary
---
**SU
On Fri, 20 Sep 2019, Jani Nikula wrote:
> In general, prefer struct drm_i915_private * over struct drm_device *
> when either will do. Rename the local variables to i915. No functional
> changes.
This one was also already
Reviewed-by: Chris Wilson
in
http://mid.mail-archive.com/156890721641.1
Please ignore the two patches here. Critical fumble.
BR,
Jani.
On Fri, 20 Sep 2019, Jani Nikula wrote:
> For completeness, add counterpart to i915_driver_modeset_probe() and
> remove the asymmetry in the probe/remove parts. No functional changes.
>
> Reviewed-by: Chris Wilson
> Signed-off-by:
For completeness, add counterpart to i915_driver_modeset_probe() and
remove the asymmetry in the probe/remove parts. No functional changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 25 +++--
1 file changed, 15 insertions(+),
In general, prefer struct drm_i915_private * over struct drm_device *
when either will do. Rename the local variable to i915. No functional
changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 59 -
1 file changed, 2
In general, prefer struct drm_i915_private * over struct drm_device *
when either will do. Rename the local variables to i915. No functional
changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 69 ++--
drivers/gpu/drm/i915/display/intel_display.
The code is too specific and detailed to have open in a high level
function. Abstract away. As a drive-by improvement switch to using
enableddisabled() in logging and git rid of a redundant !!. No
functional changes.
v2: drop the !! while at it too (Chris)
Reviewed-by: Chris Wilson
Signed-off-by
In general, prefer struct drm_i915_private * over struct drm_device *
when either will do. Rename the local variable to i915. Also propagate
to intel_hpd_poll_fini(). No functional changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 3
The i915 specific mode config init code is too specific and detailed to
have open in a high level function. Abstract away. No functional
changes.
v2: nest drm_mode_config_init() in the function too (Chris)
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/in
For completeness, add counterpart to i915_driver_modeset_probe() and
remove the asymmetry in the probe/remove parts. No functional changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 25 +++--
1 file changed, 15 insertions(+),
In general, prefer struct drm_i915_private * over struct drm_device *
when either will do. Rename the local variable to i915. No functional
changes.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 59 -
1 file changed, 2
On Thu, Jul 18, 2019 at 05:50:41PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I was playing around with YCbCr 4:4:4 output and noticed several
> things wrong in our code. So I fixed it all and tossed in the
> prep work for YCbCr 4:4:4 output on ilk+.
>
> Ville Syrjälä (12):
> drm/d
== Series Details ==
Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/66956/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6929 -> Patchwo
Disable rc6 to re-enable all engines. It seems that the multi-engine
machine lockup is tied to rc6; disabling it makes a gem-sync --run
basic-store-all survive for a few hours, whereas without we expect it to
die within seconds. The only question is how does CI fare with the
exchange?
For testing
On Wed, Sep 18, 2019 at 5:07 PM José Roberto de Souza
wrote:
>
> Adding a enable parameters allow us to share most of the code between
> enable and disable functions.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 71
> 1 file
On Sat, Sep 21, 2019 at 01:55:25AM +0800, kbuild test robot wrote:
> tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
> head: 4bb6a9d5d9a8289673c4cb0786d44be8a63c21db
> commit: 6b97b118d4d542c7bc25b725c6de3947fffb921b [6/7] drm/i915/display:
> Extract ilk_read_luts()
>
> If
== Series Details ==
Series: series starting with [CI,v2,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/66956/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/67009/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6929 -> Patchwork_14480
=
On 9/20/19 5:51 AM, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66955/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6925_
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head: 4bb6a9d5d9a8289673c4cb0786d44be8a63c21db
commit: 6b97b118d4d542c7bc25b725c6de3947fffb921b [6/7] drm/i915/display:
Extract ilk_read_luts()
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
N
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/guc: Enable guc logging on guc
log relay write
URL : https://patchwork.freedesktop.org/series/67009/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
46eb3a716fff drm/i915/guc: Enable guc logging on guc log relay
== Series Details ==
Series: treewide: remove unused argument in lock_release()
URL : https://patchwork.freedesktop.org/series/67007/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.
> -Original Message-
> From: Chris Wilson
> Sent: Friday, September 20, 2019 9:04 AM
> To: Bloomfield, Jon ; intel-
> g...@lists.freedesktop.org; Tvrtko Ursulin
> Subject: RE: [Intel-gfx] [PATCH] drm/i915: Prevent bonded requests from
> overtaking each other on preemption
>
> Quoting Blo
From: Anusha Srivatsa
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
v2: Style chan
On Fri, Sep 20, 2019 at 01:42:13PM +0200, Maarten Lankhorst wrote:
> There was a integer wraparound when mode_clock became too high,
> and we didn't correct for the FEC overhead factor when dividing,
> with the calculations breaking at HBR3.
>
> As a result our calculated bpp was way too high, and
On Fri, Sep 20, 2019 at 08:50:36AM -0400, Qian Cai wrote:
> On Fri, 2019-09-20 at 10:38 +0100, Will Deacon wrote:
> > On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> > > Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> > > in __lock_release"), @nested is no long
On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> in __lock_release"), @nested is no longer used in lock_release(), so
> remove it from all lock_release() calls and friends.
>
> Signed-off-by: Qian Cai
> ---
Alth
On Fri, 2019-09-20 at 10:38 +0100, Will Deacon wrote:
> On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote:
> > Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
> > in __lock_release"), @nested is no longer used in lock_release(), so
> > remove it from all lock_release(
Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument
in __lock_release"), @nested is no longer used in lock_release(), so
remove it from all lock_release() calls and friends.
Signed-off-by: Qian Cai
---
drivers/gpu/drm/drm_connector.c | 2 +-
drivers/gpu/drm/i91
Quoting Tvrtko Ursulin (2019-09-20 17:22:42)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
> > Since we cannot allocate underneath the vm->mutex (it is used in the
> > direct-reclaim paths), we need to shift the allocations off into a
> > mutexless worker with fence recursion prevention. To know wh
Quoting Tvrtko Ursulin (2019-09-20 17:14:43)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
> > index 2b1baf2fcc8e..6d7ac129ce8a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_timeli
== Series Details ==
Series: drm/i915: Mark contents as dirty on a write fault
URL : https://patchwork.freedesktop.org/series/67000/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14478
Summary
---
*
On 02/09/2019 05:02, Chris Wilson wrote:
Since we cannot allocate underneath the vm->mutex (it is used in the
direct-reclaim paths), we need to shift the allocations off into a
mutexless worker with fence recursion prevention. To know when we need
this protection, we mark up the address spaces t
On 02/09/2019 05:02, Chris Wilson wrote:
Now that we now longer need to guarantee that the active callback is
under the struct_mutex, we can lift it out of the i915_gem_park() and
into the engine parking itself.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 19 -
On 02/09/2019 05:02, Chris Wilson wrote:
Forgo the struct_mutex serialisation for i915_active, and interpose its
own mutex handling for active/retire.
This is a multi-layered sleight-of-hand. First, we had to ensure that no
active/retire callbacks accidentally inverted the mutex ordering rules,
On Fri, Sep 20, 2019 at 04:58:53PM +0200, Thierry Reding wrote:
> On Thu, Sep 19, 2019 at 04:28:53PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The bar values are little endian, not big endian. The pack
> > function did it right but the unpack got it wrong. Fix it.
> >
> > Cc: s
On Thu, Sep 19, 2019 at 10:53:03PM +0300, Gwan-gyeong Mun wrote:
> Support for HDR10 video was introduced in DisplayPort 1.4.
> On GLK+ platform, in order to use DisplayPort HDR10, we need to support
> BT.2020 colorimetry and HDR Static metadata.
> It implements the CTA-861-G standard for transport
Quoting Chris Wilson (2019-09-20 17:03:34)
> Quoting Bloomfield, Jon (2019-09-20 16:50:57)
> > > -Original Message-
> > > From: Intel-gfx On Behalf Of
> > > Tvrtko
> > > Ursulin
> > > Sent: Friday, September 20, 2019 8:12 AM
> > > To: Chris Wilson ;
> > > intel-gfx@lists.freedesktop.org
Quoting Bloomfield, Jon (2019-09-20 16:50:57)
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Tvrtko
> > Ursulin
> > Sent: Friday, September 20, 2019 8:12 AM
> > To: Chris Wilson ; intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Prevent bonded re
On 9/20/2019 5:48 PM, Jani Nikula wrote:
On Fri, 20 Sep 2019, Animesh Manna wrote:
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initi
Quoting Tvrtko Ursulin (2019-09-20 16:12:23)
>
> On 20/09/2019 15:57, Chris Wilson wrote:
> > Quoting Chris Wilson (2019-09-20 09:36:24)
> >> Force bonded requests to run on distinct engines so that they cannot be
> >> shuffled onto the same engine where timeslicing will reverse the order.
> >> A
> -Original Message-
> From: Intel-gfx On Behalf Of Tvrtko
> Ursulin
> Sent: Friday, September 20, 2019 8:12 AM
> To: Chris Wilson ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Prevent bonded requests from
> overtaking each other on preemption
>
>
> On 20
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14477
Summary
---
**SUCCESS**
No regression
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
_
== Series Details ==
Series: DSB enablement. (rev9)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
396d115d8cc6 drm/i915/dsb: feature flag added for display state buffer.
5a60554c2d5d drm/i915/dsb: DSB context creation.
-:63:
== Series Details ==
Series: series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
URL : https://patchwork.freedesktop.org/series/66998/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14476
On 20/09/2019 15:57, Chris Wilson wrote:
Quoting Chris Wilson (2019-09-20 09:36:24)
Force bonded requests to run on distinct engines so that they cannot be
shuffled onto the same engine where timeslicing will reverse the order.
A bonded request will often wait on a semaphore signaled by its mas
Quoting Tvrtko Ursulin (2019-09-20 15:51:35)
>
> On 20/09/2019 13:42, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-09-20 13:24:47)
> >>
> >> On 20/09/2019 09:36, Chris Wilson wrote:
> >>> Force bonded requests to run on distinct engines so that they cannot be
> >>> shuffled onto the same e
== Series Details ==
Series: series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
URL : https://patchwork.freedesktop.org/series/66998/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dp: Fix dsc bpp calculations, v2.
Okay!
On Thu, Sep 19, 2019 at 04:28:53PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The bar values are little endian, not big endian. The pack
> function did it right but the unpack got it wrong. Fix it.
>
> Cc: sta...@vger.kernel.org
> Cc: linux-me...@vger.kernel.org
> Cc: Martin Bugge
>
Quoting Chris Wilson (2019-09-20 09:36:24)
> Force bonded requests to run on distinct engines so that they cannot be
> shuffled onto the same engine where timeslicing will reverse the order.
> A bonded request will often wait on a semaphore signaled by its master,
> creating an implicit dependency
== Series Details ==
Series: series starting with [01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
URL : https://patchwork.freedesktop.org/series/66998/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5a06a0350a83 drm/i915/dp: Fix dsc bpp calculations, v2.
30142b729b5c HAX drm/
On 20/09/2019 13:42, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-20 13:24:47)
On 20/09/2019 09:36, Chris Wilson wrote:
Force bonded requests to run on distinct engines so that they cannot be
shuffled onto the same engine where timeslicing will reverse the order.
A bonded request will
== Series Details ==
Series: drm/i915: Restrict qgv points which don't have enough bandwidth. (rev2)
URL : https://patchwork.freedesktop.org/series/66993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14475
On Fri, Sep 20, 2019 at 02:24:32PM +, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add comments to explain the ilk pipe csc operation a bit better.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/dis
== Series Details ==
Series: drm/i915: Restrict qgv points which don't have enough bandwidth. (rev2)
URL : https://patchwork.freedesktop.org/series/66993/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
58676dcb1195 drm/i915: Restrict qgv points which don't have enough bandwidth.
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add comments to explain the ilk pipe csc operation a bit better.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 26 +---
> --
> 1 file changed, 21 insertions
== Series Details ==
Series: Docs: fix incorrect use of kernel-doc format in structure description.
(rev2)
URL : https://patchwork.freedesktop.org/series/66922/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14474
=
== Series Details ==
Series: drm/i915: Add TigerLake bandwidth checking (rev5)
URL : https://patchwork.freedesktop.org/series/66817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14473
Summary
---
*
On Fri, 2019-09-20 at 16:19 +0300, Ville Syrjälä wrote:
> On Fri, Sep 20, 2019 at 01:44:13PM +0300, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> >
> > Currently we ar
On Fri, Sep 20, 2019 at 03:29:06PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote:
> > The memory type values have changed in TGL, so we need to translate them
> > differently than ICL.
> >
> > BSpec: 53998
> >
> > Cc: Ville Syrjälä
> > Cc: Stanislav L
== Series Details ==
Series: drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend
URL : https://patchwork.freedesktop.org/series/66991/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14472
Summary
--
On Fri, Sep 20, 2019 at 01:44:13PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case)
Hi all,
Any update on this series ? Last time I looked, everything looked ready
and waiting to be merged.
JJ
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Intel-gfx@lists.freedesktop.org
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== Series Details ==
Series: drm/i915: Prevent bonded requests from overtaking each other on
preemption
URL : https://patchwork.freedesktop.org/series/66990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14471
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're configuring the AVI infoframe quantization range bits as if
> we're always transmitting RGB pixels. Let's fix this so that we
> correctly indicate limited range YCC quantization range when
> transmitting YCbCr
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming
convention and load latest HuC
URL : https://patchwork.freedesktop.org/series/66955/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14466_full
Quoting Tvrtko Ursulin (2019-09-20 13:24:47)
>
> On 20/09/2019 09:36, Chris Wilson wrote:
> > Force bonded requests to run on distinct engines so that they cannot be
> > shuffled onto the same engine where timeslicing will reverse the order.
> > A bonded request will often wait on a semaphore sign
== Series Details ==
Series: drm/i915: Prevent bonded requests from overtaking each other on
preemption
URL : https://patchwork.freedesktop.org/series/66990/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7885378114ae drm/i915: Prevent bonded requests from overtaking each other
== Series Details ==
Series: mdev based hardware virtio offloading support
URL : https://patchwork.freedesktop.org/series/66989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14470
Summary
---
**SUC
Quoting Chris Wilson (2019-09-20 13:22:13)
> Quoting Chris Wilson (2019-09-20 13:18:21)
> > Since dropping the set-to-gtt-domain in commit a679f58d0510 ("drm/i915:
> > Flush pages on acquisition"), we no longer mark the contents as dirty on
> > a write fault. This has the issue of us then not marki
On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote:
> The memory type values have changed in TGL, so we need to translate them
> differently than ICL.
>
> BSpec: 53998
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Signed-off-by: James Ausmus
> ---
> drivers/gpu/drm/i915/display/
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