== Series Details ==
Series: i915 vgpu PV to improve vgpu performance
URL : https://patchwork.freedesktop.org/series/66787/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
16a1cd5cf965 drm/i915: introduced vgpu pv capability
-:125: CHECK:PARENTHESIS_ALIGNMENT: Alignment should ma
This patch handles ppgtt update from g2v notification.
It read out ppgtt pte entries from guest pte tables page and
convert them to host pfns.
It creates local ppgtt tables and insert the content pages
into the local ppgtt tables directly, which does not track
the usage of guest page table and re
implemented context submission pv optimizaiton within GVTg.
GVTg to read context submission data (elsp_data) from the shared_page
directly without trap cost and eliminate execlist HW behavior emulation
without injecting context switch interrupt to guest under PV
submisison mechanism.
v0: RFC.
v1:
based on the shared memory setup between guest and GVT, the simple
pv command buffer ring was introduced by this patch used to perform
guest-2-gvt single direction communication.
v1: initial support, added to address i915 PV v6 patch set comment.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm
implement pv_caps PVINFO register handler in GVTg to
control different level pv optimization within guest.
report VGT_CAPS_PV capability in pvinfo page for guest.
v0: RFC.
v1: rebase.
v2: rebase.
v3: renamed enable_pvmmio to pvmmio_caps which is used for host
pv caps.
v4: renamed pvmmio_caps to p
GVTg implemented shared_page setup operation and read_shared_page
functionality based on hypervisor_read_gpa().
the shared_page_gpa was passed from guest driver through PVINFO
shared_page_gpa register.
v0: RFC.
v1: rebase.
v2: rebase.
v3: added shared_page_gpa check and if read_gpa failure, retur
This patch extends vgpu ppgtt g2v notification to notify host
GVT-g of ppgtt update from guest including alloc_4lvl, clear_4lv4
and insert_4lvl.
These updates use the shared memory page to pass struct pv_ppgtt_update
from guest to GVT which is used for pv optimiation implemeation within
host GVT s
It is performance optimization to override the actual submisison backend
in order to eliminate execlists csb process and reduce mmio trap numbers
for workload submission without context switch interrupt by talking with
GVT via PV submisison notification mechanism between guest and GVT.
Use PV_SUBM
To enable vgpu pv features, we need to setup a shared memory page
which will be used for data exchange directly accessed between both
guest and backend i915 driver to avoid emulation trap cost.
guest i915 will allocate this page memory and then pass it's physical
address to backend i915 driver thr
pv capability for vgpu was introduced by pv_caps in struct
i915_virtual_gpu and a new pv_caps register for host GVT
was defined in struct vgt_if for vgpu pv optimization.
both of them are used to control different feature pv optimization
supported and implemented by both guest and host.
These fie
To improve vgpu performance, it could implement some PV optimization
such as to reduce the mmio access trap numbers or eliminate certain piece
of HW emulation within guest driver to reduce vm exit/vm enter cost.
the solutions in this patch set are implemented two PV optimizations based
on the shar
== Series Details ==
Series: drm/i915: fix SFC reset flow
URL : https://patchwork.freedesktop.org/series/66779/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6904_full -> Patchwork_14421_full
Summary
---
**SUCCESS**
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Matt
> Roper
> Sent: tiistai 17. syyskuuta 2019 3.35
> To: Lucas De Marchi
> Cc: Intel Graphics
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/cml: Add second PCH ID for CMP
>
> On
On Mon, 16 Sep 2019 12:17:54 -0700, Umesh Nerlige Ramappa wrote:
>
> On Sun, Sep 15, 2019 at 02:24:41PM +0300, Lionel Landwerlin wrote:
> > On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote:
> >> OA perf unit supports non-power of 2 report sizes. Enable support for
> >> these sizes in the driver.
>
== Series Details ==
Series: drm: Handle connector tile support only for modes that match tile size
URL : https://patchwork.freedesktop.org/series/66784/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6905 -> Patchwork_14424
== Series Details ==
Series: drm/i915: Adding YUV444 packed format support for skl+
URL : https://patchwork.freedesktop.org/series/66770/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6902_full -> Patchwork_14420_full
Summa
On Mon, Sep 16, 2019 at 05:26:10PM -0700, Lucas De Marchi wrote:
> On Mon, Sep 16, 2019 at 4:33 PM Matt Roper wrote:
> >
> > The CMP PCH ID we have in the driver is correct for the CML-U machines we
> > have
> > in our CI system, but the CML-S and CML-H CI machines appear to use a
>
> CML-S is b
On Mon, Sep 16, 2019 at 4:33 PM Matt Roper wrote:
>
> The CMP PCH ID we have in the driver is correct for the CML-U machines we have
> in our CI system, but the CML-S and CML-H CI machines appear to use a
CML-S is back to life, but CML-H is still failing. Is CML-H actually
using the same PCH?
Lu
== Series Details ==
Series: drm/i915/cml: Add second PCH ID for CMP
URL : https://patchwork.freedesktop.org/series/66782/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6905 -> Patchwork_14423
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/cml: Add second PCH ID for CMP
URL : https://patchwork.freedesktop.org/series/66782/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
96520eb9d5e8 drm/i915/cml: Add second PCH ID for CMP
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped co
== Series Details ==
Series: drm/i915/guc: Enable guc logging on guc log relay write (rev3)
URL : https://patchwork.freedesktop.org/series/66502/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6905 -> Patchwork_14422
Summary
DRM Fb driver expects multiple CRTCs if it sees connector->has_tile
is set, but we need to handle tile support and look for multiple CRTCs
only for the modes that match the tile size. The other modes should
be able to be displayed without tile support or uisng single CRTC.
This patch adds the chec
The CMP PCH ID we have in the driver is correct for the CML-U machines we have
in our CI system, but the CML-S and CML-H CI machines appear to use a
different PCH ID, leading our driver to detect no PCH for them.
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
References: 729ae330a0f2e2 ("drm/i915/cml: Int
Creating and opening the GuC log relay file enables and starts
the relay potentially before the caller is ready to consume logs.
Change the behavior so that relay starts only on an explicit call
to the write function (with a value of '1'). Other values flush
the log relay as before.
v2: Style chan
== Series Details ==
Series: drm/i915: fix SFC reset flow
URL : https://patchwork.freedesktop.org/series/66779/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6904 -> Patchwork_14421
Summary
---
**SUCCESS**
No regr
Thanks for the patch and reviews, pushed to drm-misc
Regards
Manasi
On Mon, Sep 16, 2019 at 02:12:14PM -0700, Souza, Jose wrote:
> On Mon, 2019-09-16 at 12:39 -0700, Manasi Navare wrote:
> > On Mon, Sep 16, 2019 at 07:34:32PM +, Souza, Jose wrote:
> > > Someone with drm-misc commit access cou
Our assumption that the we can ask the HW to lock the SFC even if not
currently in use does not match the HW commitment. The expectation from
the HW is that SW will not try to lock the SFC if the engine is not
using it and if we do that the behavior is undefined; on ICL the HW
ends up to returning
On 9/16/19 1:54 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-09-16 21:37:26)
On 9/14/19 1:25 AM, Chris Wilson wrote:
Before we execute a batch, we must first issue any and all TLB
invalidations so that batch picks up the new page table entries.
Tigerlake's preparser is weake
On Mon, 2019-09-16 at 12:39 -0700, Manasi Navare wrote:
> On Mon, Sep 16, 2019 at 07:34:32PM +, Souza, Jose wrote:
> > Someone with drm-misc commit access could push this?
> >
>
> Sure will push this series.
Thanks Manasi
>
> Manasi
>
> > Thanks
> >
> > On Sun, 2019-09-15 at 11:36 +
Quoting Daniele Ceraolo Spurio (2019-09-16 21:37:26)
>
>
> On 9/14/19 1:25 AM, Chris Wilson wrote:
> > Before we execute a batch, we must first issue any and all TLB
> > invalidations so that batch picks up the new page table entries.
> > Tigerlake's preparser is weakening our post-sync CS_STALL
On 9/14/19 1:25 AM, Chris Wilson wrote:
Before we execute a batch, we must first issue any and all TLB
invalidations so that batch picks up the new page table entries.
Tigerlake's preparser is weakening our post-sync CS_STALL inside the
invalidate pipe-control and allowing the loading of the ba
Patches 13, 14 and this 15 look ok to me. Those num/den combos in 13 I
cannot bet my head on but the plumbing look all ok.
Also if on 1..8 some patch wasn't pushed yet, those are all
Reviewed-by: Juha-Pekka Heikkila
Ville Syrjala kirjoitti 8.7.2019 klo 15.53:
From: Ville Syrjälä
Now that t
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
>Of Chris Wilson
>Sent: Sunday, September 15, 2019 2:46 PM
>To: dri-de...@lists.freedesktop.org
>Cc: intel-gfx@lists.freedesktop.org
>Subject: [PATCH 2/2] drm/mm: Pack allocated/scanned boolean i
On Mon, Sep 16, 2019 at 07:34:32PM +, Souza, Jose wrote:
> Someone with drm-misc commit access could push this?
>
Sure will push this series.
Manasi
> Thanks
>
> On Sun, 2019-09-15 at 11:36 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [CI,1/2] drm/
Someone with drm-misc commit access could push this?
Thanks
On Sun, 2019-09-15 at 11:36 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/connector: Share with non-
> atomic drivers the function to get the single encoder
> URL : https://patchwork.free
On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
> On 9/12/2019 7:09 PM, Jani Nikula wrote:
>> On Thu, 12 Sep 2019, "Sharma, Shashank" wrote:
>>> On 9/12/2019 12:41 AM, Animesh Manna wrote:
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request
On Sun, Sep 15, 2019 at 02:24:41PM +0300, Lionel Landwerlin wrote:
On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote:
OA perf unit supports non-power of 2 report sizes. Enable support for
these sizes in the driver.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 59
On Fri, Sep 13, 2019 at 03:36:39PM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 29-07-2019 om 21:17 schreef Manasi Navare:
> > Hi Ville,
> >
> > Thanks for your review, so do we want to merge this as is or
> > do we need some function to reject the 8K mode on ICL in
> > intel_dp_mode_valid()?
>
== Series Details ==
Series: drm/i915: Adding YUV444 packed format support for skl+
URL : https://patchwork.freedesktop.org/series/66770/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6902 -> Patchwork_14420
Summary
---
On Mon, 16 Sep 2019, Ville Syrjälä wrote:
> On Mon, Sep 16, 2019 at 05:05:10PM +0300, Jani Nikula wrote:
>> On Mon, 16 Sep 2019, Chris Wilson wrote:
>> > Quoting Jani Nikula (2019-09-16 10:29:01)
>> >> Stop setting ->pipe_mask to zero when display is disabled, allowing us
>> >> to have different
== Series Details ==
Series: drm/i915: Adding YUV444 packed format support for skl+
URL : https://patchwork.freedesktop.org/series/66770/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
37a24a45ac0a drm/i915: Adding YUV444 packed format support for skl+
-:9: WARNING:COMMIT_LOG_LO
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
On Sun, 2019-09-15 at 21:37 +0100, Chris Wilson wrote:
> Include the active context register state when dumping the engine.
>
> Suggested-by: Mika Kuoppala
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 +++
Den 03-09-2019 kl. 19:24, skrev Sasha Levin:
From: Chris Wilson
[ Upstream commit aa56a292ce623734ddd30f52d73f527d1f3529b5 ]
set_page_dirty says:
For pages with a mapping this should be done under the page lock
for the benefit of asynchronous memory errors who prefer a
Ping? Any further comment on this or can't we merge at least the locking
change?
Christian.
Am 11.09.19 um 12:53 schrieb Christian König:
Am 03.09.19 um 10:05 schrieb Daniel Vetter:
On Thu, Aug 29, 2019 at 04:29:14PM +0200, Christian König wrote:
This patch is a stripped down version of the
Quoting Ville Syrjälä (2019-09-16 15:27:40)
> On Mon, Sep 16, 2019 at 05:05:10PM +0300, Jani Nikula wrote:
> > The main goal here (in this specific patch) is to decouple disabled but
> > existing display from non-existing display. That lets us develop the two
> > cases independently, and I acknowle
On Mon, Sep 16, 2019 at 05:05:10PM +0300, Jani Nikula wrote:
> On Mon, 16 Sep 2019, Chris Wilson wrote:
> > Quoting Jani Nikula (2019-09-16 10:29:01)
> >> Stop setting ->pipe_mask to zero when display is disabled, allowing us
> >> to have different code paths for not actually having display hardwa
Quoting Jani Nikula (2019-09-16 10:29:01)
> Stop setting ->pipe_mask to zero when display is disabled, allowing us
> to have different code paths for not actually having display hardware,
> and having display hardware disabled. This lets us develop those two
> avenues independently.
>
> There are
On Mon, 16 Sep 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-09-16 10:29:01)
>> Stop setting ->pipe_mask to zero when display is disabled, allowing us
>> to have different code paths for not actually having display hardware,
>> and having display hardware disabled. This lets us develop tho
Quoting Jani Nikula (2019-09-16 10:29:01)
> Stop setting ->pipe_mask to zero when display is disabled, allowing us
> to have different code paths for not actually having display hardware,
> and having display hardware disabled. This lets us develop those two
> avenues independently.
>
> There are
On 9/13/2019 1:53 PM, Anshuman Gupta wrote:
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently. [Animesh]
v2: Using a switch statement for cleaner code.
On 9/13/2019 1:53 PM, Anshuman Gupta wrote:
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v1: Use of REG_BIT and using extra space for EXITLINE_ macro
definition. [Animesh]
Cc: Ja
On Mon, 16 Sep 2019, Eric Engestrom wrote:
> On Monday, 2019-09-16 11:53:24 +0300, Jani Nikula wrote:
>> On Fri, 13 Sep 2019, Eric Engestrom wrote:
>> > On Friday, 2019-09-13 14:51:39 +0300, Jani Nikula wrote:
>> >> Add helper to check if a drm debug category is enabled. Convert drm core
>> >> to
Quoting Petri Latvala (2019-09-16 13:06:04)
> On Sun, Sep 15, 2019 at 10:39:48AM +0100, Chris Wilson wrote:
> > If the blitter is not available, we cannot use it as a source for dirty
> > rectangles. We shall have to rely on the other engines to create GPU
> > dirty instead.
> >
> > v2: Try using
== Series Details ==
Series: drm/i915: stop conflating HAS_DISPLAY() and disabled display
URL : https://patchwork.freedesktop.org/series/66749/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6897_full -> Patchwork_14418_full
On Mon, Sep 16, 2019 at 10:59:13AM +0300, Dan Carpenter wrote:
> On Mon, Sep 16, 2019 at 10:31:35AM +0300, Jani Nikula wrote:
> > On Sat, 14 Sep 2019, Dan Carpenter wrote:
> > > tree:
> > > https://kernel.googlesource.com/pub/scm/linux/kernel/git/torvalds/linux.git
> > > master
> > > head: a
== Series Details ==
Series: drm/i915: Verify the engine after acquiring the active.lock
URL : https://patchwork.freedesktop.org/series/66753/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6898 -> Patchwork_14419
Summary
--
On Sun, Sep 15, 2019 at 10:39:48AM +0100, Chris Wilson wrote:
> If the blitter is not available, we cannot use it as a source for dirty
> rectangles. We shall have to rely on the other engines to create GPU
> dirty instead.
>
> v2: Try using lots of subgroup+fixtures
>
> Signed-off-by: Chris Wils
On Monday, 2019-09-16 11:53:24 +0300, Jani Nikula wrote:
> On Fri, 13 Sep 2019, Eric Engestrom wrote:
> > On Friday, 2019-09-13 14:51:39 +0300, Jani Nikula wrote:
> >> Add helper to check if a drm debug category is enabled. Convert drm core
> >> to use it. No functional changes.
> >>
> >> Signed-
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev8)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6897_full -> Patchwork_14417_full
Summary
-
== Series Details ==
Series: drm/i915: Verify the engine after acquiring the active.lock
URL : https://patchwork.freedesktop.org/series/66753/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b5756156fe80 drm/i915: Verify the engine after acquiring the active.lock
-:16: WARNING:CO
When using virtual engines, the rq->engine is not stable until we hold
the engine->active.lock (as the virtual engine may be exchanged with the
sibling). Since commit 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
we may retire a request concurrently with resubmitting it to HW, we need
to be
Quoting Tvrtko Ursulin (2019-09-16 11:13:23)
>
> On 02/09/2019 05:02, Chris Wilson wrote:
> > Replace the struct_mutex requirement for pinning the i915_vma with the
> > local vm->mutex instead. Note that the vm->mutex is tainted by the
> > shrinker (we require unbinding from inside fs-reclaim) and
== Series Details ==
Series: drm/i915: stop conflating HAS_DISPLAY() and disabled display
URL : https://patchwork.freedesktop.org/series/66749/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6897 -> Patchwork_14418
Summary
-
== Series Details ==
Series: drm/i915/dp: Support for DP HDR outputs (rev8)
URL : https://patchwork.freedesktop.org/series/65656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6897 -> Patchwork_14417
Summary
---
**SU
Stop setting ->pipe_mask to zero when display is disabled, allowing us
to have different code paths for not actually having display hardware,
and having display hardware disabled. This lets us develop those two
avenues independently.
There are no functional changes for when there is no display. Ho
== Series Details ==
Series: series starting with [1/2] drm/i915: Show the logical context ring
state on dumping
URL : https://patchwork.freedesktop.org/series/66729/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6896_full -> Patchwork_14416_full
=
On Fri, 13 Sep 2019, Eric Engestrom wrote:
> On Friday, 2019-09-13 14:51:39 +0300, Jani Nikula wrote:
>> Add helper to check if a drm debug category is enabled. Convert drm core
>> to use it. No functional changes.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/drm_atomic_uapi.c
== Series Details ==
Series: series starting with [1/2] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
URL : https://patchwork.freedesktop.org/series/66726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6896_full -> Patchwork_14415_full
=
On Fri, 13 Sep 2019, Lucas De Marchi wrote:
> On Fri, Sep 13, 2019 at 3:33 PM José Roberto de Souza
> wrote:
>>
>> From: Vandita Kulkarni
>>
>> Add a new function to write to dkl phy pll registers. As per the
>> bspec all the registers are read modify write.
>>
>> Signed-off-by: Vandita Kulkarni
== Series Details ==
Series: drm/i915/selftests: Exercise CS TLB invalidation
URL : https://patchwork.freedesktop.org/series/66718/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6896_full -> Patchwork_14414_full
Summary
---
On Mon, Sep 16, 2019 at 10:31:35AM +0300, Jani Nikula wrote:
> On Sat, 14 Sep 2019, Dan Carpenter wrote:
> > tree:
> > https://kernel.googlesource.com/pub/scm/linux/kernel/git/torvalds/linux.git
> > master
> > head: a7f89616b7376495424f682b6086e0c391a89a1d
> > commit: df0566a641f959108c152be
On Fri, 13 Sep 2019, Jani Nikula wrote:
> Prepare for making a distinction between not having display and having
> disabled display. Add INTEL_DISPLAY_ENABLED() and use it where
> HAS_DISPLAY() is used after intel_device_info_runtime_init(). This is
> initially duplication, as disabling display st
On Sat, 14 Sep 2019, Dan Carpenter wrote:
> tree:
> https://kernel.googlesource.com/pub/scm/linux/kernel/git/torvalds/linux.git
> master
> head: a7f89616b7376495424f682b6086e0c391a89a1d
> commit: df0566a641f959108c152be748a0a58794280e0e drm/i915: move modesetting
> core code under display/
According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses Um
It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it add
It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.
Based on colorspace property value create a VSC SDP packet with appropriate
colorspace. This would help to enable wider color gamut like BT
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. It adds output_colorspace to
intel_crtc_state struct as a place holder of pipe's output colorspace.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_sdp functi
It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +
1 file changed
Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
sta
Support for HDR10 video was introduced in DisplayPort 1.4.
On GLK+ platform, in order to use DisplayPort HDR10, we need to support
BT.2020 colorimetry and HDR Static metadata.
It implements the CTA-861-G standard for transport of static HDR metadata.
It enables writing of HDR metadata infoframe SDP
Because between HDMI and DP have different colorspaces, it renames
drm_mode_create_colorspace_property() function to
drm_mode_create_hdmi_colorspace_property() function for HDMI connector.
And it adds drm_mode_create_dp_colorspace_property() function for creating
of DP colorspace property.
In order
On Fri, 2019-09-13 at 22:13 +0300, Ville Syrjälä wrote:
> On Thu, Sep 12, 2019 at 02:33:34PM +0300, Gwan-gyeong Mun wrote:
> > Because between HDMI and DP have different colorspaces, it renames
> > drm_mode_create_colorspace_property() function to
> > drm_mode_create_hdmi_colorspace_property() func
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