Re: [Intel-gfx] [PATCH 2/3] drm/i915/perf: Add support for report sizes that are not power of 2

On Sun, 15 Sep 2019 04:24:41 -0700, Lionel Landwerlin wrote: > > On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote: > > OA perf unit supports non-power of 2 report sizes. Enable support for > > these sizes in the driver. > > > > Signed-off-by: Umesh Nerlige Ramappa > > --- > > drivers/gpu/drm/i91

Re: [Intel-gfx] [Nouveau] [PATCH v6 08/17] drm/ttm: use gem vma_node

On Wed, 11 Sep 2019 at 07:53, Thierry Reding wrote: > > On Sat, Sep 07, 2019 at 09:58:46PM -0400, Ilia Mirkin wrote: > > On Wed, Aug 21, 2019 at 7:55 AM Thierry Reding > > wrote: > > > > > > On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote: > > > > On Wed, 14 Aug 2019 at 20:14, Gerd Ho

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Show the logical context ring state on dumping

== Series Details == Series: series starting with [1/2] drm/i915: Show the logical context ring state on dumping URL : https://patchwork.freedesktop.org/series/66729/ State : success == Summary == CI Bug Log - changes from CI_DRM_6896 -> Patchwork_14416 ===

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Show the logical context ring state on dumping

== Series Details == Series: series starting with [1/2] drm/i915: Show the logical context ring state on dumping URL : https://patchwork.freedesktop.org/series/66729/ State : warning == Summary == $ dim checkpatch origin/drm-tip d33259a24579 drm/i915: Show the logical context ring state on du

[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Verify the LRC register layout between init and HW

Before we submit the first context to HW, we need to construct a valid image of the register state. This layout is defined by the HW and should match the layout generated by HW when it saves the context image. Asserting that this should be equivalent should help avoid any undefined behaviour and ve

[Intel-gfx] [PATCH 1/2] drm/i915: Show the logical context ring state on dumping

Include the active context register state when dumping the engine. Suggested-by: Mika Kuoppala Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drive

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)

== Series Details == Series: series starting with [1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling) URL : https://patchwork.freedesktop.org/series/66726/ State : success == Summary == CI Bug Log - changes from CI_DRM_6896 -> Patchwork_14415 ===

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)

== Series Details == Series: series starting with [1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling) URL : https://patchwork.freedesktop.org/series/66726/ State : warning == Summary == $ dim checkpatch origin/drm-tip f54627385b19 dma-fence: Serialise signal enabling (

[Intel-gfx] [PATCH 1/2] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling)

Make dma_fence_enable_sw_signaling() behave like its dma_fence_add_callback() and dma_fence_default_wait() counterparts and perform the test to enable signaling under the fence->lock, along with the action to do so. This ensure that should an implementation be trying to flush the cb_list (by signal

[Intel-gfx] [PATCH 2/2] drm/mm: Pack allocated/scanned boolean into a bitfield

The ulterior motive to switching the booleans over to bitops is to allow use of the allocated flag as a bitlock. Signed-off-by: Chris Wilson --- drivers/gpu/drm/drm_mm.c | 36 +++ .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 6 ++-- drivers/gpu/drm/i915/g

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Exercise CS TLB invalidation

== Series Details == Series: drm/i915/selftests: Exercise CS TLB invalidation URL : https://patchwork.freedesktop.org/series/66718/ State : success == Summary == CI Bug Log - changes from CI_DRM_6896 -> Patchwork_14414 Summary --- **

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Suspend pre-parser across GTT invalidations

== Series Details == Series: drm/i915/tgl: Suspend pre-parser across GTT invalidations URL : https://patchwork.freedesktop.org/series/66703/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14413_full Su

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise CS TLB invalidation

== Series Details == Series: drm/i915/selftests: Exercise CS TLB invalidation URL : https://patchwork.freedesktop.org/series/66718/ State : warning == Summary == $ dim checkpatch origin/drm-tip ec3adb8606d4 drm/i915/selftests: Exercise CS TLB invalidation -:208: WARNING:MEMORY_BARRIER: memory

[Intel-gfx] [PATCH] drm/i915/selftests: Exercise CS TLB invalidation

Check that we are correctly invalidating the TLB at the start of a batch after updating the GTT. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 227 ++ 1 file changed, 227 insertions(+) diff --git a/

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder

== Series Details == Series: series starting with [CI,1/2] drm/connector: Share with non-atomic drivers the function to get the single encoder URL : https://patchwork.freedesktop.org/series/66701/ State : success == Summary == CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14412_full

Re: [Intel-gfx] [PATCH 3/3] drm/i915/perf: Add the report format with a non-power-of-2 size

On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote: Add the report format with size that is not a power of 2. This allows use of all report formats defined in hardware. Move the format definition to end to avoid breaking API (Lionel) Signed-off-by: Umesh Nerlige Ramappa I think that like any

Re: [Intel-gfx] [PATCH 2/3] drm/i915/perf: Add support for report sizes that are not power of 2

On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote: OA perf unit supports non-power of 2 report sizes. Enable support for these sizes in the driver. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/i915_perf.c | 59 1 file changed, 21 insertions(+)

Re: [Intel-gfx] [PATCH 1/3] drm/i915/perf: rework aging tail workaround

On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote: From: Lionel Landwerlin Right now the workaround against the OA tail pointer race condition requires at least twice the internal kernel polling timer to make any data available. This changes introduce checks on the OA data written into the circ

[Intel-gfx] [PATCH i-g-t] igt/kms_frontbuffer_tracking: Skip over IGT_DRAW_BLT when there's no BLT

If the blitter is not available, we cannot use it as a source for dirty rectangles. We shall have to rely on the other engines to create GPU dirty instead. v2: Try using lots of subgroup+fixtures Signed-off-by: Chris Wilson --- tests/kms_frontbuffer_tracking.c | 58 +

[Intel-gfx] [PATCH i-g-t] i915: More gem_require_blitter()

Some more tests that used the less common blt interfaces. Signed-off-by: Chris Wilson --- tests/i915/gem_bad_reloc.c | 1 + tests/i915/gem_caching.c | 1 + tests/i915/gem_exec_blt.c| 1 + tests/i915/gem_partial_pwrite_pread.c| 1 + tests/i915/gem

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/perf: Enable non-power-of-2 OA report sizes

== Series Details == Series: drm/i915/perf: Enable non-power-of-2 OA report sizes URL : https://patchwork.freedesktop.org/series/66697/ State : success == Summary == CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14411_full Summary

[Intel-gfx] ✓ Fi.CI.IGT: success for TGL TC enabling

== Series Details == Series: TGL TC enabling URL : https://patchwork.freedesktop.org/series/66695/ State : success == Summary == CI Bug Log - changes from CI_DRM_6894_full -> Patchwork_14410_full Summary --- **SUCCESS** No regress