== Series Details ==
Series: drm/i915: Explicitly track active fw_domain timers
URL : https://patchwork.freedesktop.org/series/63331/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6428_full -> Patchwork_13556_full
Summary
-
== Series Details ==
Series: i915 vgpu PV to improve vgpu performance
URL : https://patchwork.freedesktop.org/series/6/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6428 -> Patchwork_13557
Summary
---
**SUCCESS*
== Series Details ==
Series: i915 vgpu PV to improve vgpu performance
URL : https://patchwork.freedesktop.org/series/6/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: introduced vgpu pv capability
Okay!
Commit: drm/i915: vgpu shared memo
== Series Details ==
Series: i915 vgpu PV to improve vgpu performance
URL : https://patchwork.freedesktop.org/series/6/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7dc9248b7979 drm/i915: introduced vgpu pv capability
-:91: CHECK:PARENTHESIS_ALIGNMENT: Alignment should mat
This patch handles ppgtt update from g2v notification.
It read out ppgtt pte entries from guest pte tables page and
convert them to host pfns.
It creates local ppgtt tables and insert the content pages
into the local ppgtt tables directly, which does not track
the usage of guest page table and re
GVTg implemented shared_page setup operation and read_shared_page
functionality based on hypervisor_read_gpa().
the shared_page_gpa was passed from guest driver through PVINFO
shared_page_gpa register.
v0: RFC.
v1: rebase.
v2: rebase.
v3: added shared_page_gpa check and if read_gpa failure, retur
pv capability for vgpu was introduced by pv_caps in struct
i915_virtual_gpu and a new pv_caps register for host GVT
was defined in struct vgt_if for vgpu pv optimization.
both of them are used to control different feature pv optimization
supported and implemented by both guest and host.
These fie
based on the shared memory setup between guest and GVT, the simple
pv command buffer ring was introduced by this patch used to perform
guest-2-gvt single direction communication.
v1: initial added to address i915 PV v6 patch set comment.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i91
implement pv_caps PVINFO register handler in GVTg to
control different level pv optimization within guest.
report VGT_CAPS_PV capability in pvinfo page for guest.
v0: RFC.
v1: rebase.
v2: rebase.
v3: renamed enable_pvmmio to pvmmio_caps which is used for host
pv caps.
v4: renamed pvmmio_caps to p
To enable vgpu pv features, we need to setup a shared memory page
which will be used for data exchange directly accessed between both
guest and backend i915 driver to avoid emulation trap cost.
guest i915 will allocate this page memory and then pass it's physical
address to backend i915 driver thr
To improve vgpu performance, it could implement some PV optimization
such as to reduce the mmio access trap numbers or eliminate certain piece
of HW emulation within guest driver to reduce vm exit/vm enter cost.
the solutions in this patch set are implemented two PV optimizations based
on the shar
implemented context submission pv optimizaiton within GVTg.
GVTg to read context submission data (elsp_data) from the shared_page
directly without trap cost and eliminate execlist HW behavior emulation
without injecting context switch interrupt to guest under PV
submisison mechanism.
v0: RFC.
v1:
It is performance optimization to override the actual submisison backend
in order to eliminate execlists csb process and reduce mmio trap numbers
for workload submission without context switch interrupt by talking with
GVT via PV submisison notification mechanism between guest and GVT.
Use PV_SUBM
This patch extends vgpu ppgtt g2v notification to notify host
GVT-g of ppgtt update from guest including alloc_4lvl, clear_4lv4
and insert_4lvl.
These updates use the shared memory page to pass struct pv_ppgtt_update
from guest to GVT which is used for pv optimiation implemeation within
host GVT s
== Series Details ==
Series: drm/i915: Explicitly track active fw_domain timers
URL : https://patchwork.freedesktop.org/series/63331/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6428 -> Patchwork_13556
Summary
---
Stop guessing over whether we have an extra wakeref held by the delayed
fw put, and track it explicitly for the sake of debug.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_uncore.c | 13 ++---
drivers/gpu/drm/i915/intel_uncore.h | 1 +
2 files changed,
== Series Details ==
Series: series starting with [01/11] drm/i915/gtt: Use shallow dma pages for
scratch
URL : https://patchwork.freedesktop.org/series/63329/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6428 -> Patchwork_13555
==
== Series Details ==
Series: series starting with [01/11] drm/i915/gtt: Use shallow dma pages for
scratch
URL : https://patchwork.freedesktop.org/series/63329/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/gtt: Use shallow dma pages for scra
== Series Details ==
Series: series starting with [01/11] drm/i915/gtt: Use shallow dma pages for
scratch
URL : https://patchwork.freedesktop.org/series/63329/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
46b4d072b194 drm/i915/gtt: Use shallow dma pages for scratch
627dff7858
With an explicit level, we can refactor the separate clear functions
as a simple recursive function. The additional knowledge of the level
allows us to spot when we can free an entire subtree at once.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Kconfig.debug | 15 +++
drivers/gpu/drm/
Refactor the separate allocation routines into a single recursive
function.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 272 ++--
1 file changed, 97 insertions(+), 175 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/
Each level has its own scratch. Make the levels more obvious by forgoing
the fancy similarly names and replace them with a number. 0 is the bottom
most level, the physical page used for actual data; 1+ are the page
directories.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c
With an explicit level, we can refactor the separate cleanup functions
as a simple recursive function. We take the opportunity to pass down the
size of each level so that we can deal with the different sizes of
top-level and avoid over allocating for 32/36-bit vm.
Signed-off-by: Chris Wilson
---
Apply the new radix shift helpers to extract the multi-level indices
cleanly when inserting pte into the gtt tree.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 115 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 92 ++
2 files cha
We only use the dma pages for scratch, and so do not need to allocate
the extra storage for the shadow page directory.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 192
drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +-
2 files
In preparation for refactoring the free/clear/alloc, first move the code
around so that we can avoid forward declarations in the next set of
patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 673 ++--
1 file changed, 337 insertions(+), 336 del
This will be useful to consolidate recursive code.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +++
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
ind
After Mika tidied up the structs such that we use the same routines
everywhere on gen8, take the next small step so that the redudant
routines are reduced by simple recursion.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lis
The page directory extends the page table with the shadow entries. Make
the page directory struct embed the page table for easier code reuse.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 100 ++--
The radix levels of each page directory are easily determined so replace
the numerous hardcoded constants with precomputed derived constants.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 +
1 file changed, 39 insertions(+)
diff --git a/dri
We can simplify our gtt walking code by comparing against NULL for
scratch entries as opposed to looking up the distinct per-level scratch
pointer.
The only caveat is to remember to protect external parties and map the
NULL to the scratch top pd.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/
== Series Details ==
Series: drm/i915: Fix assert_forcewake_active consideration of timer (rev2)
URL : https://patchwork.freedesktop.org/series/63323/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6428 -> Patchwork_13554
Su
== Series Details ==
Series: drm/i915: Pull assert_forcewake_active() underneath the lock (rev2)
URL : https://patchwork.freedesktop.org/series/63273/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6427_full -> Patchwork_13552_full
==
The timer will keep running until there are no active users of the
fw_domain; until it completes, the wake_count will be raised.
Signed-off-by: Chris Wilson
---
Last go, honest.
-Chris
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dri
The timer only runs if there are no active users of the fw_domain
remain, that is if the current value of domain->active is *false*.
Fix the logical inversion in the assert!
Signed-off-by: Chris Wilson
---
Stop flip-flopping long enough to tell me is the last fix required!
-Chris
---
drivers/gpu
Quoting Chris Wilson (2019-07-07 16:11:35)
> Make no assumption that something in the background is not acquiring the
> fw_domain -- but we still do not track owner so assume that any active
> domain is intended by the caller.
>
> Signed-off-by: Chris Wilson
Preemptive irc r-b (under a blanket r
== Series Details ==
Series: drm/i915: Pull assert_forcewake_active() underneath the lock (rev2)
URL : https://patchwork.freedesktop.org/series/63273/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6427 -> Patchwork_13552
Su
Make no assumption that something in the background is not acquiring the
fw_domain -- but we still do not track owner so assume that any active
domain is intended by the caller.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_uncore.c | 4
1 file changed, 4 insertions(+)
diff --
Looks good to me, there in one minor comment.
On 6/25/2019 11:24 PM, Lucas De Marchi wrote:
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marc
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