From gen12 onwards Display State Buffer(DSB) is hardware capability
added which allows driver to batch submit display HW programming.
Feature flag has_dsb added to identify the driver/platform support
at runtime.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm
The function will internally get the gem buffer from global GTT
which is mapped in cpu domain to feed the data + opcode for DSB engine.
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/dr
DSB can access specific register, To identify those register
which can be written through DSB, enum reg_write_cap is added
to hold the capability.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
1 file changed, 12 insertions
Display State Buffer (DSB) is hardware capability which allows
driver to batch submit HW programming.
As part of initial enablement common api created which currently used
to program gamma lut proramming.
Going forwad DSB support can be added for HDR and flip related operation.
Few changes of th
Freed the gem object after completion of dsb workload.
Cc: Shashank Sharma
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_dsb.c | 16
drivers/gpu/drm/i915/intel_dsb.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers
DSB context destroyed using intel_dsb_put() in cleanup function.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
Existing mmio-reg-write need intel_uncore handle which is part
of dev_priv structure and the same design is followed by
adding dsb handle in dev_priv for programming registers through DSB.
I915_WRITE is modified to check for register capability and call
dsb-reg-write based on its capability.
No c
The dsb get call added part of the prepare so that we don't
have things that can fail in the commit proper.
The allocated dsb-context will be tracked under intel_crtc_state
instead of intel_crtc per atomic-commit.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_dsb.c | 9 +
1 file changed, 9 insertions(+)
diff -
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9 ++
drivers/gpu/drm/i915/intel_dsb.c | 54 +++
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rod
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-b
Added key register definitions of DSB.
dsb-ctrl register is required to enable dsb-engine.
head-ptr register hold the head of buffer address from where the
execution will start.
Programming tail-ptr register is a trigger point to start execution.
Cc: Uma Shankar
Cc: Jani Nikula
Cc: Rodrigo Vi
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. Will be using for bulk register programming
e.g. gamma lut programming, HDR meta data programming.
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
dr
Hi, Derek:
On Fri, 2019-06-21 at 20:41 -0700, Derek Basehore wrote:
> This inits the panel orientation property for the mediatek dsi driver
> if the panel orientation (connector.display_info.panel_orientation) is
> not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
>
Reviewed-by: CK Hu
> Signed-off-by: D
Hello,
immediately after I have upgraded my system from Fedora 28 x64 to 29
graphics' issue started. Mouse leaves a trail composed of multiple
blinking cursors and sometimes rectangular not-refreshed parts. The more
loaded the system is the more pronounced the issue - the longer the
trail. It
Hi Jani.
On Thu, Jun 27, 2019 at 02:01:03PM +0300, Jani Nikula wrote:
> Fix build warning if drm_panel.h is built with CONFIG_OF=n or
> CONFIG_DRM_PANEL=n and included without the prerequisite err.h:
>
> ./include/drm/drm_panel.h: In function ‘of_drm_find_panel’:
> ./include/drm/drm_panel.h:203:9
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