On Tue, 2019-06-18 at 13:27 +0100, Guillaume Tucker wrote:
> Add libatomic to the Fedora docker image so it can link binaries that
> use __atomic_* functions. Also explicitly add libatomic1 to Debian
> docker images as it is needed in particular on non-x86 architectures
> for run-time linkage.
Pe
On 18/06/2019 20:54, john.c.harri...@intel.com wrote:
From: John Harrison
Newer hardware supports extra feature in the whitelist registers. This
patch updates the selftest to test that entries marked as read only
are actually read only.
Also updated the read/write access definitions to make i
On Tue, 2019-06-18 at 17:03 +0100, Guillaume Tucker wrote:
> On 18/06/2019 15:37, Ser, Simon wrote:
> > On Tue, 2019-06-18 at 14:59 +0100, Guillaume Tucker wrote:
> > > On 18/06/2019 14:20, Ser, Simon wrote:
> > > > On Tue, 2019-06-18 at 13:27 +0100, Guillaume Tucker wrote:
> > > > > Add conditiona
On 18/06/2019 21:08, John Harrison wrote:
Tvrtko, does this look plausible?
It seems to work for me in that it passes on ICL with the new read-only
registers. I'm not sure if there is a valid way to detect whether the
registers are actually readable though. How would the test know what is
a
On 18/06/2019 21:21, Chris Wilson wrote:
In order to pin the engine as busy, we have to prevent the kernel from
executing other independent work ahead of our plug, so tell the spinner
to not allow preemption.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_engines.c | 3 ++-
1 file chang
Hi,
Here's one gvt fix for 5.2-rc6 to sanitize reserved register write in
PVINFO which should be discarded. This fixed some guest behavior which
contain some unmerged features that probe through PVINFO register state.
Thanks.
--
The following changes since commit 15e7f52a4596b496ce3da2fa4c1f94c6
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ezequiel Garcia
>Sent: Friday, June 14, 2019 9:48 PM
>To: Shankar, Uma
>Cc: Emil Velikov ; intel-gfx@lists.freedesktop.org;
>Syrjala,
>Ville ; Lankhorst, Maarten
>;
>dri-devel
>Subject:
> -Original Message-
> From: Kulkarni, Vandita
> Sent: Wednesday, June 19, 2019 10:49 AM
> To: José Roberto de Souza ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI
> strap
>
> > -Original Message
> -Original Message-
> From: Intel-gfx On Behalf Of José
> Roberto de Souza
> Sent: Wednesday, June 19, 2019 1:30 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/ehl/dsi: Enable AFE over PPI strap
>
> The other additional step in th
== Series Details ==
Series: Implicit dev_priv removal and GT compartmentalization (rev10)
URL : https://patchwork.freedesktop.org/series/62046/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6291_full -> Patchwork_13327_full
== Series Details ==
Series: drm/i915: Check backlight type while doing eDP backlight initializaiton
URL : https://patchwork.freedesktop.org/series/62362/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6300 -> Patchwork_13341
== Series Details ==
Series: drm/i915: Use drm_gem_object.resv
URL : https://patchwork.freedesktop.org/series/62307/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6291_full -> Patchwork_13326_full
Summary
---
**FAILU
== Series Details ==
Series: drm/drm_vblank: Change EINVAL by the correct errno (rev4)
URL : https://patchwork.freedesktop.org/series/51147/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6300 -> Patchwork_13340
Summary
If LFP backlight type setting from VBT was "VESA eDP AUX Interface".
Driver should check panel capability and try to initialize aux backlight.
No matter i915_modparams.enable_dpcd_backlight was enabled or not.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Jose Roberto de Souza
Cc: Cooper Chiou
Signed
For historical reason, the function drm_wait_vblank_ioctl always return
-EINVAL if something gets wrong. This scenario limits the flexibility
for the userspace make detailed verification of the problem and take
some action. In particular, the validation of “if (!dev->irq_enabled)”
in the drm_wait_v
== Series Details ==
Series: mm: Use local variable for swap address space
URL : https://patchwork.freedesktop.org/series/62358/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6299 -> Patchwork_13339
Summary
---
**FAI
This addresses the following build error:
mm/huge_memory.c: In function ‘__split_huge_page’:
mm/huge_memory.c:2506:41: warning: dereferencing ‘void *’ pointer
__xa_store(&swap_address_space(entry)->i_pages,
^~
mm/huge_memory.c:2506:41: error: request for
== Series Details ==
Series: series starting with [1/6] dma-buf: add dynamic DMA-buf handling v10
URL : https://patchwork.freedesktop.org/series/62299/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6291_full -> Patchwork_13325_full
=
On Fri, 2019-06-14 at 21:27 -0700, Dhinakaran Pandiyan wrote:
> "drm/i915/psr" in the subject.
Done
>
> On Sat, 2019-04-20 at 13:55 -0700, José Roberto de Souza wrote:
> > PSR registers are a mess, some have the full address while others
> > just
> > have the additional offset from psr_mmio_base
== Series Details ==
Series: drm/i915/gtt: Defer address space cleanup to an RCU worker
URL : https://patchwork.freedesktop.org/series/62356/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6299 -> Patchwork_13338
Summary
---
== Series Details ==
Series: drm/i915/gtt: Defer address space cleanup to an RCU worker
URL : https://patchwork.freedesktop.org/series/62356/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/gtt: Defer address space cleanup to an RCU worker
+./i
== Series Details ==
Series: series starting with [1/3] drm/i915/icl: Add new supported CD clocks
URL : https://patchwork.freedesktop.org/series/62355/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6299 -> Patchwork_13337
S
== Series Details ==
Series: drm/i915/execlists: Detect cross-contamination with GuC
URL : https://patchwork.freedesktop.org/series/62296/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6291_full -> Patchwork_13324_full
Summ
On 6/18/19 4:23 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-06-19 00:06:39)
On 6/18/19 2:23 AM, Tvrtko Ursulin wrote:
On 17/06/2019 19:09, Daniele Ceraolo Spurio wrote:
-static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
+static int intel_uncore_fw_doma
Enable RCU protection of i915_address_space and its ppgtt superclasses,
and defer its cleanup into a worker executed after an RCU grace period.
In the future we will be able to use the RCU protection to reduce the
locking around VM lookups, but the immediate benefit is being able to
defer the rele
== Series Details ==
Series: series starting with [1/3] drm/i915/icl: Add new supported CD clocks
URL : https://patchwork.freedesktop.org/series/62355/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Add new supported CD clocks
Okay!
Comm
Quoting Daniele Ceraolo Spurio (2019-06-19 00:06:39)
>
>
> On 6/18/19 2:23 AM, Tvrtko Ursulin wrote:
> >
> > On 17/06/2019 19:09, Daniele Ceraolo Spurio wrote:
> >> -static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> >> +static int intel_uncore_fw_domains_init(struct intel_u
On 6/18/19 2:23 AM, Tvrtko Ursulin wrote:
On 17/06/2019 19:09, Daniele Ceraolo Spurio wrote:
We'd like to introduce a display uncore with no forcewake domains, so
let's avoid wasting memory and be ready to allocate only what we need.
Even without multiple uncore, we still don't need all the d
EHL has it own voltage level requirement depending on cd clock.
BSpec: 21809
Cc: Clint Taylor
Cc: Matt Roper
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 --
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/g
EHL do not support 648 and 652.8 MHz.
BSpec: 20598
Cc: Clint Taylor
Cc: Matt Roper
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk
Now 180, 172.8 and 192 MHz are supported.
180 and 172.8 MHz CD clocks will only be used when audio is not
enabled as state by BSpec and implemented in
intel_crtc_compute_min_cdclk(), CD clock must be at least twice of
Azalia BCLK and BCLK by default is 96 MHz, it could be set to 48 MHz
but we are
On Thu, Jun 13, 2019 at 11:54 AM Liviu Dudau wrote:
>
> On Wed, Jun 12, 2019 at 11:16:02PM -0300, Brian Starkey wrote:
> > Add support in igt_kms for writeback connectors, with the ability
> > to attach framebuffers.
> >
> > v5: Rebase and add DRM_CLIENT_CAP_WRITEBACK_CONNECTORS before
> > drmMode
On Tue, Jun 18, 2019 at 08:01:13PM +0200, Greg Kroah-Hartman wrote:
> On Tue, Jun 18, 2019 at 07:32:20PM +0200, Daniel Vetter wrote:
> > On Tue, Jun 18, 2019 at 5:25 PM Greg Kroah-Hartman
> > wrote:
> > > On Tue, Jun 18, 2019 at 05:19:38PM +0200, Greg Kroah-Hartman wrote:
> > > > I could just "ope
== Series Details ==
Series: series starting with [1/2] drm/i915/ehl/dsi: Set lane latency
optimization for DW1
URL : https://patchwork.freedesktop.org/series/62340/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6299 -> Patchwork_13336
On 6/18/19 2:00 AM, Tvrtko Ursulin wrote:
On 17/06/2019 19:09, Daniele Ceraolo Spurio wrote:
We always call some of the setup/cleanup functions for forcewake, even
if the feature is not actually available. Skipping these operations if
forcewake is not available saves us some operations on old
== Series Details ==
Series: i915/gem_ctx_engine: Prevent preemption
URL : https://patchwork.freedesktop.org/series/62342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6299 -> IGTPW_3174
Summary
---
**SUCCESS**
N
== Series Details ==
Series: drm/i915: Switch to per-crtc vblank vfuncs
URL : https://patchwork.freedesktop.org/series/62287/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6290_full -> Patchwork_13321_full
Summary
---
== Series Details ==
Series: drm/i915: Implement read-only support in whitelist selftest
URL : https://patchwork.freedesktop.org/series/62339/
State : failure
== Summary ==
Applying: drm/i915: Implement read-only support in whitelist selftest
error: sha1 information is lacking or useless
(dri
In order to pin the engine as busy, we have to prevent the kernel from
executing other independent work ahead of our plug, so tell the spinner
to not allow preemption.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ctx_engines.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Tvrtko, does this look plausible?
It seems to work for me in that it passes on ICL with the new read-only
registers. I'm not sure if there is a valid way to detect whether the
registers are actually readable though. How would the test know what is
a valid value? If one assumes that one gets ba
The other additional step in the DSI sequqence for EHL.
BSpec: 20597
Cc: Uma Shankar
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8
drivers/gpu/drm/i915/i915_reg.h| 4
2 files changed, 12 insertions(+)
diff --git a/dr
From: Vandita Kulkarni
EHL has 2 additional steps in the DSI sequence, this is one of then
the lane latency optimization for DW1.
BSpec: 20597
Cc: Uma Shankar
Cc: Rodrigo Vivi
Cc: Jani Nikula
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++
driver
From: John Harrison
Newer hardware supports extra feature in the whitelist registers. This
patch updates the selftest to test that entries marked as read only
are actually read only.
Also updated the read/write access definitions to make it clearer that
they are an enum field not a set of single
On Tue, 2019-06-18 at 12:00 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/psr: Force manual PSR exit in older gens
> URL : https://patchwork.freedesktop.org/series/62249/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6287_full -> Patchwork_13316
== Series Details ==
Series: series starting with [01/26] drm/i915: Keep engine alive as we retire
the context
URL : https://patchwork.freedesktop.org/series/62278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6290_full -> Patchwork_13320_full
===
Quoting Daniele Ceraolo Spurio (2019-06-18 19:40:40)
>
>
> On 6/18/19 3:22 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-06-17 19:09:33)
> >> We always call some of the setup/cleanup functions for forcewake, even
> >> if the feature is not actually available. Skipping these ope
== Series Details ==
Series: drm/i915/ehl: Allow combo PHY A to drive a third external display (rev3)
URL : https://patchwork.freedesktop.org/series/62131/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6297 -> Patchwork_13334
===
On 6/18/19 3:22 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-06-17 19:09:33)
We always call some of the setup/cleanup functions for forcewake, even
if the feature is not actually available. Skipping these operations if
forcewake is not available saves us some operations on olde
== Series Details ==
Series: drm/i915/ehl: Allow combo PHY A to drive a third external display (rev3)
URL : https://patchwork.freedesktop.org/series/62131/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d46fd4652551 drm/i915/ehl: Allow combo PHY A to drive a third external displ
== Series Details ==
Series: docs: fix some broken references due to txt->rst renames
URL : https://patchwork.freedesktop.org/series/62327/
State : failure
== Summary ==
Applying: docs: fix some broken references due to txt->rst renames
error: sha1 information is lacking or useless
(Documenta
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Flush live_evict
URL : https://patchwork.freedesktop.org/series/62325/
State : failure
== Summary ==
Applying: drm/i915/selftests: Flush live_evict
Using index info to reconstruct a base tree...
M drivers/gpu/drm
On Tuesday, 2019-06-18 16:02:41 +0200, Daniel Vetter wrote:
> I rushed merging this a bit too much, and Noralf pointed out that
> we're a lot better already and have made great progress.
>
> Let's try again.
>
> Fixes: 42dbbb4b54a3 ("drm/todo: Add new debugfs todo")
> Cc: Greg Kroah-Hartman
> Cc
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190618]
[cannot apply to v5.2-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
On Tue, Jun 18, 2019 at 08:25:52PM +0300, Ville Syrjälä wrote:
> On Fri, Jun 07, 2019 at 08:41:29PM +0300, Imre Deak wrote:
> > When enabling a TypeC port we need to reserve all the required PLLs for
> > it, the TBT PLL for TBT-alt and the MG PHY PLL for DP-alt/legacy sinks.
> > We can select the p
On Tue, Jun 18, 2019 at 07:32:20PM +0200, Daniel Vetter wrote:
> On Tue, Jun 18, 2019 at 5:25 PM Greg Kroah-Hartman
> wrote:
> > On Tue, Jun 18, 2019 at 05:19:38PM +0200, Greg Kroah-Hartman wrote:
> > > On Fri, Jun 14, 2019 at 10:36:14PM +0200, Daniel Vetter wrote:
> > > > Greg is busy already, bu
EHL has a mux on combo PHY A that allows it to be driven either by an
internal display (DDI-A or DSI DPHY) or by an external display (DDI-D).
This is a motherboard design decision that can not be changed on the
fly. Unfortunately there are no strap registers that allow us to detect
the board confi
On Tue, Jun 18, 2019 at 10:30:06AM -0700, Matt Roper wrote:
> On Tue, Jun 18, 2019 at 07:08:55PM +0300, Ville Syrjälä wrote:
> > On Mon, Jun 17, 2019 at 04:48:10PM -0700, Matt Roper wrote:
> > > EHL has a mux on combo PHY A that allows it to be driven either by an
> > > internal display (DDI-A or D
Quoting Tvrtko Ursulin (2019-06-18 17:58:02)
>
> On 18/06/2019 17:19, Chris Wilson wrote:
> > This has count me out on countless occasions, when we retrieve a pointer
> > from the submission/execlists backend, it does not carry a reference to
> > the context or ring. Those are only pinned while th
On Tue, Jun 18, 2019 at 5:25 PM Greg Kroah-Hartman
wrote:
> On Tue, Jun 18, 2019 at 05:19:38PM +0200, Greg Kroah-Hartman wrote:
> > On Fri, Jun 14, 2019 at 10:36:14PM +0200, Daniel Vetter wrote:
> > > Greg is busy already, but maybe he won't do everything ...
> > >
> > > Cc: Greg Kroah-Hartman
>
On Tue, Jun 18, 2019 at 07:08:55PM +0300, Ville Syrjälä wrote:
> On Mon, Jun 17, 2019 at 04:48:10PM -0700, Matt Roper wrote:
> > EHL has a mux on combo PHY A that allows it to be driven either by an
> > internal display (DDI-A or DSI DPHY) or by an external display (DDI-D).
> > This is a motherboar
Hi Chris,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20190618]
[cannot apply to v5.2-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url
On Fri, Jun 07, 2019 at 08:41:29PM +0300, Imre Deak wrote:
> When enabling a TypeC port we need to reserve all the required PLLs for
> it, the TBT PLL for TBT-alt and the MG PHY PLL for DP-alt/legacy sinks.
> We can select the proper PLL for the current port mode from the reserved
> PLLs only once
On 18/06/2019 17:19, Chris Wilson wrote:
This has count me out on countless occasions, when we retrieve a pointer
from the submission/execlists backend, it does not carry a reference to
the context or ring. Those are only pinned while the rquest is active,
so if we see the request is completed,
== Series Details ==
Series: series starting with [1/3] drm/i915/gtt: pde entry encoding is identical
URL : https://patchwork.freedesktop.org/series/62324/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6294 -> Patchwork_13331
===
On 18/06/2019 17:19, Chris Wilson wrote:
Be sure to cleanup after live_evict by flushing any residual state off
the GPU using igt_flush_test.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/dr
On Tue, Jun 18, 2019 at 10:26:52AM +0300, Laurent Pinchart wrote:
> Hi Sean,
>
> Thank you for the patch.
>
> On Mon, Jun 17, 2019 at 02:15:42PM -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > drm_atomic_get_crtc_state() returns an error pointer when it fails, so
> > the null check is doing
On Tue, Jun 18, 2019 at 07:39:09PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 04, 2019 at 05:58:18PM +0300, Imre Deak wrote:
> > Use hex numbers, since that makes more sense when decoding a bit pattern.
> >
> > No functional change.
> >
> > Suggested-by: Ville Syrjälä
> > Cc: Animesh Manna
> > C
On Tue, Jun 18, 2019 at 07:33:13PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 04, 2019 at 05:58:12PM +0300, Imre Deak wrote:
> > Factor out helpers reading/parsing the TypeC specific registers, making
> > current users of them clearer and letting us use them later.
> >
> > While at it also:
> > - S
On Tue, Jun 04, 2019 at 05:58:18PM +0300, Imre Deak wrote:
> Use hex numbers, since that makes more sense when decoding a bit pattern.
>
> No functional change.
>
> Suggested-by: Ville Syrjälä
> Cc: Animesh Manna
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/int
== Series Details ==
Series: series starting with [1/3] drm/i915/gtt: pde entry encoding is identical
URL : https://patchwork.freedesktop.org/series/62324/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/gtt: pde entry encoding is identical
-O:
Quoting Mika Kuoppala (2019-06-18 17:17:31)
> If we setup backing phys page for 3lvl pdps, even they
even though they
> are not used, we lose 5 pages per ppgtt.
>
> Trading this memory on bsw, we gain more common code paths for all
> gen8+ directory m
== Series Details ==
Series: series starting with [1/3] drm/i915/gtt: pde entry encoding is identical
URL : https://patchwork.freedesktop.org/series/62324/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
224a6de52ba2 drm/i915/gtt: pde entry encoding is identical
-:55: CHECK:MACRO
On 18/06/2019 16:19, Greg Kroah-Hartman wrote:
> On Fri, Jun 14, 2019 at 10:36:14PM +0200, Daniel Vetter wrote:
>> Greg is busy already, but maybe he won't do everything ...
>>
>> Cc: Greg Kroah-Hartman
>> Signed-off-by: Daniel Vetter
>> ---
>> Documentation/gpu/todo.rst | 3 +++
>> 1 file chan
Max backlight value for the panel was being calculated using byte
count i.e. 0x if 2 bytes are supported for backlight brightness
and 0xff if 1 byte is supported. However, EDP_PWMGEN_BIT_COUNT
determines the number of active control bits used for the brightness
setting. Thus, even if the panel
On 14/06/2019 16:34, Christoph Hellwig wrote:
On Fri, Jun 14, 2019 at 05:30:32PM +0200, Greg KH wrote:
On Fri, Jun 14, 2019 at 04:48:57PM +0200, Christoph Hellwig wrote:
On Fri, Jun 14, 2019 at 04:02:39PM +0200, Greg KH wrote:
Perhaps a hint as to how we can fix this up? This is the first tim
On Mon, 2019-06-17 at 15:47 -0700, Randy Dunlap wrote:
> Hi,
> Just a comment style nit below...
>
> On 6/16/19 7:04 PM, Alastair D'Silva wrote:
> > From: Alastair D'Silva
> >
> > This patch removes the hardcoded row limits and allows for
> > other lengths. These lengths must still be a multiple
There are three left-overs from the recent file renames,
probably due to some other conflicting patch.
Fix them.
Signed-off-by: Mauro Carvalho Chehab
---
This patch is against today's next-20190617 branch. Not sure if it
will apply cleanly at -docs tree. If not, Please let me know for me to
sp
On 18/06/2019 02:50, Patchwork wrote:
== Series Details ==
Series: Update whitelist support for new hardware (rev2)
URL : https://patchwork.freedesktop.org/series/62076/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6289 -> Patchwork_13319
==
On Tue, Jun 04, 2019 at 05:58:12PM +0300, Imre Deak wrote:
> Factor out helpers reading/parsing the TypeC specific registers, making
> current users of them clearer and letting us use them later.
>
> While at it also:
> - Simplify icl_tc_phy_connect() with an early return in legacy mode.
> - Simpl
Quoting Mika Kuoppala (2019-06-18 17:17:29)
> For all page directory entries, the pde encoding is
> identical. Don't compilicate call sites with different
> versions of doing the same thing. We check the existence of
> physical page before writing the entry into it. This further
> generalizes the p
Quoting Chris Wilson (2019-06-18 17:19:51)
> This has count me out on countless occasions, when we retrieve a pointer
> from the submission/execlists backend, it does not carry a reference to
> the context or ring. Those are only pinned while the rquest is active,
> so if we see the request is comp
== Series Details ==
Series: Update whitelist support for new hardware (rev2)
URL : https://patchwork.freedesktop.org/series/62076/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6289_full -> Patchwork_13319_full
Summary
---
Quoting Mika Kuoppala (2019-06-18 17:06:36)
> Chris Wilson writes:
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> > index c851c4029597..3a926a8755c6 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
> > +++ b/drivers/
This has count me out on countless occasions, when we retrieve a pointer
from the submission/execlists backend, it does not carry a reference to
the context or ring. Those are only pinned while the rquest is active,
so if we see the request is completed, it may be in the process of being
retired an
Be sure to cleanup after live_evict by flushing any residual state off
the GPU using igt_flush_test.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
b/drivers/g
If we setup backing phys page for 3lvl pdps, even they
are not used, we lose 5 pages per ppgtt.
Trading this memory on bsw, we gain more common code paths for all
gen8+ directory manipulation. And those paths are now void of checks
for page directory type, making the hot paths faster.
Signed-off-
We don't use common codepaths to setup and cleanup page
directories vs page tables. So their setup and cleanup macros
are of no use.
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
For all page directory entries, the pde encoding is
identical. Don't compilicate call sites with different
versions of doing the same thing. We check the existence of
physical page before writing the entry into it. This further
generalizes the pd so that manipulation in callsites will be
identical,
On 18/06/2019 14:43, John Harrison wrote:
On 6/17/2019 23:42, Tvrtko Ursulin wrote:
On 18/06/2019 02:01, john.c.harri...@intel.com wrote:
From: "Robert M. Fosha"
Updates the live_workarounds selftest to handle whitelisted
registers that are flagged as read only.
Signed-off-by: Robert M. Fos
On 18/06/2019 02:01, john.c.harri...@intel.com wrote:
From: John Harrison
Newer hardware adds flags to the whitelist work-around register. These
allow per access direction privileges and ranges.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
Signed-off-by: John Harrison
Signed-off-by: Rob
On Mon, Jun 17, 2019 at 04:48:10PM -0700, Matt Roper wrote:
> EHL has a mux on combo PHY A that allows it to be driven either by an
> internal display (DDI-A or DSI DPHY) or by an external display (DDI-D).
> This is a motherboard design decision that can not be changed on the
> fly. Unfortunately
Chris Wilson writes:
> Previously, we want to shrink the pages of freed objects before they
> were RCU collected. However, by removing the struct_mutex serialisation
> around the active reference, we need to acquire an extra reference
> around the wait. Unfortunately this means that we have to sk
On 18/06/2019 15:37, Ser, Simon wrote:
> On Tue, 2019-06-18 at 14:59 +0100, Guillaume Tucker wrote:
>> On 18/06/2019 14:20, Ser, Simon wrote:
>>> On Tue, 2019-06-18 at 13:27 +0100, Guillaume Tucker wrote:
Add conditional dependency on libatomic in order to be able to use the
__atomic_* fu
== Series Details ==
Series: prime doc polish and ... a few cleanups (rev6)
URL : https://patchwork.freedesktop.org/series/62135/
State : failure
== Summary ==
Applying: drm/todo: Update drm_gem_object_funcs todo even more
Applying: drm/gem: Unexport drm_gem_(un)pin/v(un)map
Using index info t
On Tue, Jun 18, 2019 at 03:54:01PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-06-18 15:21:07)
> [snip mechanical changes]
>
> > @@ -4839,65 +4792,18 @@ void intel_irq_init(struct drm_i915_private
> > *dev_priv)
> > dev->driver->get_vblank_timestamp =
> > drm_calc_vbltimesta
On Tue, Jun 18, 2019 at 05:19:38PM +0200, Greg Kroah-Hartman wrote:
> On Fri, Jun 14, 2019 at 10:36:14PM +0200, Daniel Vetter wrote:
> > Greg is busy already, but maybe he won't do everything ...
> >
> > Cc: Greg Kroah-Hartman
> > Signed-off-by: Daniel Vetter
> > ---
> > Documentation/gpu/todo.
On Tue, May 21, 2019 at 11:44:11AM -0400, Jerome Glisse wrote:
> On Mon, May 20, 2019 at 11:39:42PM +0200, Daniel Vetter wrote:
> > Just a bit of paranoia, since if we start pushing this deep into
> > callchains it's hard to spot all places where an mmu notifier
> > implementation might fail when i
On Fri, Jun 14, 2019 at 10:36:14PM +0200, Daniel Vetter wrote:
> Greg is busy already, but maybe he won't do everything ...
>
> Cc: Greg Kroah-Hartman
> Signed-off-by: Daniel Vetter
> ---
> Documentation/gpu/todo.rst | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/gpu
On Tue, Jun 18, 2019 at 03:46:29PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-06-18 15:21:06)
> > @@ -59,14 +57,13 @@ TRACE_EVENT(intel_pipe_disable,
> > ),
> >
> > TP_fast_assign(
> > - enum pipe _pipe;
> > -
== Series Details ==
Series: drm/i915: Finish drm_driver vfunc cleanup
URL : https://patchwork.freedesktop.org/series/62317/
State : failure
== Summary ==
Applying: drm/i915: Fix various tracepoints for gen2
Applying: drm/i915: Nuke drm_driver irq vfuncs
Using index info to reconstruct a base
1 - 100 of 269 matches
Mail list logo
