Quoting Tvrtko Ursulin (2019-05-23 07:43:12)
>
> On 23/05/2019 07:37, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Engine enumerated test names have changed so fast-feedback.testlist needs
> > to be updated. However listing all engines there won't scale. So instead
> > add new tests ca
We rearranged the vm_destroy_ioctl to avoid taking struct_mutex, little
realising that buried underneath the gen6 ppgtt release path was a
struct_mutex requirement (to remove its GGTT vma). Until that
struct_mutex is vanquished, take a detour in gen6_ppgtt_cleanup to do
the i915_vma_destroy from in
On 23/05/2019 07:37, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Engine enumerated test names have changed so fast-feedback.testlist needs
to be updated. However listing all engines there won't scale. So instead
add new tests cases which iterate all engines internally.
v2:
* Fix basic-all te
From: Tvrtko Ursulin
Engine enumerated test names have changed so fast-feedback.testlist needs
to be updated. However listing all engines there won't scale. So instead
add new tests cases which iterate all engines internally.
v2:
* Fix basic-all test name.
* Fix params to basic (bool false to
Hi Sean,
On Tue, 21 May 2019 10:51:51 +1000 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> Documentation/devicetree/bindings/vendor-prefixes.txt
>
> between commit:
>
> 8122de54602e ("dt-bindings: Convert vendor prefixes to json-schema")
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
include/drm/drm_mode_config.h
between commit:
585b000de23b ("drm: move content protection property to mode_config")
from the drm-intel tree and commit:
fbb5d0353c62 ("drm: Add HDR source metadata property")
from t
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/drm_atomic_uapi.c
between commit:
585b000de23b ("drm: move content protection property to mode_config")
from the drm-intel tree and commit:
fbb5d0353c62 ("drm: Add HDR source metadata property")
fr
On Wed, 22 May 2019 22:19:47 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-05-22 20:00:57)
Without breaking existing usage, slightly update HuC status codes
to provide more info to the clients:
1 if HuC firmware is loaded and verified,
0 if HuC firmware is not enabled,
-ENOPKG
On Fri, May 03, 2019 at 05:13:47PM -0700, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> >Manasi Navare
> >Sent: Tuesday, April 23, 2019 8:49 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Nikula, Jani
On Fri, May 03, 2019 at 05:09:20PM -0700, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> >Manasi Navare
> >Sent: Tuesday, April 23, 2019 8:49 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Daniel Vette
Hi Tvrtko,
> +static void all(int i915)
> +{
> + const struct intel_execution_engine2 *e;
> +
> + __for_each_physical_engine(i915, e)
> + basic(i915, e, false);
ops... there is an error in my previous patch.
I restored the meaining of flags because you and Chris didn't
like t
Hi Tvrtko,
On Wed, May 22, 2019 at 02:14:17PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This enables static test enumeration to see the engine.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Andi Shyti
Thanks,
Andi
___
Intel-gfx mail
Hi Tvrtko,
On Wed, May 22, 2019 at 02:32:39PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> commit c5d3e39caa456b1e061644b739131f2b54c84c08
> Author: Tvrtko Ursulin
> Date: Wed May 22 10:00:54 2019 +0100
>
> drm/i915: Engine discovery query
>
> Signed-off-by: Tvrtko Ur
Hi Tvrtko,
On Wed, May 22, 2019 at 05:06:58PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Otherwise debug output looks messy when we trigger this.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Andi Shyti
Reviewed-by: Andi Shyti
Thanks,
Andi
___
Hi Tvrtko,
On Wed, May 22, 2019 at 04:04:13PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Use from_user_pointer when casting __u64 to a pointer.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Andi Shyti
Reviewed-by: Andi Shyti
Thanks,
Andi
_
== Series Details ==
Series: GuC fixes (rev2)
URL : https://patchwork.freedesktop.org/series/60795/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6123 -> Patchwork_13075
Summary
---
**FAILURE**
Serious unknown cha
On Thu, May 16, 2019 at 07:40:05PM +0530, Uma Shankar wrote:
> This patch series enables HDR support in drm. It basically defines
> HDR metadata structures, property to pass content (after blending)
> metadata from user space compositors to driver.
>
> Dynamic Range and Mastering infoframe creatio
== Series Details ==
Series: GuC fixes (rev2)
URL : https://patchwork.freedesktop.org/series/60795/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
54ff1dca4c58 drm/i915/selftests: Move some reset testcases to separate file
-:95: WARNING:FILE_PATH_CHANGES: added, moved or deleted
Quoting Michal Wajdeczko (2019-05-22 20:00:57)
> Without breaking existing usage, slightly update HuC status codes
> to provide more info to the clients:
> 1 if HuC firmware is loaded and verified,
> 0 if HuC firmware is not enabled,
> -ENOPKG if HuC firmware is not loaded,
> -ENODEV if HuC is
Quoting Michal Wajdeczko (2019-05-22 20:00:56)
> During driver load we checked that HuC firmware was verified, and once
> verified it stays verified, so there is no need to check that again.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Tony Ye
Makes sense to me as purely a code
Quoting Michal Wajdeczko (2019-05-22 20:00:55)
> In gt_sanitize we reset whole GPU (and indirectly uC).
> Make sure we don't miss to run our dedicated uC sanitize code.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 ++
> drivers/gpu/drm
Quoting Michal Wajdeczko (2019-05-22 20:32:02)
> Knowing that GuC will be reset soon, we may stop all communication
> immediately without doing graceful cleanup as it is not needed.
The difference between stop and disable is that it avoids the
serialisation, right? Is this patch still required --
Quoting Michal Wajdeczko (2019-05-22 20:32:03)
> We may skip reset preparation steps if GuC is already sanitized.
>
> v2: replace USES_GUC with guc_is_loaded
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
-Chris
__
Quoting Michal Wajdeczko (2019-05-22 20:32:01)
> We should not attempt to unwind GuC hardware/firmware setup
> if we already have sanitized GuC.
>
> v2: replace USES_GUC with guc_is_loaded
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
Reviewed-by: Chris Wi
Quoting Michal Wajdeczko (2019-05-22 20:32:00)
> We already have helper function for checking GuC firmware
> load status. Replace existing open-coded checks.
>
> v2: drop redundant USES_GUC check
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
-Chris
__
Quoting Michal Wajdeczko (2019-05-22 20:31:59)
> Explicitly sanitize GuC/HuC on load failure and when we finish
> using them to make sure our fw state tracking is always correct.
>
> While around, use new helper in uc_reset_prepare.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: D
On Wed, May 22, 2019 at 01:38:18PM +0300, Jani Nikula wrote:
> On Tue, 21 May 2019, Nathan Chancellor wrote:
> > Hi Jani,
> >
> > On Mon, Apr 29, 2019 at 03:29:36PM +0300, Jani Nikula wrote:
> >> It used to be handy that we only had a couple of headers, but over time
> >> intel_drv.h has become un
On Wed, May 22, 2019 at 01:35:05PM +0300, Jani Nikula wrote:
> Fix the duplicate typedef for intel_wakeref_t leading to Clang build
> issues. While at it, actually make the intel_runtime_pm.h header
> self-contained, which was claimed in the commit being fixed.
>
> Reported-by: Nathan Chancellor
Quoting Michal Wajdeczko (2019-05-22 20:31:58)
> This function just check our software flag, while 'is_alive'
> may suggest that we are checking runtime firmware status.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/intel_guc.h
Quoting Michal Wajdeczko (2019-05-22 20:31:57)
> We were testing full GPU reset in atomic context without correctly
> wrapping it by prepare/finish steps. This could confuse our GuC
> reset handling code.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
-Chris
__
Quoting Michal Wajdeczko (2019-05-22 20:31:56)
> Split igt_atomic_reset selftests into separate full & engines parts,
> so we can move former to the dedicated reset selftests file.
>
> While here change engines test to loop first over atomic phases and
> then loop over available engines.
>
> Sign
Quoting Michal Wajdeczko (2019-05-22 20:31:55)
> igt_global_reset and igt_wedged_reset testcases are first candidates.
>
> Suggested-by: Chris Wilson
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c
> b/dri
== Series Details ==
Series: drm/i915: HuC updates
URL : https://patchwork.freedesktop.org/series/61001/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6122 -> Patchwork_13074
Summary
---
**SUCCESS**
No regressions
== Series Details ==
Series: series starting with [1/1] drm/i915: remove unused IO_TLB_SEGPAGES
which should be defined by swiotlb
URL : https://patchwork.freedesktop.org/series/60998/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6122 -> Patchwork_13073
=
The only detail of note here was that we were creating a fence from the
recursive batch, now supported by igt_spin_t (thanks Tvrtko).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
lib/igt_core.c | 1 +
lib/igt_dummyload.c |
Hi Da.*,
First -fixes pull, predictably light. The merge here was bringing over some
sun4i patches that missed the last -misc-next-fixes pull.
drm-misc-fixes-2019-05-22:
- sun4i fixes to hdmi phy as well as u16 overflow in dsi (left from -next-fixes)
- gma500 fix to make lvds detection more reli
We were testing full GPU reset in atomic context without correctly
wrapping it by prepare/finish steps. This could confuse our GuC
reset handling code.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 ++
1 file changed, 2 insertions(+)
diff --g
Split igt_atomic_reset selftests into separate full & engines parts,
so we can move former to the dedicated reset selftests file.
While here change engines test to loop first over atomic phases and
then loop over available engines.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/g
Explicitly sanitize GuC/HuC on load failure and when we finish
using them to make sure our fw state tracking is always correct.
While around, use new helper in uc_reset_prepare.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 1
We may skip reset preparation steps if GuC is already sanitized.
v2: replace USES_GUC with guc_is_loaded
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
We already have helper function for checking GuC firmware
load status. Replace existing open-coded checks.
v2: drop redundant USES_GUC check
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_uc.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff
This function just check our software flag, while 'is_alive'
may suggest that we are checking runtime firmware status.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc.h| 10 +-
drivers/gpu/drm/i915/intel_guc_sub
igt_global_reset and igt_wedged_reset testcases are first candidates.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_reset.c | 4 +
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 50
drivers/gpu/drm/i915/gt/s
Knowing that GuC will be reset soon, we may stop all communication
immediately without doing graceful cleanup as it is not needed.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.h | 5 +
drivers/gpu/drm/i915/intel_uc.c
We should not attempt to unwind GuC hardware/firmware setup
if we already have sanitized GuC.
v2: replace USES_GUC with guc_is_loaded
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
Misc GuC fixes for upcoming 32.0.3
v2: modified reset selftests
Michal Wajdeczko (9):
drm/i915/selftests: Move some reset testcases to separate file
drm/i915/selftests: Split igt_atomic_reset testcase
drm/i915/selftests: Use prepare/finish during atomic reset test
drm/i915/guc: Rename int
On Tue, May 21, 2019 at 04:24:58PM +0300, Ville Syrjälä wrote:
> On Mon, May 20, 2019 at 04:25:41PM -0700, Khaled Almahallawy wrote:
> > According to DP 1.4 standard, if the source supports four pre-emphasis
> > levels, then the source shall set the bit MAX_PRE-EMPHASIS_REACHED = 1 only
> > when
Test-with: <20190519201634.24816-1-michal.wajdec...@intel.com>
Michal Wajdeczko (3):
drm/i915/uc: Make uc_sanitize part of gt_sanitize
drm/i915/huc: Check HuC firmware status only once
drm/i915/huc: Update HuC status codes
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 ++
drivers/gpu/drm/i915
Without breaking existing usage, slightly update HuC status codes
to provide more info to the clients:
1 if HuC firmware is loaded and verified,
0 if HuC firmware is not enabled,
-ENOPKG if HuC firmware is not loaded,
-ENODEV if HuC is not present on this platform.
Signed-off-by: Michal Wajdec
During driver load we checked that HuC firmware was verified, and once
verified it stays verified, so there is no need to check that again.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc.c | 17 ++---
drivers/gpu/drm/i915/intel_huc.h
In gt_sanitize we reset whole GPU (and indirectly uC).
Make sure we don't miss to run our dedicated uC sanitize code.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 ++
drivers/gpu/drm/i915/i915_gem_pm.c| 1 -
2 files changed, 2 insertions(+),
== Series Details ==
Series: series starting with [CI,01/15] drm/i915: Split GEM object type
definition to its own header
URL : https://patchwork.freedesktop.org/series/60990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6121 -> Patchwork_13072
==
== Series Details ==
Series: fbcon notifier begone! (rev2)
URL : https://patchwork.freedesktop.org/series/60843/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6114_full -> Patchwork_13061_full
Summary
---
**SUCCESS**
On Tue, May 21, 2019 at 06:37:30PM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v5,1/2] drm/i915: Make sandybridge_pcode_read()
> deal with the second data register
> URL : https://patchwork.freedesktop.org/series/60921/
> State : success
>
> == Summary ==
>
== Series Details ==
Series: series starting with [CI,01/15] drm/i915: Split GEM object type
definition to its own header
URL : https://patchwork.freedesktop.org/series/60990/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Split GEM object t
== Series Details ==
Series: series starting with [CI,01/15] drm/i915: Split GEM object type
definition to its own header
URL : https://patchwork.freedesktop.org/series/60990/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
598f3d9e15d1 drm/i915: Split GEM object type definition
== Series Details ==
Series: series starting with [CI,01/10] drm/i915: Restore control over ppgtt
for context creation ABI
URL : https://patchwork.freedesktop.org/series/60931/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6115_full -> Patchwork_13066_full
===
== Series Details ==
Series: i915/gem_exec_fence: Replace open-coded recursive batch with igt_spin_t
URL : https://patchwork.freedesktop.org/series/60993/
State : failure
== Summary ==
CI Bug Log - changes from IGT_5005 -> IGTPW_3031
Summar
This patch removes IO_TLB_SEGPAGES which is no longer used since
commit 5584f1b1d73e ("drm/i915: fix i915 running as dom0 under Xen").
As the define of both IO_TLB_SEGSIZE and IO_TLB_SHIFT are from swiotlb,
IO_TLB_SEGPAGES should be defined on swiotlb side if it is required in the
future.
Signed-
Quoting Tvrtko Ursulin (2019-05-22 16:57:20)
> From: Tvrtko Ursulin
>
> New command line option to allow controling the initial pseudo random
> generator seed in order to allow repeatable runs.
>
> Signed-off-by: Tvrtko Ursulin
> Suggested-by: Chris Wilson
> Suggested-by: Simon Ser
Reviewed-
Quoting Tvrtko Ursulin (2019-05-22 16:57:19)
> From: Tvrtko Ursulin
>
> Back when gem_wsim used forking it was safe to use the common storage
> prng, but after converting to threads it no longer is.
>
> Fix by storing and using a new per workload seed for batch buffer
> duration randomness.
>
>
Quoting Tvrtko Ursulin (2019-05-22 17:31:41)
> From: Tvrtko Ursulin
>
> Engine enumerated test names have changed so fast-feedback.testlist needs
> to be updated. However listing all engines there won't scale. So instead
> add new tests cases which iterate all engines internally.
>
> Signed-off-
From: Tvrtko Ursulin
Engine enumerated test names have changed so fast-feedback.testlist needs
to be updated. However listing all engines there won't scale. So instead
add new tests cases which iterate all engines internally.
Signed-off-by: Tvrtko Ursulin
---
tests/i915/gem_busy.c
On 22/05/2019 16:57, Chris Wilson wrote:
The only detail of note here was that we were creating a fence from the
recursive batch, now supported by igt_spin_t (thanks Tvrtko).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Auld
Too quick for me,
Reviewed-by: Matthew Auld
== Series Details ==
Series: series starting with [1/4] drm/i915: move and rename register read
ioctl function declaration
URL : https://patchwork.freedesktop.org/series/60981/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6121 -> Patchwork_13071
=
Quoting Tvrtko Ursulin (2019-05-22 17:06:58)
> From: Tvrtko Ursulin
>
> Otherwise debug output looks messy when we trigger this.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Andi Shyti
> ---
> lib/i915/gem_engine_topology.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/
From: Tvrtko Ursulin
Otherwise debug output looks messy when we trigger this.
Signed-off-by: Tvrtko Ursulin
Cc: Andi Shyti
---
lib/i915/gem_engine_topology.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
ind
== Series Details ==
Series: drm/i915: remove duplicate typedef for intel_wakeref_t
URL : https://patchwork.freedesktop.org/series/60955/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6121 -> Patchwork_13069
Summary
---
From: Tvrtko Ursulin
A new workload command for enabling a load balanced context map (aka
Virtual Engine). Example usage:
B.1
This turns on load balancing for context one, assuming it has already been
configured with an engine map. Only DEFAULT engine specifier can be used
with load balanced
From: Tvrtko Ursulin
Engine bonds are an i915 uAPI applicable to load balanced contexts with
engine map. They allow expression rules of engine selection between two
contexts when submissions are also tied with submit fences.
Please refer to the README for a more detailed description.
v2:
* Use
From: Tvrtko Ursulin
We can improve the parsing loop readability a bit more by avoiding some
line breaks caused by explicit NULL checks.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
benchmarks/gem_wsim.c | 39 +++
1 file changed, 15 insertion
From: Tvrtko Ursulin
For simulating frame split workloads it is useful to express a batch which
ends at the same time as the parallel submission on the respective bonded
engine. For this we add support for infinite batch durations and the batch
terminate command ('T'). Syntax looks like this:
From: Tvrtko Ursulin
Back when gem_wsim used forking it was safe to use the common storage
prng, but after converting to threads it no longer is.
Fix by storing and using a new per workload seed for batch buffer
duration randomness.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 17
From: Tvrtko Ursulin
Support new i915 uAPI for configuring contexts with engine maps.
Please refer to the README file for more detailed explanation.
v2:
* Allow defining engine maps by class.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 211 +++-
From: Tvrtko Ursulin
On Icelake second vcs engine is vcs2 instead of vcs1 so add some logical
to physical instance remapping based on engine discovery to support it.
v2:
* Rebase.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
benchmarks/gem_wsim.c | 22 +-
The only detail of note here was that we were creating a fence from the
recursive batch, now supported by igt_spin_t (thanks Tvrtko).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Auld
---
tests/i915/gem_exec_fence.c | 74 ++---
1 file changed, 12 i
From: Tvrtko Ursulin
A new workload command ('S') is added which allows per context slice
(re-)configuration.
v2:
* Only query device SSEU on first use. (Chris)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
benchmarks/gem_wsim.c | 83 --
From: Tvrtko Ursulin
A new command line switch ('-s') is added which toggles the low slice
count mode for workloads following on the command line.
This enables easy benchmarking of the effect of running the existing media
workloads in parallel against another client. For example:
./gem_wsim -
From: Tvrtko Ursulin
This will allow applying the discovered engine configuration from a single
place.
v2:
* Consolidate enum to ci conversion.
Signed-off-by: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 163 --
1 file changed, 94 insertions(+), 69 delet
From: Tvrtko Ursulin
Parsing an integer workload descriptor field is a common pattern which we
can extract to a helper macro and by doing so further improve the
readability of the main parsing loop.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
benchmarks/gem_wsim.c | 80 +++
From: Tvrtko Ursulin
Instead of hardcoding the VCS balancing engines, discover, both with the
new engines query, or with the legacy get_param in the fallback case, so
class based addressing always works.
v2:
* Simplify has_engine_query check. (Andi)
* Fix assert on uninitialized variable. (And
From: Tvrtko Ursulin
To allow exercising the SSEU configuration in combination with Virtual
Engine, allow RCS to be specified in the engine map and use appropriate
index based addressing when applying SSEU configuration to it.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
benchm
From: Tvrtko Ursulin
A few additional workloads useful for experimenting with scheduling.
Signed-off-by: Tvrtko Ursulin
Acked-by: Chris Wilson
---
benchmarks/wsim/frame-split-60fps.wsim | 16
benchmarks/wsim/high-composited-game.wsim | 11 +++
benchmarks/wsim/m
From: Tvrtko Ursulin
Yet unmerged work with five unreviewed patches.
Tvrtko Ursulin (15):
gem_wsim: Engine map support
gem_wsim: Save some lines by changing to implicit NULL checking
gem_wsim: Compact int command parsing with a macro
gem_wsim: Engine map load balance command
gem_wsim:
From: Tvrtko Ursulin
New command line option to allow controling the initial pseudo random
generator seed in order to allow repeatable runs.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Suggested-by: Simon Ser
---
benchmarks/gem_wsim.c | 12 +---
1 file changed, 9 inserti
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev2)
URL : https://patchwork.freedesktop.org/series/60916/
State : failure
== Summary ==
Applying: drm/i915/perf: introduce a versioning of the i915-perf uapi
Applying: drm/i915/perf: allow holding preemption on filtered
Continuing the theme of separating out the GEM clutter.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile | 26 +--
drivers/gpu/drm/i915/Makefile.header-test | 2 -
.../gpu/drm/i915/{ => gem}/i915_gem_clflush.c | 24 ++
Continuing the decluttering of i915_gem.c by moving the object wait
decomposition into its own file.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 8 +
drivers/gpu/drm/i915/gem/i915_g
Split the plain old shmem object into its own file to start decluttering
i915_gem.c
v2: Lose the confusing, hysterical raisins, suffix of _gtt.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ob
Continuing the decluttering of i915_gem.c by moving the object busy
checking into its own file.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gem/i915_gem_busy.c | 138 +++
drivers/gpu/drm/i9
Declutter i915_drv/gem.h by moving the ioctl API into its own header.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_ioctls.h | 52 ++
drivers/gpu/drm/i915/i915_drv.c| 1 +
drivers/gpu/drm/i915/i915_drv.h|
Use the per-object local lock to control the cache domain of the
individual GEM objects, not struct_mutex. This is a huge leap forward
for us in terms of object-level synchronisation; execbuffers are
coordinated using the ww_mutex and pread/pwrite is finally fully
serialised again.
Signed-off-by:
Continuing the decluttering of i915_gem.c, now the turn of do_mmap and
the faulthandlers
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 504
drivers/gpu/drm/i915/ge
Currently the code for manipulating the pages on an object is still
residing in i915_gem.c, move it to i915_gem_object.c
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 4 +-
.../gpu/drm/i915/{ => gem}/i915_gem_obj
Continuing the decluttering of i915_gem.c, that of the read/write
domains, perhaps the biggest of GEM's follies?
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 782 +
Out scatterlist utility routines can be pulled out of i915_gem.h for a
bit more decluttering.
v2: Push I915_GTT_PAGE_SIZE out of i915_scatterlist itself and into the
caller.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers
Continuing the decluttering of i915_gem.c, this time the legacy physical
object.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_object.h| 11 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h
An old optimisation to reduce the number of atomics per batch sadly
relies on struct_mutex for coordination. In order to remove struct_mutex
from serialising object/context closing, always taking and releasing an
active reference on first use / last use greatly simplifies the locking.
Signed-off-b
For convenience in avoiding inline spaghetti, keep the type definition
as a separate header.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
Acked-by: Rodrigo Vivi
Acked-by: Jani Nikula
Acked-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm
Rename the engine this HW context is currently active upon (that we are
flying upon) to disambiguate between the mixture of different active
terms (and prevent conflict in future patches).
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_context_types.h |
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