[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data type to u32

== Series Details == Series: series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data type to u32 URL : https://patchwork.freedesktop.org/series/60007/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6007_full -> Patchwork_12886_full =

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: add in-kernel blitter client

== Series Details == Series: drm/i915: add in-kernel blitter client URL : https://patchwork.freedesktop.org/series/60017/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12889 Summary --- **FAILURE**

Re: [Intel-gfx] [PATCH] drm/i915: add in-kernel blitter client

Quoting Matthew Auld (2019-04-26 23:17:05) > The plan is to use the blitter engine for async object clearing when > using local memory, but before we can move the worker to get_pages() we > have to first tame some more of our struct_mutex usage. With this in > mind we should be able to upstream the

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add in-kernel blitter client

== Series Details == Series: drm/i915: add in-kernel blitter client URL : https://patchwork.freedesktop.org/series/60017/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: add in-kernel blitter client +drivers/gpu/drm/i915/i915_gem_client_blt.h:

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add in-kernel blitter client

== Series Details == Series: drm/i915: add in-kernel blitter client URL : https://patchwork.freedesktop.org/series/60017/ State : warning == Summary == $ dim checkpatch origin/drm-tip 658ea31e573a drm/i915: add in-kernel blitter client -:43: CHECK:SPACING: spaces preferred around that '<<' (ct

[Intel-gfx] [PATCH] drm/i915: add in-kernel blitter client

The plan is to use the blitter engine for async object clearing when using local memory, but before we can move the worker to get_pages() we have to first tame some more of our struct_mutex usage. With this in mind we should be able to upstream the object clearing as some selftests, which should se

[Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor to expand subslice mask (rev3)

== Series Details == Series: Refactor to expand subslice mask (rev3) URL : https://patchwork.freedesktop.org/series/59742/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC

[Intel-gfx] [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h

Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.h | 47 drivers/gpu/drm/i915/intel_device_info.h | 47 2 files changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/dr

[Intel-gfx] [PATCH 0/5] Refactor to expand subslice mask

This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice

[Intel-gfx] [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function

Add a new function to return the number of subslices per slice to consolidate code usage. v2: rebase on changes to move sseu struct to intel_sseu.h Cc: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++ drivers/gpu/drm/i915/i915_debugf

[Intel-gfx] [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation

Subslice stride and EU stride are calculated multiple times in i915_query. Move this calculation to a macro to reduce code duplication. Cc: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_sseu.h | 1 + drivers/gpu/drm/i915/i915_query.c| 17 ---

[Intel-gfx] [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl

In the GETPARAM ioctl handler, use a local variable to consolidate usage of SSEU runtime info. Cc: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/i915_drv.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_d

[Intel-gfx] [PATCH 5/5] drm/i915: Expand subslice mask

Currently, the subslice_mask runtime parameter is stored as an array of subslices per slice. Expand the subslice mask array to better match what is presented to userspace through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is then calculated: slice * subslice stride + subslice i

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/execlists: Flush the tasklet on parking

== Series Details == Series: series starting with [1/3] drm/i915/execlists: Flush the tasklet on parking URL : https://patchwork.freedesktop.org/series/60008/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12887 ===

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/execlists: Flush the tasklet on parking

== Series Details == Series: series starting with [1/3] drm/i915/execlists: Flush the tasklet on parking URL : https://patchwork.freedesktop.org/series/60008/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Flush the tasklet on park

Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color

On Fri, Apr 26, 2019 at 11:53:54AM -0700, Aditya Swarup wrote: > On Fri, Apr 26, 2019 at 09:41:06PM +0300, Ville Syrjälä wrote: > > On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote: > > > On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote: > > > > On Thu, Apr 25, 2019 at 06:

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data type to u32

== Series Details == Series: series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data type to u32 URL : https://patchwork.freedesktop.org/series/60007/ State : success == Summary == CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12886 ===

Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color

On Fri, Apr 26, 2019 at 09:41:06PM +0300, Ville Syrjälä wrote: > On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote: > > On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote: > > > On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote: > > > > From: Clinton Taylor > > >

Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color

On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote: > On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote: > > On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote: > > > From: Clinton Taylor > > > > > > v2: Fix commit msg to reflect why issue occurs(Jani) > > > Set

Re: [Intel-gfx] [PATCH v7] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color

On Fri, Apr 26, 2019 at 01:12:58PM +0300, Ville Syrjälä wrote: > On Thu, Apr 25, 2019 at 01:44:37PM -0700, Aditya Swarup wrote: > > On Wed, Apr 17, 2019 at 12:57:44PM +0300, Jani Nikula wrote: > > > On Fri, 05 Apr 2019, Aditya Swarup wrote: > > > > From: Clinton Taylor > > > > > > > > v2: Fix com

Re: [Intel-gfx] [PATCH 3/3] drm/i915/icl: Add Multi-segmented gamma support

On Fri, Apr 26, 2019 at 11:31:51PM +0530, Shashank Sharma wrote: > ICL introduces a new gamma correction mode in display engine, called > multi-segmented-gamma mode. This mode allows users to program the > darker region of the gamma curve with sueprfine precision. An > example use case for this is

Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color

On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote: > On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote: > > From: Clinton Taylor > > > > v2: Fix commit msg to reflect why issue occurs(Jani) > > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color. > > > > Changi

[Intel-gfx] [PATCH 3/3] drm/i915: Convert inconsistent static engine tables into an init error

Remove the modification of the "constant" device info by promoting the inconsistent intel_engine static table into an initialisation error. Now, if we add a new engine into the device_info, we must first add that engine information into the intel_engines. Signed-off-by: Chris Wilson --- drivers/

[Intel-gfx] [PATCH 2/3] drm/i915: Move the engine->destroy() vfunc onto the engine

Make the engine responsible for cleaning itself up! This removes the i915->gt.cleanup vfunc that has been annoying the casual reader and myself for the last several years, and helps keep a future patch to add more cleanup tidy. v2: Assert that engine->destroy is set after the backend starts alloc

[Intel-gfx] [PATCH 1/3] drm/i915/execlists: Flush the tasklet on parking

Tidy up the cleanup sequence by always ensure that the tasklet is flushed on parking (before we cleanup). The parking provides a convenient point to ensure that the backend is truly idle. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++-- driv

Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Add register definitions for Multi Segmented gamma

On Fri, Apr 26, 2019 at 11:31:50PM +0530, Shashank Sharma wrote: > From: Uma Shankar > > Add macros to define multi segmented gamma registers > > Cc: Ville Syrjälä > Cc: Maarten Lankhorst > Signed-off-by: Uma Shankar > --- > drivers/gpu/drm/i915/i915_reg.h | 17 + > 1 file ch

[Intel-gfx] [PATCH 3/3] drm/i915/icl: Add Multi-segmented gamma support

ICL introduces a new gamma correction mode in display engine, called multi-segmented-gamma mode. This mode allows users to program the darker region of the gamma curve with sueprfine precision. An example use case for this is HDR curves (like PQ ST-2084). If we plot a gamma correction curve from v

[Intel-gfx] [PATCH 2/3] drm/i915/icl: Add register definitions for Multi Segmented gamma

From: Uma Shankar Add macros to define multi segmented gamma registers Cc: Ville Syrjälä Cc: Maarten Lankhorst Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 17 + 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/d

[Intel-gfx] [PATCH 1/3] drm/i915: Change gamma/degamma_lut_size data type to u32

Currently, data type of gamma_lut_size & degamma_lut_size elements in intel_device_info is u16, which means it can accommodate maximum 64k values. In case of ICL multisegmented gamma, the size of gamma LUT is 256K. This patch changes the data type of both of these elements to u32. Cc: Ville Syrjä

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts

== Series Details == Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/60004/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6006 -> Patchwork_12885

Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1

On Thu, Apr 18, 2019 at 3:06 AM Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin > > WaEnableStateCacheRedirectToCS context workaround configures the L3 cache > to benefit 3d workloads but media has different requirements. > > Remove the workaround and whitelist the register to allow any userspace

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts

== Series Details == Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/60004/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/gvt: Pin the per-engine GVT s

Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1

Joonas, Mesa now applies this WA on ICL and we're not seeing any regressions in CI. I tested Mesa with and without this patch applied to kernel. I don't see any performance impact to Manhattan from GfxBench5. I'm little surprised to see it's not really helping benchmark performance in Mesa. I'll

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts

== Series Details == Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/60004/ State : warning == Summary == $ dim checkpatch origin/drm-tip df18fb0cb42a drm/i915/gvt: Pin the per-engine GVT shadow contexts

[Intel-gfx] [CI 4/9] drm/i915/selftests: Pass around intel_context for sseu

Combine the (i915_gem_context, intel_engine) into a single parameter, the intel_context for convenience and later simplification. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- .../gpu/drm/i915/selftests/i915_gem_context.c | 74 +++ 1 file changed, 44 insertions(+),

[Intel-gfx] [CI 7/9] drm/i915: Switch back to an array of logical per-engine HW contexts

We switched to a tree of per-engine HW context to accommodate the introduction of virtual engines. However, we plan to also support multiple instances of the same engine within the GEM context, defeating our use of the engine as a key to looking up the HW context. Just allocate a logical per-engine

[Intel-gfx] [CI 5/9] drm/i915: Pass intel_context to intel_context_pin_lock()

Move the intel_context_instance() to the caller so that we can decouple ourselves from one context instance per engine. v2: Rename pin_lock() to lock_pinned(), hopefully that is clearer. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_context.c |

[Intel-gfx] [CI 3/9] drm/i915/selftests: Use the real kernel context for sseu isolation tests

Simply the setup slightly for the sseu selftests to use the actual kernel_context. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- .../gpu/drm/i915/selftests/i915_gem_context.c | 17 - 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i

[Intel-gfx] [CI 9/9] drm/i915: Move i915_request_alloc into selftests/

Having transitioned GEM over to using intel_context as its primary means of tracking the GEM context and engine combined and using i915_request_create(), we can move the older i915_request_alloc() helper function into selftests/ where the remaining users are confined. Signed-off-by: Chris Wilson

[Intel-gfx] [CI 8/9] drm/i915: Remove intel_context.active_link

We no longer need to track the active intel_contexts within each engine, allowing us to drop a tricky mutex_lock from inside unpin (which may occur inside fs_reclaim). Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_context.c | 11 +--

[Intel-gfx] [CI 6/9] drm/i915: Split engine setup/init into two phases

In the next patch, we require the engine vfuncs setup prior to initialising the pinned kernel contexts, so split the vfunc setup from the engine initialisation and call it earlier. v2: s/setup_xcs/setup_common/ for intel_ring_submission_setup() Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Urs

[Intel-gfx] [CI 2/9] drm/i915: Export intel_context_instance()

We want to pass in a intel_context into intel_context_pin() and that requires us to first be able to lookup the intel_context! Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_context.c| 37 +++--- drivers/gpu/drm/i915/gt/intel_contex

[Intel-gfx] [CI 1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts

Our eventual goal is to rid request construction of struct_mutex, with the short term step of lifting the struct_mutex requirements into the higher levels (i.e. the caller must ensure that the context is already pinned into the GTT). In this patch, we pin GVT's shadow context upon allocation and so

[Intel-gfx] [PATCH xf86-video-intel v2 2/2] sna: Support 10bpc gamma via the GAMMA_LUT crtc property

From: Ville Syrjälä Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when the running with > 8bpc. v2: s/sna_crtc_id/__sna_crtc_id/ in DBG since we have a sna_crtc Cc: Mario Kleiner Signed-off-by: Ville Syrjälä --- src/sna/sna_display.c | 245 +++-

[Intel-gfx] [PATCH xf86-video-intel v2 1/2] sna: Refactor property parsing

From: Ville Syrjälä Generalize the code that parses the plane properties to be useable for crtc (or any kms object) properties as well. v2: plane 'type' prop is enum not range! Cc: Mario Kleiner Signed-off-by: Ville Syrjälä --- src/sna/sna_display.c | 69 ++---

Re: [Intel-gfx] [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+

On Fri, Apr 26, 2019 at 04:01:02PM +0100, Chris Wilson wrote: > Quoting Ville Syrjälä (2019-04-26 15:54:54) > > On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote: > > > On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote: > > > > Quoting Ville Syrjala (2019-04-15 15:16:41) > >

Re: [Intel-gfx] [PATCH v2] drm: prefix header search paths with $(srctree)/

On Fri, Apr 26, 2019 at 12:56:48PM +1000, Dave Airlie wrote: > Daniel, drm-misc-next-fixes? Makes sense. Pushed. Cheers, Daniel > > Dave. > > On Fri, 26 Apr 2019 at 12:25, wrote: > > > > Hi Dave, > > > > > -Original Message- > > > From: Dave Airlie [mailto:airl...@gmail.com] > > > Sen

Re: [Intel-gfx] [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+

Quoting Ville Syrjälä (2019-04-26 15:54:54) > On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote: > > On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote: > > > Quoting Ville Syrjala (2019-04-15 15:16:41) > > > > From: Ville Syrjälä > > > > > > > > Since SKL the eLLC has been

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_tiling_max_stride: Skip if chipset is unknown

On Fri, Apr 26, 2019 at 08:56:45AM +0100, Chris Wilson wrote: > If we can't match the devid to a chipset, we do not have a reference for > the tiling strides. Instead of randomly failing, skip with a > semi-informative message. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110523 > Si

Re: [Intel-gfx] [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+

On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote: > On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote: > > Quoting Ville Syrjala (2019-04-15 15:16:41) > > > From: Ville Syrjälä > > > > > > Since SKL the eLLC has been sitting on the far side of the system > > > agent, meani

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband

== Series Details == Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59980/ State : success == Summary == CI Bug Log - changes from CI_DRM_6002_full -> Patchwork_12884_full ==

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used

On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote: > > On 4/13/2019 12:00 AM, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > The pipe has a special HDR mode with higher precision when only > > HDR planes are active. Let's use it. > > > > Curiously this fixes the kms_color gam

Re: [Intel-gfx] [PATCH] drm/i915: Clean up cherryview_load_luts()

Reviewed-by: Swati Sharma Thanks and Regards, Swati -Original Message- From: Intel-gfx On Behalf Of Ville Syrjala Sent: Monday, April 8, 2019 5:48 PM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH] drm/i915: Clean up cherryview_load_luts() From: Ville Syrjälä I like

Re: [Intel-gfx] [PATCH] drm/i915: Fix ICL output CSC programming

Reviewed-by: Swati Sharma Thanks and Regards, Swati -Original Message- From: Intel-gfx On Behalf Of Ville Syrjala Sent: Friday, April 26, 2019 12:54 AM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH] drm/i915: Fix ICL output CSC programming From: Ville Syrjälä When

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts

== Series Details == Series: series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/59970/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6002_full -> Patchwork_12883_full =

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used

On 4/13/2019 12:00 AM, Ville Syrjala wrote: From: Ville Syrjälä The pipe has a special HDR mode with higher precision when only HDR planes are active. Let's use it. Curiously this fixes the kms_color gamma/degamma tests when using a HDR plane, which is always the case unless one hacks the tes

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev7)

== Series Details == Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev7) URL : https://patchwork.freedesktop.org/series/58912/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6001_full -> Patchwork_12881_full =

Re: [Intel-gfx] [PATCH 24/45] drm/i915: Split GEM object type definition to its own header

On Thu, 25 Apr 2019, Chris Wilson wrote: > For convenience in avoiding inline spaghetti, keep the type definition > as a separate header. > > Signed-off-by: Chris Wilson > Reviewed-by: Matthew Auld > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/gem/Makefil

Re: [Intel-gfx] [PATCH 01/45] drm/i915: Seal races between async GPU cancellation, retirement and signaling

On 25/04/2019 11:42, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-04-25 11:35:01) On 25/04/2019 10:19, Chris Wilson wrote: Currently there is an underlying assumption that i915_request_unsubmit() is synchronous wrt the GPU -- that is the request is no longer in flight as we remove it. In

Re: [Intel-gfx] [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context

Quoting Ville Syrjälä (2019-04-23 16:36:47) > On Fri, Apr 19, 2019 at 12:17:47PM +0100, Chris Wilson wrote: > > Despite what I think the prm recommends, commit f2253bd9859b > > ("drm/i915/ringbuffer: EMIT_INVALIDATE after switch context") turned out > > to be a huge mistake when enabling Ironlake c

Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color

On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote: > From: Clinton Taylor > > v2: Fix commit msg to reflect why issue occurs(Jani) > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color. > > Changing settings from 10/12 bit deep color to 8 bit(& vice versa) > doesn't work c

Re: [Intel-gfx] [PATCH v7] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color

On Thu, Apr 25, 2019 at 01:44:37PM -0700, Aditya Swarup wrote: > On Wed, Apr 17, 2019 at 12:57:44PM +0300, Jani Nikula wrote: > > On Fri, 05 Apr 2019, Aditya Swarup wrote: > > > From: Clinton Taylor > > > > > > v2: Fix commit msg to reflect why issue occurs(Jani) > > > Set GCP_COLOR_INDICATION on

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915: Introduce intel_irq

== Series Details == Series: series starting with [1/7] drm/i915: Introduce intel_irq URL : https://patchwork.freedesktop.org/series/59958/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12880_full Sum

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks

== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks URL : https://patchwork.freedesktop.org/series/59956/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12879_full

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix ICL output CSC programming

== Series Details == Series: drm/i915: Fix ICL output CSC programming URL : https://patchwork.freedesktop.org/series/59955/ State : success == Summary == CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12878_full Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband

== Series Details == Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59980/ State : success == Summary == CI Bug Log - changes from CI_DRM_6002 -> Patchwork_12884

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband

== Series Details == Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59980/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Disable

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband

== Series Details == Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59980/ State : warning == Summary == $ dim checkpatch origin/drm-tip ab284a305f9c drm/i915: Disable preemption and

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/icl: Factor out combo PHY lane power setup helper

== Series Details == Series: series starting with [v2,1/2] drm/i915/icl: Factor out combo PHY lane power setup helper URL : https://patchwork.freedesktop.org/series/59954/ State : success == Summary == CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12877_full

Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1

+ Anuj Quoting Lionel Landwerlin (2019-04-26 11:13:58) > On 18/04/2019 18:06, Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin > > > > WaEnableStateCacheRedirectToCS context workaround configures the L3 cache > > to benefit 3d workloads but media has different requirements. > > > > Remove the worka

Re: [Intel-gfx] [PATCH v3 0/9] drm/i915/perf: add OA interrupt support

FYI, MDAPI got tired of waiting for this to land upstream : https://github.com/intel/metrics-discovery/commit/7b6399d5d5e5ef5fcc018a48853b46d0803da441 Apart from squashing the last commit, any other change needed? Thanks, -Lionel On 03/04/2019 00:36, Lionel Landwerlin wrote: On 02/04/2019

[Intel-gfx] [CI 5/8] drm/i915: Separate sideband declarations to intel_sideband.h

Split the sideback declarations out of the ginormous i915_drv.h Signed-off-by: Chris Wilson Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/Makefile.header-test | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 120

[Intel-gfx] [CI 8/8] drm/i915: Move sandybride pcode access to intel_sideband.c

sandybride_pcode is another sideband, so move it to their new home. Signed-off-by: Chris Wilson Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 10 -- drivers/gpu/drm/i915/intel_hdcp.c | 1 + drivers/gpu/drm/i915/intel_pm.c | 195 - dr

[Intel-gfx] [CI 6/8] drm/i915: Merge sbi read/write into a single accessor

Since intel_sideband_read and intel_sideband_write differ by only a couple of lines (depending on whether we feed the value in or out), merge the two into a single common accessor. v2: Restore vlv_flisdsi_read() lost during rebasing. Signed-off-by: Chris Wilson Reviewed-by: Ville Syrjälä --- d

[Intel-gfx] [CI 4/8] drm/i915: Replace pcu_lock with sb_lock

We now have two locks for sideband access. The general one covering sideband access across all generation, sb_lock, and a specific one covering sideband access via the punit on vlv/chv. After lifting the sb_lock around the punit into the callers, the pcu_lock is now redudant and can be separated fr

[Intel-gfx] [CI 7/8] drm/i915: Merge sandybridge_pcode_(read|write)

These routines are identical except in the nature of the value parameter. For writes it is a pure in-param, but for a read, we need an out-param. Since they differ in a single line, merge the two routines into one. Signed-off-by: Chris Wilson Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/inte

[Intel-gfx] [CI 3/8] drm/i915: Lift sideband locking for vlv_punit_(read|write)

Lift the sideband acquisition for vlv_punit_read and vlv_punit_write into their callers, so that we can lock the sideband once for a sequence of operations, rather than perform the heavyweight acquisition on each request. Signed-off-by: Chris Wilson Reviewed-by: Ville Syrjälä --- drivers/gpu/dr

[Intel-gfx] [CI 2/8] drm/i915: Lift acquiring the vlv punit magic to a common sb-get

As we now employ a very heavy pm_qos around the punit access, we want to minimise the number of synchronous requests by performing one for the whole punit sequence rather than around individual accesses. The sideband lock is used for this, so push the pm_qos into the sideband lock acquisition and r

[Intel-gfx] [CI 1/8] drm/i915: Disable preemption and sleeping while using the punit sideband

While we talk to the punit over its sideband, we need to prevent the cpu from sleeping in order to prevent a potential machine hang. Note that by itself, it appears that pm_qos_update_request (via intel_idle) doesn't provide a sufficient barrier to ensure that all core are indeed awake (out of Cst

Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1

On 18/04/2019 18:06, Tvrtko Ursulin wrote: From: Tvrtko Ursulin WaEnableStateCacheRedirectToCS context workaround configures the L3 cache to benefit 3d workloads but media has different requirements. Remove the workaround and whitelist the register to allow any userspace configure the behaviou

[Intel-gfx] [PATCH i-g-t] i915/gem_tiling_max_stride: Skip if chipset is unknown

If we can't match the devid to a chipset, we do not have a reference for the tiling strides. Instead of randomly failing, skip with a semi-informative message. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110523 Signed-off-by: Chris Wilson --- tests/i915/gem_tiling_max_stride.c | 16 ++

Re: [Intel-gfx] [PATCH] drm/i915: Fix ICL output CSC programming

On Thu, Apr 25, 2019 at 12:24 PM Ville Syrjala wrote: > > From: Ville Syrjälä > > When I refactored the code into its own function I accidentally > misplaced the <<16 shifts for some of the registers causing us > to lose the blue channel entirely. > > We should really find a way to test this... >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts

== Series Details == Series: series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/59970/ State : success == Summary == CI Bug Log - changes from CI_DRM_6002 -> Patchwork_12883 ===