== Series Details ==
Series: series starting with [01/10] drm/i915: Seal races between async GPU
cancellation, retirement and signaling
URL : https://patchwork.freedesktop.org/series/59912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c9843a19934a drm/i915: Seal races between
Hi Dave & Daniel,
Just one use-after-free fix and Icelake DP programming fix.
Best Regards, Joonas
***
drm-intel-next-fixes-2019-04-25:
- Use after free fix during GEM_CREATE when reporting back object size
- Icelake DP register programming order fix
The following changes since commit 6ecac85
== Series Details ==
Series: drm/i915: Seal races between async GPU cancellation, retirement and
signaling (rev2)
URL : https://patchwork.freedesktop.org/series/59584/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5990_full -> Patchwork_12861_full
From: Dongwon Kim
Setting bit5 (headerless msg for preemptable GPGPU context) of SAMPLER_MODE
register to enable support for the headless msgs on gen11. None of existing
use cases will be affected by this as this change makes both types of message
- headerless and w/ header supported at the same
We want to pass in a intel_context into intel_context_pin() and that
requires us to first be able to lookup the intel_context!
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c| 37 +++---
drivers/gpu/drm/i915/gt/intel_contex
We no longer need to track the active intel_contexts within each engine,
allowing us to drop a tricky mutex_lock from inside unpin (which may
occur inside fs_reclaim).
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 11 +--
Simply the setup slightly for the sseu selftests to use the actual
kernel_context.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i
Our eventual goal is to rid request construction of struct_mutex, with
the short term step of lifting the struct_mutex requirements into the
higher levels (i.e. the caller must ensure that the context is already
pinned into the GTT). In this patch, we pin GVT's shadow context upon
allocation and so
Combine the (i915_gem_context, intel_engine) into a single parameter,
the intel_context for convenience and later simplification.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 74 +++
1 file changed, 44 insertions(+),
Currently there is an underlying assumption that i915_request_unsubmit()
is synchronous wrt the GPU -- that is the request is no longer in flight
as we remove it. In the near future that may change, and this may upset
our signaling as we can process an interrupt for that request while it
is no long
In the next patch, we require the engine vfuncs setup prior to
initialising the pinned kernel contexts, so split the vfunc setup from
the engine initialisation and call it earlier.
v2: s/setup_xcs/setup_common/ for intel_ring_submission_setup()
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Urs
Move the intel_context_instance() to the caller so that we can decouple
ourselves from one context instance per engine.
v2: Rename pin_lock() to lock_pinned(), hopefully that is clearer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c |
It was noted that we made the same mistake for VM_ID as for object
handles, whereby we ensured that we only allocated a single handle for
one ppgtt. This has the unfortunate consequence for userspace that they
need to reference count the handles to avoid destroying an active ID. If
we allow multipl
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
multiple instances of the same engine within the GEM context, defeating
our use of the engine as a key to looking up the HW context. Just
allocate a logical per-engine
Having transitioned GEM over to using intel_context as its primary means
of tracking the GEM context and engine combined and using
i915_request_create(), we can move the older i915_request_alloc()
helper function into selftests/ where the remaining users are confined.
Signed-off-by: Chris Wilson
== Series Details ==
Series: drm/i915: Explicitly pin the logical context for execbuf
URL : https://patchwork.freedesktop.org/series/59911/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5994 -> Patchwork_12866
Summary
-
In order to separate the reservation phase of building a request from
its emission phase, we need to pull some of the request alloc activities
from deep inside i915_request to the surface, GEM_EXECBUFFER.
v2: Be frivolous, use a local drm_i915_private..
Signed-off-by: Chris Wilson
Reviewed-by: T
== Series Details ==
Series: drm/i915/selftests: Verify whitelist of context registers (rev3)
URL : https://patchwork.freedesktop.org/series/59870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5989_full -> Patchwork_12860_full
=
== Series Details ==
Series: drm/i915: Store the default sseu setup on the engine
URL : https://patchwork.freedesktop.org/series/59869/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5987_full -> Patchwork_12859_full
Summary
Hi Dave and Daniel,
This has been a very quiet week. The only 2 patches here
was queued last week.
drm-intel-fixes-2019-04-24:
A fix for display lanes calculation for BXT and a protection
to avoid enabling FEC without DSC.
Thanks,
Rodrigo.
The following changes since commit 3f5f5d534bd40b666cf
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Introduce struct intel_wakeref
URL : https://patchwork.freedesktop.org/series/59904/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5992 -> Patchwork_12865
Hi Da.*,
First pull from -next-fixes for 5.2. Mostly lease fixes from Daniel with a NULL
deref from Noralf.
Please pull!
drm-misc-next-fixes-2019-04-24:
- fb_helper: Fix NULL deref in legacy drivers (Noralf)
- leases: Ensure lessees can't connect to objects outside their perview (Daniel)
- leas
Setting bit5 (headerless msg for preemptable GPGPU context) of SAMPLER_MODE
register to enable support for the headless msgs on gen11. None of existing
use cases will be affected by this as this change makes both types of message
- headerless and w/ header supported at the same time. It also compli
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Introduce struct intel_wakeref
URL : https://patchwork.freedesktop.org/series/59904/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Introduce struct intel_wakeref
-drivers/g
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Introduce struct intel_wakeref
URL : https://patchwork.freedesktop.org/series/59904/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a7bf2659e2d4 drm/i915: Introduce struct intel_wakeref
-:65: WARNING:FILE_PATH_
Quoting Dongwon Kim (2019-04-24 21:38:57)
> Setting bit5 (headerless msg for preemptable GPGPU context) of SAMPLER_MODE
> register to enable support for the headless msgs on gen11. None of existing
> use cases will be affected by this as this change makes both types of message
> - headerless and w/
Setting bit5 (headerless msg for preemptable GPGPU context) of SAMPLER_MODE
register to enable support for the headless msgs on gen11. None of existing
use cases will be affected by this as this change makes both types of message
- headerless and w/ header supported at the same time. It also compli
On Thu, Apr 18, 2019 at 10:41:38AM +0200, Thomas Gleixner wrote:
> Replace the indirection through struct stack_trace by using the storage
> array based interfaces and storing the information is a small lockdep
> specific data structure.
>
Acked-by: Peter Zijlstra (Intel)
___
Em qua, 2019-04-24 às 20:58 +0100, Chris Wilson escreveu:
> Quoting Jian-Hong Pan (2019-04-23 10:28:10)
> > From: Daniel Drake
> >
> > On many (all?) the Gemini Lake systems we work with, there is frequent
> > momentary graphical corruption at the top of the screen, and it seems
> > that disablin
We wish to start segregating the power management into different control
domains, both with respect to the hardware and the user interface. The
first step is that at the lowest level flow of requests, we want to
process a context event (and not a global GEM operation). In this patch,
we introduce t
Start acquiring the logical intel_context and using that as our primary
means for request allocation. This is the initial step to allow us to
avoid requiring struct_mutex for request allocation along the
perma-pinned kernel context, but it also provides a foundation for
breaking up the complex requ
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the h
Split out the powermanagement portion (GT wakeref, suspend/resume) of
GEM from i915_gem.c into its own file.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/Makefile.header-test | 1 +
drivers/gpu/drm/
For controlling runtime pm of the GT and engines, we would like to have
a callback to do extra work the first time we wake up and the last time
we drop the wakeref. This first/last access needs serialisation and so
we encompass a mutex with the regular intel_wakeref_t tracker.
v2: Drop the _once n
== Series Details ==
Series: drm/i915/fbdev: Actually configure untiled displays (rev2)
URL : https://patchwork.freedesktop.org/series/56728/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5985_full -> Patchwork_12858_full
S
Quoting Jian-Hong Pan (2019-04-23 10:28:10)
> From: Daniel Drake
>
> On many (all?) the Gemini Lake systems we work with, there is frequent
> momentary graphical corruption at the top of the screen, and it seems
> that disabling framebuffer compression can avoid this.
>
> The ticket was reported
== Series Details ==
Series: drm/i915: Move GraphicsTechnology files under gt/
URL : https://patchwork.freedesktop.org/series/59900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5991 -> Patchwork_12864
Summary
---
*
On Wed, 24 Apr 2019, Peter Zijlstra wrote:
> On Thu, Apr 18, 2019 at 10:41:37AM +0200, Thomas Gleixner wrote:
> > There is only one caller of check_prev_add() which hands in a zeroed struct
> > stack trace and a function pointer to save_stack(). Inside check_prev_add()
> > the stack_trace struct is
On Thu, Apr 18, 2019 at 10:41:37AM +0200, Thomas Gleixner wrote:
> There is only one caller of check_prev_add() which hands in a zeroed struct
> stack trace and a function pointer to save_stack(). Inside check_prev_add()
> the stack_trace struct is checked for being empty, which is always
> true. B
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Factor out combo PHY lane
power setup helper
URL : https://patchwork.freedesktop.org/series/59893/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5991 -> Patchwork_12863
=
== Series Details ==
Series: drm/i915: Seal races between async GPU cancellation, retirement and
signaling (rev2)
URL : https://patchwork.freedesktop.org/series/59584/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5990 -> Patchwork_12861
==
== Series Details ==
Series: drm/i915: Move GraphicsTechnology files under gt/
URL : https://patchwork.freedesktop.org/series/59900/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Move GraphicsTechnology files under gt/
+drivers/gpu/drm/i915/
== Series Details ==
Series: drm/i915: Move GraphicsTechnology files under gt/
URL : https://patchwork.freedesktop.org/series/59900/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f510efa18d5d drm/i915: Move GraphicsTechnology files under gt/
-:131: WARNING:FILE_PATH_CHANGES: ad
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Factor out combo PHY lane
power setup helper
URL : https://patchwork.freedesktop.org/series/59893/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Factor out combo PHY
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Factor out combo PHY lane
power setup helper
URL : https://patchwork.freedesktop.org/series/59893/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f4ea4c654a95 drm/i915/icl: Factor out combo PHY lane power set
Quoting Daniele Ceraolo Spurio (2019-04-24 18:53:08)
>
>
> On 4/24/19 8:47 AM, Chris Wilson wrote:
> > Given an implicit semaphore from one engine to the next, check that if
> > we skip the wait on that semaphore the following batch although
> > submitted early (as it depends along the single eng
On 4/24/19 8:47 AM, Chris Wilson wrote:
Given an implicit semaphore from one engine to the next, check that if
we skip the wait on that semaphore the following batch although
submitted early (as it depends along the single engine timeline) is not
executed ahead of its dependency.
Signed-off-by
On Wed, Apr 24, 2019 at 1:40 PM Srivatsa, Anusha
wrote:
>
> Hi,
>
> Requesting to have the below i915 changes merged-
>
>
>
> The following changes since commit 260cb35b11a968e7896f911565b75e411636ad69:
>
>
> Merge branch 'for-upstream' of git://git.chelsio.net/pub/git/linux-firmware
> (2019-04
Start partitioning off the code that talks to the hardware (GT) from the
uapi layers and move the device facing code under gt/
One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to
subdivide that header and body further (and split out the submission
code from the ringbuffer and log
== Series Details ==
Series: drm/vc4: Fix compilation error reported by kbuild test bot
URL : https://patchwork.freedesktop.org/series/59891/
State : failure
== Summary ==
Applying: drm/vc4: Fix compilation error reported by kbuild test bot
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: drm/i915/selftests: Verify whitelist of context registers (rev3)
URL : https://patchwork.freedesktop.org/series/59870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5989 -> Patchwork_12860
Summa
Hi,
Requesting to have the below i915 changes merged-
The following changes since commit 260cb35b11a968e7896f911565b75e411636ad69:
Merge branch 'for-upstream' of git://git.chelsio.net/pub/git/linux-firmware
(2019-04-09 06:41:10 -0400)
are available in the Git repository at:
git://anongit.f
Den 23.04.2019 13.04, skrev Martin Peres:
> On 20/04/2019 20:24, Noralf Trønnes wrote:
>>
>>
>> Den 20.04.2019 12.45, skrev Noralf Trønnes:
>>> This moves the modesetting code from drm_fb_helper to drm_client so it
>>> can be shared by all internal clients.
>>>
>>> Changes this time:
>>> - Use fu
Given an implicit semaphore from one engine to the next, check that if
we skip the wait on that semaphore the following batch although
submitted early (as it depends along the single engine timeline) is not
executed ahead of its dependency.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
Given an implicit semaphore from one engine to the next, check that if
we skip the wait on that semaphore the following batch although
submitted early (as it depends along the single engine timeline) is not
executed ahead of its dependency.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
Given an implicit semaphore from one engine to the next, check that if
we skip the wait on that semaphore the following batch although
submitted early (as it depends along the single engine timeline) is not
executed ahead of its dependency.
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
== Series Details ==
Series: drm/i915: Store the default sseu setup on the engine
URL : https://patchwork.freedesktop.org/series/59869/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5987 -> Patchwork_12859
Summary
---
This step of the BSpec combo PHY port enabling is missing, so add it
now.
Reported-by: Ville Syrjala
Cc: Jani Nikula
Cc: Madhav Chauhan
Cc: Ville Syrjala
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm
Factor out the combo PHY lane power configuration code to a separate
helper; it will be also needed by the next patch adding the same
configuration for DDI ports.
While at it also add support to handle lane reversal which wasn't
needed for DSI, but will be needed by DDI ports.
Also, remove the ma
Op 24-04-2019 om 17:06 schreef Maarten Lankhorst:
> Op 24-04-2019 om 15:12 schreef kbuild test robot:
>> tree: git://anongit.freedesktop.org/drm/drm-misc for-linux-next-fixes
>> head: d08106796a78a4273e39e1bbdf538dc4334b2635
>> commit: d08106796a78a4273e39e1bbdf538dc4334b2635 [1/1] drm/vc4: Fix
Op 24-04-2019 om 15:12 schreef kbuild test robot:
> tree: git://anongit.freedesktop.org/drm/drm-misc for-linux-next-fixes
> head: d08106796a78a4273e39e1bbdf538dc4334b2635
> commit: d08106796a78a4273e39e1bbdf538dc4334b2635 [1/1] drm/vc4: Fix memory
> leak during gpu reset.
> reproduce:
>
== Series Details ==
Series: drm/i915/fbdev: Actually configure untiled displays (rev2)
URL : https://patchwork.freedesktop.org/series/56728/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5985 -> Patchwork_12858
Summary
---
== Series Details ==
Series: drm/i915: Store the default sseu setup on the engine
URL : https://patchwork.freedesktop.org/series/59869/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Store the default sseu setup on the engine
-O:drivers/gpu/d
== Series Details ==
Series: drm/i915: Store the default sseu setup on the engine
URL : https://patchwork.freedesktop.org/series/59869/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d5a366875370 drm/i915: Store the default sseu setup on the engine
-:387: WARNING:FILE_PATH_CHANG
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: 575436c338f413c032e3accde7933e67f44261fb
commit: 3a6142185c17293159dec428c56f7f1f0ec53f61 [3/9] Merge remote-tracking
branch 'drm/drm-next' into drm-tip
reproduce:
# apt-get install sparse
git checkout 3a6142185c1729
Currently there is an underlying assumption that i915_request_unsubmit()
is synchronous wrt the GPU -- that is the request is no longer in flight
as we remove it. In the near future that may change, and this may upset
our signaling as we can process an interrupt for that request while it
is no long
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: 575436c338f413c032e3accde7933e67f44261fb
commit: 3a6142185c17293159dec428c56f7f1f0ec53f61 [3/9] Merge remote-tracking
branch 'drm/drm-next' into drm-tip
config: x86_64-rhel-7.6 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1)
== Series Details ==
Series: drm/i915/fbdev: Actually configure untiled displays (rev2)
URL : https://patchwork.freedesktop.org/series/56728/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
13043f445b75 drm/i915/fbdev: Actually configure untiled displays
-:40: CHECK:LINE_SPACING:
On 24/04/2019 12:03, Chris Wilson wrote:
Quoting Chris Wilson (2019-04-24 11:00:03)
Quoting Tvrtko Ursulin (2019-04-16 15:50:27)
On 16/04/2019 10:12, Chris Wilson wrote:
+ rq = ERR_PTR(-ENODEV);
+ with_intel_runtime_pm(engine->i915, wakeref)
+ rq = i915_request_alloc(engi
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that those registers we do add
are (a) then writa
Quoting Chris Wilson (2019-04-24 11:00:03)
> Quoting Tvrtko Ursulin (2019-04-16 15:50:27)
> >
> > On 16/04/2019 10:12, Chris Wilson wrote:
> > > + rq = ERR_PTR(-ENODEV);
> > > + with_intel_runtime_pm(engine->i915, wakeref)
> > > + rq = i915_request_alloc(engine, ctx);
> > > +
On 24/04/2019 11:54, Chris Wilson wrote:
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that those registers we do add
are (a) then writa
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that those registers we do add
are (a) then writa
Quoting Tvrtko Ursulin (2019-04-16 15:50:27)
>
> On 16/04/2019 10:12, Chris Wilson wrote:
> > The RING_NONPRIV allows us to add registers to a whitelist that allows
> > userspace to modify them. Ideally such registers should be safe and
> > saved within the context such that they do not impact sys
On 24/04/2019 10:51, Chris Wilson wrote:
As we push for better compartmentalisation, it is more convenient to
copy the default sseu configuration from the engine into the derived
logical context, than it is to dig it out from i915->runtime_info.
v2: Use intel_sseu_from_device_info() to describe
As we push for better compartmentalisation, it is more convenient to
copy the default sseu configuration from the engine into the derived
logical context, than it is to dig it out from i915->runtime_info.
v2: Use intel_sseu_from_device_info() to describe the converter
Signed-off-by: Chris Wilson
Quoting Tvrtko Ursulin (2019-04-17 10:40:26)
>
> On 17/04/2019 08:56, Chris Wilson wrote:
> > +/*
> > + * Powergating configuration for a particular (context,engine).
> > + */
> > +struct intel_sseu {
> > + u8 slice_mask;
> > + u8 subslice_mask;
> > + u8 min_eus_per_subslice;
> > +
Op 24-04-2019 om 02:50 schreef Dave Airlie:
> This patch broke userspace. I'm reverting it.
>
> I know userspace was broken, but since it's a userspace lots of people
> are using we shouldn't break it.
>
> We either need to add this as a config option that we can let people
> pick the breakage, or
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