== Series Details ==
Series: drm/i915/icl: Prevent possibe de-reference in
skl_check_pipe_max_pixel_clock.
URL : https://patchwork.freedesktop.org/series/59547/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5936_full -> Patchwork_12811_full
===
== Series Details ==
Series: drm/i915/icl: Prevent possibe de-reference in
skl_check_pipe_max_pixel_clock.
URL : https://patchwork.freedesktop.org/series/59547/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5936 -> Patchwork_12811
=
From: Clint Taylor
Add protections to prevent NULL de-reference for a couple variables used
in skl_check_pipe_max_pixel_clock to prevent GP exception from occurring
during some IGT tests.
References: https://bugs.freedesktop.org/show_bug.cgi?id=109084
Cc: Rodrigo Vivi
Cc: Martin Peres
Signed-
== Series Details ==
Series: drm/i915: Configurable GT idle frequency
URL : https://patchwork.freedesktop.org/series/59535/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5936_full -> Patchwork_12810_full
Summary
---
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev7)
URL : https://patchwork.freedesktop.org/series/58081/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5936_full -> Patchwork_12809_full
On Mon, Apr 15, 2019 at 04:05:26PM -0700, Bob Paauwe wrote:
There are real-time use cases where having deterministic CPU processes
can be more important than GPU power/performance. Parking the GPU at a
specific freqency by setting idle, min and max prohibits the normal
dynamic GPU frequency switc
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59534/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5936_full -> Patchwork_12808_full
==
== Series Details ==
Series: drm/i915: Configurable GT idle frequency
URL : https://patchwork.freedesktop.org/series/59535/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5936 -> Patchwork_12810
Summary
---
**SUCCESS*
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev7)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5936 -> Patchwork_12809
Summary
== Series Details ==
Series: drm/i915: Configurable GT idle frequency
URL : https://patchwork.freedesktop.org/series/59535/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Configurable GT idle frequency
+drivers/gpu/drm/i915/i915_sysfs.c:496:1
There are real-time use cases where having deterministic CPU processes
can be more important than GPU power/performance. Parking the GPU at a
specific freqency by setting idle, min and max prohibits the normal
dynamic GPU frequency switching which can introduce significant PCI-E
latency. This adds
Em seg, 2019-04-15 às 09:42 +0300, Tomi Sarvela escreveu:
> On 4/12/19 11:57 PM, Paulo Zanoni wrote:
> > Em qui, 2019-04-11 às 01:08 +, Patchwork escreveu:
> > > == Series Details ==
> > >
> > > Series: IRQ initialization debloat and conversion to uncore (rev2)
> > > URL : https://patchwork.
Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)
V2: Fix typo in headline(Chris)
Handle the non double buffered nature of the register(Ville)
V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks unrelated.
V4: Split the icl and skl wa's(Ville)
V5: Split
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59534/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5936 -> Patchwork_12808
On 4/9/19 2:41 PM, Chris Wilson wrote:
> Quoting Fernando Pacheco (2019-04-09 22:31:00)
>> GuC and HuC depend on struct_mutex for device
>> reinitialization. Moving away from this dependency
>> requires perma-pinning the firmware images in GGTT.
>> The upper portion of the GuC address space has
>>
On 4/15/19 3:10 PM, Daniele Ceraolo Spurio wrote:
On 4/15/19 2:44 PM, Michal Wajdeczko wrote:
On Mon, 15 Apr 2019 23:19:40 +0200, Daniele Ceraolo Spurio
wrote:
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Gen11 defines new register for checking HuC authentication status.
Look into the
>-Original Message-
>From: Wajdeczko, Michal
>Sent: Thursday, April 11, 2019 1:45 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Wajdeczko, Michal ; Ceraolo Spurio, Daniele
>; Joonas Lahtinen
>; Vivi, Rodrigo ;
>Srivatsa, Anusha
>Subject: [PATCH v2 20/22] drm/i915/guc: Define GuC firmware
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59534/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/bdw+: Move misc d
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/bdw+: Move misc display IRQ
handling to it own function
URL : https://patchwork.freedesktop.org/series/59534/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8041c9d42fca drm/i915/bdw+: Move misc display IRQ han
On 4/15/19 2:44 PM, Michal Wajdeczko wrote:
On Mon, 15 Apr 2019 23:19:40 +0200, Daniele Ceraolo Spurio
wrote:
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by:
A new macro that is going to be added in a further patch will need to
adjust the offset returned by _MMIO_TRANS2(), so here adding
_TRANS2() and moving most of the implementation of _MMIO_TRANS2() to
it and while at it taking the opportunity to rename pipe to trans.
Cc: Rodrigo Vivi
Signed-off-by
Just moving it to reduce the tabs and avoid break code lines.
No behavior changes intended here.
v2:
- Reading misc display IRQ outside of gen8_de_misc_irq_handler() as
other irq handlers (Dhinakaran)
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
d
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET + 0x800 and
using it makes more difficult for people with an PSR register address
from BSpec to search the register name in
i915 does not support enabling PSR on any transcoder other than eDP.
Clean up the misleading non-eDP code that currently exists to allow
for the rework of PSR register definitions in the next patch.
v2:
- Commit message updated (Rodrigo and Dhinakaran)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
R
Lets make PSR register macros explicit about what transcoder is used
to calculate the register offset.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++
drivers/gpu/drm/i915/i915_reg.h | 26 +++---
On Mon, 15 Apr 2019 23:19:40 +0200, Daniele Ceraolo Spurio
wrote:
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Ro
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: John Spotswood
Cc:
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
With newer GuC firmware it is always ok to ask GuC to update power
domain states. Make it an unconditional initialization step.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Reviewed-by: Daniele Ceraolo Spurio
D
Op 13-04-2019 om 13:13 schreef Simon Ser:
> From: Ville Syrjälä
>
> This adds basic immutable support for the zpos property. The zpos increases
> from bottom to top: primary, sprites, cursor.
>
> Signed-off-by: Ville Syrjälä
> [cont...@emersion.fr: adapted for latest drm-tip]
> Signed-off-by: Sim
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
There are few minor changes in the CSS header related to the version
numbering in new GuC firmwares. Update our definition and start using
common tools for extracting bitfields.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas
On Fri, 2019-04-12 at 17:24 -0700, Ceraolo Spurio, Daniele wrote:
>
> On 4/12/19 5:06 PM, Daniele Ceraolo Spurio wrote:
> >
> >
> >
> > On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> > >
> > > New GuC firmwares use updated sleep status definitions.
> > >
> > There is also no need to poll on re
== Series Details ==
Series: drm/i915: Nuke drm_crtc_state and use intel_atomic_state instead (rev3)
URL : https://patchwork.freedesktop.org/series/59363/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934_full -> Patchwork_12806_full
==
Pushed to dinq, thanks for the review!
Regards
Manasi
On Mon, Apr 15, 2019 at 11:22:10AM -0700, Manasi Navare wrote:
> This is one of the patches to start replacing drm pointers
> and use the intel_atomic_state and intel_crtc to derive
> the necessary intel state variables required for the intel
On Mon, Apr 15, 2019 at 4:14 PM Lankhorst, Maarten
wrote:
>
> mån 2019-04-15 klockan 19:26 +0530 skrev Sharma, Shashank:
> > > -Original Message-
> > > From: Lankhorst, Maarten
> > > Sent: Monday, April 15, 2019 4:28 PM
> > > To: Shankar, Uma ; intel-gfx@lists.freedeskt
> > > op.org; dri-
== Series Details ==
Series: series starting with [1/9] drm/i915: Verify workarounds immediately
after application
URL : https://patchwork.freedesktop.org/series/59523/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12807
=
On Mon, Apr 15, 2019 at 8:01 PM Greg Kroah-Hartman
wrote:
> On Mon, Apr 15, 2019 at 10:44:12PM +0530, Ramalingam C wrote:
> > On 2019-04-15 at 16:47:16 +0200, Greg Kroah-Hartman wrote:
> > > On Mon, Apr 15, 2019 at 06:11:13PM +0530, Ramalingam C wrote:
> > > > On 2019-04-05 at 14:32:00 +0200, Greg
== Series Details ==
Series: series starting with [1/2] include: linux: Regularise the use of
FIELD_SIZEOF macro
URL : https://patchwork.freedesktop.org/series/59514/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934_full -> Patchwork_12804_full
=
From: Jani Nikula
commit 21635d7311734d2d1b177f8a95e2f9386174b76d upstream.
Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast
and narrow") started to optize the eDP 1.4+ link config, both per spec
and as preparation for display stream compression support.
Sadly, we again fac
== Series Details ==
Series: series starting with [1/9] drm/i915: Verify workarounds immediately
after application
URL : https://patchwork.freedesktop.org/series/59523/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a34f6c36c289 drm/i915: Verify workarounds immediately after ap
== Series Details ==
Series: drm/i915: Nuke drm_crtc_state and use intel_atomic_state instead (rev3)
URL : https://patchwork.freedesktop.org/series/59363/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12806
Sometimes the HW doesn't even play fair, and completely forgets about
register writes. Skip verifying known troublemakers.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 40 ++
HDC_CHICKEN and CTX_PREEMPT were not writable through the whitelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_workarounds.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 9cd392
Read the engine workarounds back using the GPU after loading the initial
context state to verify that we are setting them correctly, and bail if
it fails.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 6 +
drivers/gpu/drm/i915/intel_workaro
According to our selftests, not all gen9 platforms share the common
registers. Inline gen9_whitelist_build() into each platform before we
start pruning.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_workarounds.c | 43 ++--
1 file changed, 33 insertions(+), 10 de
HDC_CHICKEN and CTX_PREEMPT were not writable through the whitelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_workarounds.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 0ad261
Immediately after writing the workaround, verify that it stuck in the
register.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 32 +---
1 file changed, 18 insertion
HDC_CHICKEN and CTX_PREEMPT were not writable through the whitelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_workarounds.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 836315
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that those registers we do add
are (a) then writa
HDC_CHICKEN and CTX_PREEMPT were not writable through the whitelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_workarounds.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 476e3a
== Series Details ==
Series: series starting with [1/4] drm/i915: Verify workarounds immediately
after application (rev2)
URL : https://patchwork.freedesktop.org/series/59513/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12805
==
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Definition of the parameters block passed to GuC is about to change.
Slightly refactor code now to make upcoming patch smaller.
I don't think this simplifies the upcoming patch (6/22) in any way,
since most changes in that one are concentrated in th
== Series Details ==
Series: drm/i915: Finish the ack+handler split for irq handler
URL : https://patchwork.freedesktop.org/series/59512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934_full -> Patchwork_12802_full
Summa
This is one of the patches to start replacing drm pointers
and use the intel_atomic_state and intel_crtc to derive
the necessary intel state variables required for the intel
modeset functions.
v3:
* Remove the unwanted newline (Ville)
v2:
* Flip the function arguments (Ville)
* Remove some remaini
On Mon, Apr 15, 2019 at 03:17:30PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 12, 2019 at 02:22:32PM -0700, Manasi Navare wrote:
> > This is one of the patches to start replacing drm pointers
> > and use the intel_atomic_state and intel_crtc to derive
> > the necessary intel state variables required
On Mon, Apr 15, 2019 at 10:44:12PM +0530, Ramalingam C wrote:
> On 2019-04-15 at 16:47:16 +0200, Greg Kroah-Hartman wrote:
> > On Mon, Apr 15, 2019 at 06:11:13PM +0530, Ramalingam C wrote:
> > > On 2019-04-05 at 14:32:00 +0200, Greg Kroah-Hartman wrote:
> > > > On Fri, Apr 05, 2019 at 04:06:22PM +0
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
Current GuC firmwares identify response message in a different way.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/intel_
On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
From: Oscar Mateo
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
Signed-off-by: Oscar Mateo
Signed-off-by: Micha
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that those registers we do add
are (a) then writa
== Series Details ==
Series: drm/i915: Enable eLLC caching of display buffers for SKL+
URL : https://patchwork.freedesktop.org/series/59502/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934_full -> Patchwork_12799_full
Su
== Series Details ==
Series: series starting with [1/2] include: linux: Regularise the use of
FIELD_SIZEOF macro
URL : https://patchwork.freedesktop.org/series/59514/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12804
===
On 2019-04-15 at 16:47:16 +0200, Greg Kroah-Hartman wrote:
> On Mon, Apr 15, 2019 at 06:11:13PM +0530, Ramalingam C wrote:
> > On 2019-04-05 at 14:32:00 +0200, Greg Kroah-Hartman wrote:
> > > On Fri, Apr 05, 2019 at 04:06:22PM +0530, Ramalingam C wrote:
> > > > On 2019-04-05 at 11:23:00 +0200, Greg
On Mon, Apr 15, 2019 at 05:52:51PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-15 16:49:04)
> > static irqreturn_t
> > -gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> > +gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl,
> > +
== Series Details ==
Series: series starting with [1/2] include: linux: Regularise the use of
FIELD_SIZEOF macro
URL : https://patchwork.freedesktop.org/series/59514/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0595fc32fba7 include: linux: Regularise the use of FIELD_SIZEOF
== Series Details ==
Series: series starting with [1/4] drm/i915: Verify workarounds immediately
after application
URL : https://patchwork.freedesktop.org/series/59513/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12803
=
On Mon, Apr 15, 2019 at 05:48:04PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-15 16:49:03)
> > @@ -2563,15 +2613,20 @@ static void ilk_display_irq_handler(struct
> > drm_i915_private *dev_priv,
> >
> > /* check event from PCH */
> > if (de_iir & DE_PCH_EVENT) {
>
Quoting Ville Syrjala (2019-04-15 16:49:04)
> static irqreturn_t
> -gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> +gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl,
> + const struct gen8_de_irq_regs *de,
> + const
Quoting Ville Syrjala (2019-04-15 16:49:03)
> @@ -2563,15 +2613,20 @@ static void ilk_display_irq_handler(struct
> drm_i915_private *dev_priv,
>
> /* check event from PCH */
> if (de_iir & DE_PCH_EVENT) {
> - u32 pch_iir = I915_READ(SDEIIR);
> + struct
Quoting Ville Syrjala (2019-04-15 16:49:02)
> static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> {
> + struct hpd_irq_regs hpd = {};
Is unnecessary, right?
hpd.hotplug_trigger is set here, and .dig_hotplug_reg immediately after
by irq_ack.
So other than those e
Quoting Ville Syrjala (2019-04-15 16:49:01)
> From: Ville Syrjälä
>
> Reduce the clutter a bit by introducing gen8_de_pipe_fault_mask().
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.free
On Mon, Apr 15, 2019 at 04:55:25PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-15 16:49:00)
> > From: Ville Syrjälä
> >
> > I never finished the irq ack+handler split for ilk+. Let's try to do
> > that now since people seem keen on cleaning up stuff in there. One
> > thing I didn'
== Series Details ==
Series: drm/i915: Finish the ack+handler split for irq handler
URL : https://patchwork.freedesktop.org/series/59512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12802
Summary
---
On Thu, Apr 11, 2019 at 05:36:30PM +0300, Gwan-gyeong Mun wrote:
> This patch series fix missed detection of changing of edid on between
> suspend and resume.
> First patch fixes drm_helper_hdp_irq_event() in order to fix a below use
> case.
>
> Following scenario requires detection of changing o
On Mon, Apr 15, 2019 at 05:03:09PM +0100, Chris Wilson wrote:
> Quoting Patchwork (2019-04-15 16:21:30)
> > == Series Details ==
> >
> > Series: drm/i915: Enable eLLC caching of display buffers for SKL+
> > URL : https://patchwork.freedesktop.org/series/59502/
> > State : success
> >
> > == Sum
Quoting Tvrtko Ursulin (2019-04-15 13:25:08)
>
> On 15/04/2019 12:45, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-04-15 12:43:07)
> >> From: Tvrtko Ursulin
> >>
> >> WaEnableStateCacheRedirectToCS context workaround configures the L3 cache
> >> to benefit 3d workloads but media has diffe
> > > On Wed 2019-04-10 13:17:17, Alastair D'Silva wrote:
> > > > From: Alastair D'Silva
> > > >
> > > > With modern high resolution screens, we can display more data,
> > > > which makes life a bit easier when debugging.
> > >
> > > I have quite some doubts about this feature.
> > >
> > > We are
In favour of FIELD_SIZEOF, lets deprecate other two similar macros
sizeof_field and SIZEOF_FIELD, and remove them completely.
Signed-off-by: Shyam Saini
---
arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 7 ---
include/linux/stddef.h | 8
tools/testing/
Currently, there are 3 different macros, namely sizeof_field, SIZEOF_FIELD
and FIELD_SIZEOF which are used to calculate the size of a member of
structure, so to bring uniformity in entire kernel source tree lets use
FIELD_SIZEOF and replace all occurrences of other two macros with this.
For this p
> -Original Message-
> From: Petr Mladek
> Sent: Monday, 15 April 2019 7:24 PM
> To: Alastair D'Silva
> Cc: 'Alastair D'Silva' ; 'Jani Nikula'
> ; 'Joonas Lahtinen'
> ; 'Rodrigo Vivi'
;
> 'David Airlie' ; 'Daniel Vetter' ;
'Karsten
> Keil' ; 'Jassi Brar' ; 'Tom
> Lendacky' ; 'David S. Mil
> -Original Message-
> From: Petr Mladek
> Sent: Saturday, 13 April 2019 12:12 AM
> To: Alastair D'Silva
> Cc: alast...@d-silva.org; Jani Nikula ;
Joonas
> Lahtinen ; Rodrigo Vivi
> ; David Airlie ; Daniel Vetter
> ; Karsten Keil ; Jassi Brar
> ; Tom Lendacky ;
> David S. Miller ; Jose Ab
> On Apr 14, 2019, at 3:14 AM, Shyam Saini
> wrote:
>
> Currently, there are 3 different macros, namely sizeof_field, SIZEOF_FIELD
> and FIELD_SIZEOF which are used to calculate the size of a member of
> structure, so to bring uniformity in entire kernel source tree lets use
> FIELD_SIZEOF and
> -Original Message-
> From: David Laight
> Sent: Monday, 15 April 2019 8:21 PM
> To: 'Alastair D'Silva' ; 'Petr Mladek'
>
> Cc: 'Alastair D'Silva' ; 'Jani Nikula'
> ; 'Joonas Lahtinen'
> ; 'Rodrigo Vivi' ;
> 'David Airlie' ; 'Daniel Vetter' ; 'Karsten
> Keil' ; 'Jassi Brar' ; 'Tom
> Lend
> -Original Message-
> From: Petr Mladek
> Sent: Saturday, 13 April 2019 12:04 AM
> To: Alastair D'Silva
> Cc: alast...@d-silva.org; Jani Nikula ;
Joonas
> Lahtinen ; Rodrigo Vivi
> ; David Airlie ; Daniel Vetter
> ; Karsten Keil ; Jassi Brar
> ; Tom Lendacky ;
> David S. Miller ; Jose Ab
On Sun, Apr 14, 2019 at 2:15 AM Shyam Saini
wrote:
>
> Currently, there are 3 different macros, namely sizeof_field, SIZEOF_FIELD
> and FIELD_SIZEOF which are used to calculate the size of a member of
> structure, so to bring uniformity in entire kernel source tree lets use
> FIELD_SIZEOF and repl
> -Original Message-
> From: Petr Mladek
> Sent: Friday, 12 April 2019 11:48 PM
> To: Alastair D'Silva
> Cc: alast...@d-silva.org; Jani Nikula ;
Joonas
> Lahtinen ; Rodrigo Vivi
> ; David Airlie ; Daniel Vetter
> ; Karsten Keil ; Jassi Brar
> ; Tom Lendacky ;
> David S. Miller ; Jose Abre
> From: Alastair D'Silva
> > Sent: 15 April 2019 11:29
> ...
> > I do, and I believe the choice of the output length should be in the
> > hands of the caller.
> >
> > On further thought, it would make more sense to remove the hardcoded
> > list of sizes and just enforce a power of 2. The function s
> -Original Message-
> From: David Laight
> Sent: Monday, 15 April 2019 9:04 PM
> To: 'Alastair D'Silva' ; 'Petr Mladek'
>
> Cc: 'Alastair D'Silva' ; 'Jani Nikula'
> ; 'Joonas Lahtinen'
> ; 'Rodrigo Vivi' ;
> 'David Airlie' ; 'Daniel Vetter' ; 'Karsten
> Keil' ; 'Jassi Brar' ; 'Tom
> Lend
Package: linux-image-4.19.0-0.bpo.4-amd64
Version: 4.19.28-2~bpo9+1
X-Debbugs-CC: ibm-a...@hmh.eng.br, ibm-acpi-de...@lists.sourceforge.net,
platform-driver-...@vger.kernel.org, intel-gfx@lists.freedesktop.org
Dear Maintainer,
I have a Lenovo ThinkPad T480s with Intel GFX and a Lenovo ThinkPad U
> > > On Wed 2019-04-10 13:17:18, Alastair D'Silva wrote:
> > > > From: Alastair D'Silva
> > > >
> > > > Some buffers may only be partially filled with useful data, while
> > > > the rest is padded (typically with 0x00 or 0xff).
> > > >
> > > > This patch introduces flags which allow lines of padd
Hi,
On Mon, Apr 15, 2019 at 11:13 AM Alexei Starovoitov
wrote:
>
> On Sun, Apr 14, 2019 at 2:15 AM Shyam Saini
> wrote:
> >
> > Currently, there are 3 different macros, namely sizeof_field, SIZEOF_FIELD
> > and FIELD_SIZEOF which are used to calculate the size of a member of
> > structure, so to
On Wed, Apr 10, 2019 at 09:49:33PM -0400, Rob Clark wrote:
> On Tue, Apr 9, 2019 at 8:27 AM Eric Engestrom
> wrote:
> >
> > On Tuesday, 2019-04-09 12:59:13 +0100, Eric Engestrom wrote:
> > > On Tuesday, 2019-04-09 11:35:14 +, Ayan Halder wrote:
> > > > Generated using make headers_install fro
Quoting Patchwork (2019-04-15 16:21:30)
> == Series Details ==
>
> Series: drm/i915: Enable eLLC caching of display buffers for SKL+
> URL : https://patchwork.freedesktop.org/series/59502/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12799
> ==
Sometimes the HW doesn't even play fair, and completely forgets about
register writes. Skip verifying known troublemakers.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 40 ++
Read the engine workarounds back using the GPU after loading the initial
context state to verify that we are setting them correctly, and bail if
it fails.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 6 +
drivers/gpu/drm/i915/intel_workaro
Immediately after writing the workaround, verify that it stuck in the
register.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108954
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 32 +---
1 file changed, 18 insertion
The RING_NONPRIV allows us to add registers to a whitelist that allows
userspace to modify them. Ideally such registers should be safe and
saved within the context such that they do not impact system behaviour
for other users. This selftest verifies that those registers we do add
are (a) then writa
Quoting Ville Syrjala (2019-04-15 16:49:00)
> From: Ville Syrjälä
>
> I never finished the irq ack+handler split for ilk+. Let's try to do
> that now since people seem keen on cleaning up stuff in there. One
> thing I didn't dare touch is gen11_gt_irq_handler() as that thing
> looks a bit nuts.
>
From: Ville Syrjälä
Collect the hpd related register values into a struct for
so that it's more convenient to pass them around.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 241 ++--
1 file changed, 137 insertions(+), 104 deletions(-)
diff --g
From: Ville Syrjälä
All the older platforms already follow the ack+handler apporoach
for interrupts. Convert ilk+ as well. As the number of registers
involved is rather large we'll introduce a few more structs to
carry the register values around.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/dr
From: Ville Syrjälä
The proper way to process interrupts is to first acknowledge them
all, and later process them. Start down that path for pch interrupts
by collecting the relevant register values into a struct so that
we can carry them from the ack part to the handler part.
Signed-off-by: Vill
From: Ville Syrjälä
I never finished the irq ack+handler split for ilk+. Let's try to do
that now since people seem keen on cleaning up stuff in there. One
thing I didn't dare touch is gen11_gt_irq_handler() as that thing
looks a bit nuts.
A bit of a downside:
Total: Before=39303, After=40393, c
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