== Series Details ==
Series: drm/i915: Pass intel_context to i915_request_create() (rev2)
URL : https://patchwork.freedesktop.org/series/58380/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5793_full -> Patchwork_12568_full
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Assign genlock CRTC pointer in
all slave CRTC states for tiled displays
URL : https://patchwork.freedesktop.org/series/58393/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5792_full -> Patchwork_12567_full
== Series Details ==
Series: GEN8+ GPU Watchdog Reset Support
URL : https://patchwork.freedesktop.org/series/58443/
State : failure
== Summary ==
Applying: drm/i915: Add engine reset count in get-reset-stats ioctl
Applying: drm/i915: Watchdog timeout: IRQ handler for gen8+
Applying: drm/i915:
On Fri, Mar 22, 2019 at 09:08:35PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-03-22 18:08:03)
> > From: Ville Syrjälä
> >
> > The AGPBUSY thing doesn't work on i945gm anymore. This means
> > the gmch is incapable of waking the CPU from C3 when an interrupt
> > is generated. The inte
From: Michel Thierry
Emit the required commands into the ring buffer for starting and
stopping the watchdog timer before/after batch buffer start during
batch buffer submission.
v2: Support watchdog threshold per context engine, merge lri commands,
and move watchdog commands emission to emit_bb_
From: Michel Thierry
Users/tests relying on the total reset count will start seeing a smaller
number since most of the hangs can be handled by engine reset.
Note that if reset engine x, context a running on engine y will be unaware
and unaffected.
To start the discussion, include just a total en
From: Michel Thierry
*** General ***
Watchdog timeout (or "media engine reset") is a feature that allows
userland applications to enable hang detection on individual batch buffers.
The detection mechanism itself is mostly bound to the hardware and the only
thing that the driver needs to do to su
From: Michel Thierry
Save the watchdog threshold (in us) as part of the engine state.
v2: Only do it for gen8+ (and prevent a missing-case warn).
v3: use ctx->__engine.
v4: Rebase.
v5: Rebase.
v6: Rebase, use intel_context_lookup()
Cc: Antonio Argenziano
Cc: Tvrtko Ursulin
Signed-off-by: Mich
This is a rebased on the original patch series from Michel Thierry:
https://patchwork.freedesktop.org/series/21868
Note that this series is only limited to the GPU Watchdog timeout for
execlists as it leaves out support for GuC based submissions for later.
PATCH v5 of this series was tested from
From: Michel Thierry
Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do the conversion to
'timestamps'.
The recommended default watchdog threshold for vide
== Series Details ==
Series: HDCP2.2 Phase II (rev4)
URL : https://patchwork.freedesktop.org/series/57232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5792_full -> Patchwork_12566_full
Summary
---
**SUCCESS**
No
On 3/21/19 5:00 AM, Michal Wajdeczko wrote:
GuC may send notification messages with payload larger than
single u32. Prepare driver to accept longer messages.
Reviewed-by: Daniele Ceraolo Spurio
To give a bit more context, for example the RESET_COMPLETE G2H will
provide the engine class in
== Series Details ==
Series: Do not re-read dpll registers (rev2)
URL : https://patchwork.freedesktop.org/series/58382/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5797 -> Patchwork_12581
Summary
---
**SUCCESS**
v2 of https://patchwork.freedesktop.org/series/58382/
Instead of re-reading the registers we just read on the hw state
readout, use the values saved on intel_shared_dpll. Besides not doing
the MMIO, this helps on sharing code since we don't have to
differentiate e.g. ICL and CNL because they have
By the time skl_ddi_clock_get() is called - and thus
skl_calc_wrpll_link() - we've just got the hw state from the pll
registers. We don't need to read them again: we can rather reuse what
was cached in the dpll_hw_state.
v2: rename state variable to pll_state, make argument const in
skl_calc_w
Now that pll_id is not used anymore for combophy, reduce its scope.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9e4d58759910.
Rename state to pll_state and use it as the argument to
bxt_calc_pll_link(), similar to how it's done in the skl variant.
The WARN_ON(!crtc_state->shared_dpll) is not very useful, so remove it
as well.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_ddi.c | 24 +---
By the time cnl_ddi_clock_get() is called we've just got the hw state
from the pll registers. We don't need to read them again: we can rather
reuse what was cached in the dpll_hw_state.
This also affects the code for ICL since it partially reuses the CNL
code. However the more intricate part on IC
By the time icl_ddi_clock_get() is called we've just got the hw state
from the pll registers. We don't need to read them again: we can rather
reuse what was cached in the dpll_hw_state.
While at it, s/refclk/ref_clock/ just to be consistent with the name
used in code nearby.
Signed-off-by: Lucas
== Series Details ==
Series: drm/i915: Add not fenceable reason to not enable FBC
URL : https://patchwork.freedesktop.org/series/58390/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5792_full -> Patchwork_12565_full
Summary
== Series Details ==
Series: drm/i915: Mark AML 0x87CA as ULX
URL : https://patchwork.freedesktop.org/series/58440/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5797 -> Patchwork_12580
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915: Mark AML 0x87CA as ULX
URL : https://patchwork.freedesktop.org/series/58440/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Mark AML 0x87CA as ULX
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3576:16: w
On Fri, 2019-03-22 at 22:49 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> If I'm reading the spec right AML 0x87CA is a Y SKU, so it
> should be marked as ULX in our old style terminology.
You are right, only the CPU is based on CFL.
Reviewed-by: José Roberto de Souza
>
> Cc: sta...@
Quoting Ville Syrjala (2019-03-22 18:08:04)
> From: Ville Syrjälä
>
> The vblank timestamp->counter guesstimator seems to be
> working sufficiently well, so there's no reason not to
> disable vblank interrupts ASAP even on gen2.
>
> Signed-off-by: Ville Syrjälä
Acked-by: Chris Wilson
-Chris
__
Quoting Ville Syrjala (2019-03-22 18:08:03)
> From: Ville Syrjälä
>
> The AGPBUSY thing doesn't work on i945gm anymore. This means
> the gmch is incapable of waking the CPU from C3 when an interrupt
> is generated. The interrupts just get postponed indefinitely until
> something wakes up the CPU.
From: Ville Syrjälä
If I'm reading the spec right AML 0x87CA is a Y SKU, so it
should be marked as ULX in our old style terminology.
Cc: sta...@vger.kernel.org
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Fixes: c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID")
Signed-
On Fri, Mar 22, 2019 at 12:50:07PM -0700, Lucas De Marchi wrote:
On Fri, Mar 22, 2019 at 03:09:59PM +0200, Ville Syrjälä wrote:
On Thu, Mar 21, 2019 at 03:02:57PM -0700, Lucas De Marchi wrote:
By the time icl_ddi_clock_get() is called we've just got the hw state
from the pll registers. We don't
On Thu, Mar 21, 2019 at 02:53:00PM -0700, Clinton Taylor wrote:
>
> On 3/20/19 6:54 AM, Imre Deak wrote:
> > From: Ville Syrjälä
> >
> > If we have only a single active pipe and the cdclk change only requires
> > the cd2x divider to be updated bxt+ can do the update with forcing a full
> > modes
On Fri, Mar 22, 2019 at 12:50:07PM -0700, Lucas De Marchi wrote:
> On Fri, Mar 22, 2019 at 03:09:59PM +0200, Ville Syrjälä wrote:
> >On Thu, Mar 21, 2019 at 03:02:57PM -0700, Lucas De Marchi wrote:
> >> By the time icl_ddi_clock_get() is called we've just got the hw state
> >> from the pll register
== Series Details ==
Series: series starting with [1/2] drm/i915: Disable C3 when enabling vblank
interrupts on i945gm
URL : https://patchwork.freedesktop.org/series/58427/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5796 -> Patchwork_12579
=
== Series Details ==
Series: series starting with [1/2] drm/i915: Disable C3 when enabling vblank
interrupts on i945gm
URL : https://patchwork.freedesktop.org/series/58427/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Disable C3 when enabl
On Fri, Mar 22, 2019 at 03:09:59PM +0200, Ville Syrjälä wrote:
On Thu, Mar 21, 2019 at 03:02:57PM -0700, Lucas De Marchi wrote:
By the time icl_ddi_clock_get() is called we've just got the hw state
from the pll registers. We don't need to read them again: we can rather
reuse what was cached in t
On Fri, Mar 22, 2019 at 09:28:01PM +0200, Jani Nikula wrote:
> On Fri, 22 Mar 2019, Ville Syrjälä wrote:
> > On Fri, Mar 22, 2019 at 11:44:21AM -0700, Manasi Navare wrote:
> >> On Fri, Mar 22, 2019 at 08:09:50PM +0200, Ville Syrjälä wrote:
> >> > In that case there is no point in doing a rmw.
> >>
== Series Details ==
Series: drm/i915: stop storing the media fuse
URL : https://patchwork.freedesktop.org/series/58387/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12564_full
Summary
---
**F
On Fri, 22 Mar 2019, Ville Syrjälä wrote:
> On Fri, Mar 22, 2019 at 11:44:21AM -0700, Manasi Navare wrote:
>> On Fri, Mar 22, 2019 at 08:09:50PM +0200, Ville Syrjälä wrote:
>> > In that case there is no point in doing a rmw.
>>
>> But isnt it always a good idea to do rmw? I mean what if the maste
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/ehl: Add EHL platform info and
PCI IDs
URL : https://patchwork.freedesktop.org/series/58425/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5796 -> Patchwork_12578
=
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/ehl: Add EHL platform info and
PCI IDs
URL : https://patchwork.freedesktop.org/series/58425/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/ehl: Add EHL platform info and PCI
Hi Chris,
sorry for the late reply, I got 5 version of this same patch and
I couldn't figure out what was what :)
Could you please add some versioning or note if version is
the same?
Some nits and questions
> +static bool has_context_engines(int i915)
> +{
> + struct drm_i915_gem_contex
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/ehl: Add EHL platform info and
PCI IDs
URL : https://patchwork.freedesktop.org/series/58425/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
53f2a89ae9a7 drm/i915/ehl: Add EHL platform info and PCI IDs
-:63: ERR
== Series Details ==
Series: drm/edid: Remove defunct EDID_QUIRK_FIRST_DETAILED_PREFERRED
URL : https://patchwork.freedesktop.org/series/58424/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5796 -> Patchwork_12577
Summary
-
On Fri, Mar 22, 2019 at 11:44:21AM -0700, Manasi Navare wrote:
> On Fri, Mar 22, 2019 at 08:09:50PM +0200, Ville Syrjälä wrote:
> > On Fri, Mar 22, 2019 at 10:58:01AM -0700, Manasi Navare wrote:
> > > On Fri, Mar 22, 2019 at 03:16:03PM +0200, Ville Syrjälä wrote:
> > > > On Fri, Mar 22, 2019 at 11:
On Fri, Mar 22, 2019 at 08:09:50PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 22, 2019 at 10:58:01AM -0700, Manasi Navare wrote:
> > On Fri, Mar 22, 2019 at 03:16:03PM +0200, Ville Syrjälä wrote:
> > > On Fri, Mar 22, 2019 at 11:34:25AM +0200, Jani Nikula wrote:
> > > > On Thu, 21 Mar 2019, Manasi N
== Series Details ==
Series: Do not re-read dpll registers
URL : https://patchwork.freedesktop.org/series/58382/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12562_full
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/guc: Replace preempt_client lookup with engine->preempt_context
URL : https://patchwork.freedesktop.org/series/58422/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5796 -> Patchwork_12576
===
== Series Details ==
Series: drm/i915: set vdbox/vebox enable masks on all gens
URL : https://patchwork.freedesktop.org/series/58381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12561_full
Summary
-
On Fri, 22 Mar 2019, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Looks like EDID_QUIRK_FIRST_DETAILED_PREFERRED never did anything.
> Its counterpart in f86EdidModes.c is properly hooked up but somehow
> that functionality was lost when it was copied into the kernel.
>
> The concensus seems to
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev3)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12560_full
== Series Details ==
Series: drm/i915/guc: GuC suspend path cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/58370/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12558_full
Summary
--
On Fri, Mar 22, 2019 at 10:58:01AM -0700, Manasi Navare wrote:
> On Fri, Mar 22, 2019 at 03:16:03PM +0200, Ville Syrjälä wrote:
> > On Fri, Mar 22, 2019 at 11:34:25AM +0200, Jani Nikula wrote:
> > > On Thu, 21 Mar 2019, Manasi Navare wrote:
> > > > In case of tiled displays where different tiles a
From: Ville Syrjälä
The vblank timestamp->counter guesstimator seems to be
working sufficiently well, so there's no reason not to
disable vblank interrupts ASAP even on gen2.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 8 +---
1 file changed, 1 insertion(+), 7 deleti
From: Ville Syrjälä
The AGPBUSY thing doesn't work on i945gm anymore. This means
the gmch is incapable of waking the CPU from C3 when an interrupt
is generated. The interrupts just get postponed indefinitely until
something wakes up the CPU. This is rather annoying for vblank
interrupts as we are
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Calculate maximum
ring size for preemption chain
URL : https://patchwork.freedesktop.org/series/58376/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12557_full
==
From: Bob Paauwe
Configure the correct set of outputs for EHL. EHL has three DDI's
plus DSI.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 7 ++-
1 fil
From: Bob Paauwe
EHL has a different number of subslices.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_device_info.c | 12 +---
1 file changed, 9 insertions(+
From: Lucas De Marchi
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
v2: Rebase on top of s/icl_pll_funcs/combo_pll_funcs
Signed-off-by: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
Signed-off-by:
From: Bob Paauwe
Add ElkhartLake as a unique platform as there are some differences
between it and Icelake.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/d
From: Anusha Srivatsa
EHL uses the same firmware as ICL.
Cc: Bob Paauwe
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: Bob Paauwe
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1 inserti
From: James Ausmus
Add known EHL PCI IDs.
v2 (Rodrigo): Removed x86 early quirk. To be sent in a separated
patch cc'ing the appropriated list and maintainers for
proper ack.
v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since GEN&_FEATURES.
- A
On Fri, Mar 22, 2019 at 03:16:03PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 22, 2019 at 11:34:25AM +0200, Jani Nikula wrote:
> > On Thu, 21 Mar 2019, Manasi Navare wrote:
> > > In case of tiled displays where different tiles are displayed across
> > > different ports, we need to synchronize the t
On Fri, Mar 22, 2019 at 11:34:25AM +0200, Jani Nikula wrote:
> On Thu, 21 Mar 2019, Manasi Navare wrote:
> > In case of tiled displays where different tiles are displayed across
> > different ports, we need to synchronize the transcoders involved.
> > This patch implements the transcoder port sync
From: Ville Syrjälä
Looks like EDID_QUIRK_FIRST_DETAILED_PREFERRED never did anything.
Its counterpart in f86EdidModes.c is properly hooked up but somehow
that functionality was lost when it was copied into the kernel.
The concensus seems to be that this quirk is a bit misguided
anyway so let's
Circumvent the dance we currently perform to find the preempt_client and
lookup its HW context for this engine, as we know we have already pinned
the preempt_context on the engine.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+),
On Fri, 2019-03-22 at 11:15 +0200, Jani Nikula wrote:
> On Thu, 21 Mar 2019, José Roberto de Souza wrote:
> > Right now it have a mix of PSR registers that are relative to PSR
> > mmio base and other register with a hardcoded address, lets keep it
> > consistented and have it all relative to mmio
== Series Details ==
Series: Revert "drm/i915: Introduce private PAT management"
URL : https://patchwork.freedesktop.org/series/58421/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5795 -> Patchwork_12575
Summary
---
On Wed, Mar 20, 2019 at 11:46:35PM +0200, Ville Syrjala wrote:
> + /*
> + * Try to muzzle SAGV to prevent it from
> + * messing up the memory controller readout.
> + */
> + intel_disable_sagv(dev_priv);
> +
> + /*
> + * Magic sleep to avoid observing very high DDR cl
== Series Details ==
Series: Revert "drm/i915: Introduce private PAT management"
URL : https://patchwork.freedesktop.org/series/58421/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: Revert "drm/i915: Introduce private PAT management"
-drivers/gpu/drm/i
Quoting Andi Shyti (2019-03-22 16:40:07)
> Hi Chris,
>
> sorry for the late reply, I got 5 version of this same patch and
> I couldn't figure out what was what :)
>
> Could you please add some versioning or note if version is
> the same?
>
> Some nits and questions
>
> > +static bool has_co
== Series Details ==
Series: Revert "drm/i915: Introduce private PAT management"
URL : https://patchwork.freedesktop.org/series/58421/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a3e8095440a5 Revert "drm/i915: Introduce private PAT management"
-:275: WARNING:LONG_LINE_COMMENT
On Thu, Mar 21, 2019 at 01:20:51PM -0700, Rodrigo Vivi wrote:
> On Thu, Mar 21, 2019 at 07:51:28PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > I added the loop but neglected to actually pass the level to the
> > function. So we were just looping 8 times calculating the exact
> > s
On Fri, Mar 22, 2019 at 10:32:40AM +0200, Jani Nikula wrote:
> On Thu, 21 Mar 2019, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Both LVDS and eDP have the same code to look up the preferred mode
> > from the connector probed_modes list. Move the code to a common
> > location.
> >
> > Sig
Quoting Michał Winiarski (2019-03-22 16:20:37)
> This reverts commit 4395890a48551982549d222d1923e2833dac47cf.
>
> It's been over a year since this was merged, and the actual users of
> intel_ppat_get / intel_ppat_put never materialized.
>
> Time to remove it!
>
> Fixes: 4395890a4855 ("drm/i915:
This reverts commit 4395890a48551982549d222d1923e2833dac47cf.
It's been over a year since this was merged, and the actual users of
intel_ppat_get / intel_ppat_put never materialized.
Time to remove it!
Fixes: 4395890a4855 ("drm/i915: Introduce private PAT management")
Signed-off-by: Michał Winia
== Series Details ==
Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on
multiple transcoders
URL : https://patchwork.freedesktop.org/series/58373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12556_full
=
On Fri, Mar 22, 2019 at 03:37:35PM +, Kulkarni, Vandita wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Friday, March 22, 2019 8:02 PM
> > To: Kulkarni, Vandita
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > Subject: Re: [Intel-gfx] [v2 2/2] drm/i915/
On Fri, Mar 22, 2019 at 03:42:43PM +, Brian Starkey wrote:
> On Fri, Mar 22, 2019 at 04:02:57PM +0200, Ville Syrjälä wrote:
> > On Fri, Mar 22, 2019 at 01:39:04PM +, Brian Starkey wrote:
> > > Hi,
> > >
> > > On Fri, Mar 22, 2019 at 01:06:01PM +, Shankar, Uma wrote:
> > > >
> > > >
>
On Fri, Mar 22, 2019 at 04:02:57PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 22, 2019 at 01:39:04PM +, Brian Starkey wrote:
> > Hi,
> >
> > On Fri, Mar 22, 2019 at 01:06:01PM +, Shankar, Uma wrote:
> > >
> > >
> > > >-Original Message-
> > > >From: Roper, Matthew D
> > > >Sent: F
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, March 22, 2019 8:02 PM
> To: Kulkarni, Vandita
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [Intel-gfx] [v2 2/2] drm/i915/icl: Fix port disable sequence for
> mipi-
> dsi
>
> On Fri, Mar 22, 2019 at 05:4
== Series Details ==
Series: series starting with [1/3] drm/i915: Handle YUV subpixel support better
URL : https://patchwork.freedesktop.org/series/58415/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5795 -> Patchwork_12574
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, March 22, 2019 8:03 PM
> To: Kulkarni, Vandita
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [Intel-gfx] [v2 1/2] drm/i915/icl: Ungate ddi clocks before IO
> enable
>
> On Fri, Mar 22, 2019 at 05:43:51PM
== Series Details ==
Series: drm/i915: Really calculate the cursor ddb based on the highest enabled
wm level
URL : https://patchwork.freedesktop.org/series/58372/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791_full -> Patchwork_12555_full
=
== Series Details ==
Series: series starting with [1/3] drm/i915: Handle YUV subpixel support better
URL : https://patchwork.freedesktop.org/series/58415/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Handle YUV subpixel support better
+driv
== Series Details ==
Series: series starting with [1/3] drm/i915: Handle YUV subpixel support better
URL : https://patchwork.freedesktop.org/series/58415/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
26e8aad601f1 drm/i915: Handle YUV subpixel support better
-:9: WARNING:COMMIT
Quoting Ville Syrjälä (2019-03-22 14:28:37)
> On Thu, Mar 21, 2019 at 04:19:08PM +, Chris Wilson wrote:
> > If we are already in the desired write domain of a set-domain ioctl,
> > then there is nothing for us to do and we can quickly return back to
> > userspace, avoiding any lock contention.
On Fri, Mar 22, 2019 at 05:43:51PM +0530, Vandita Kulkarni wrote:
> IO enable sequencing needs ddi clocks enabled.
> These clocks will be gated at a later point in
> the enable sequence.
>
> v2: Fix the commit header (uma)
>
> Signed-off-by: Vandita Kulkarni
> Reviewed-by: Uma Shankar
> ---
>
On Fri, Mar 22, 2019 at 05:43:52PM +0530, Vandita Kulkarni wrote:
> Re-enable clock gating of DDI clocks.
>
> v2: Fix the default ddi clk state for mipi-dsi (Imre)
>
> Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/icl_dsi.c
On Thu, Mar 21, 2019 at 04:19:08PM +, Chris Wilson wrote:
> If we are already in the desired write domain of a set-domain ioctl,
> then there is nothing for us to do and we can quickly return back to
> userspace, avoiding any lock contention. By recognising that the
> write_domain is always a s
On Fri, Mar 22, 2019 at 02:59:52PM +0100, Maarten Lankhorst wrote:
> Y41x formats is a 4:4:4 format, so it can be addressed with pixel level
> accuracy.
> Meanwhile it seems that while rotating YUYV 4:2:2 formats need a multiple of 2
> for width and height, otherwise corruption occurs.
>
> For YU
On Fri, Mar 22, 2019 at 02:59:54PM +0100, Maarten Lankhorst wrote:
> 90/270 rotation is not supported for Y21x and the 12/16 bits XVYU formats,
> reject support for them.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 5 +
> 1
On Fri, Mar 22, 2019 at 02:59:53PM +0100, Maarten Lankhorst wrote:
> This was missing in the original addition of those formats, but in
> PLANE_SIZE description it's mentioned that 8 cpp formats are not
> valid with Yf tiling. Reject this case properly.
>
> Also reject Y21x Yf tiling support this
On Fri, Mar 22, 2019 at 01:39:04PM +, Brian Starkey wrote:
> Hi,
>
> On Fri, Mar 22, 2019 at 01:06:01PM +, Shankar, Uma wrote:
> >
> >
> > >-Original Message-
> > >From: Roper, Matthew D
> > >Sent: Friday, March 22, 2019 2:50 AM
> > >To: Shankar, Uma
> > >Cc: intel-gfx@lists.fre
Y41x formats is a 4:4:4 format, so it can be addressed with pixel level
accuracy.
Meanwhile it seems that while rotating YUYV 4:2:2 formats need a multiple of 2
for width and height, otherwise corruption occurs.
For YUV 4:2:2, the spec says that w/h should always be even, but we get
away with odd
This was missing in the original addition of those formats, but in
PLANE_SIZE description it's mentioned that 8 cpp formats are not
valid with Yf tiling. Reject this case properly.
Also reject Y21x Yf tiling support this is also not supported.
Changes since v1:
- Reject Y21x as well.
Signed-off-
90/270 rotation is not supported for Y21x and the 12/16 bits XVYU formats,
reject support for them.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_sprite.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_
On Wed, Mar 20, 2019 at 05:03:16PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Syrjala, Ville
> >Sent: Tuesday, March 19, 2019 10:29 PM
> >To: Lankhorst, Maarten
> >Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
> >Sharma, Shashank ; Roper, Matthew D
> >
> >Subject
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Ungate ddi clocks before IO
enable
URL : https://patchwork.freedesktop.org/series/58408/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5794 -> Patchwork_12573
Hi,
On Fri, Mar 22, 2019 at 01:06:01PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Roper, Matthew D
> >Sent: Friday, March 22, 2019 2:50 AM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
> >; Syrjala, Ville ;
> >Sharma,
> >Shashank
> >
>-Original Message-
>From: Roper, Matthew D
>Sent: Friday, March 22, 2019 3:34 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
>; Syrjala, Ville ;
>Sharma,
>Shashank
>Subject: Re: [RFC v1 7/7] drm/i915: Add multi segment gamma for icl
>
>On Tue, Mar 19, 20
On Fri, Mar 22, 2019 at 11:34:25AM +0200, Jani Nikula wrote:
> On Thu, 21 Mar 2019, Manasi Navare wrote:
> > In case of tiled displays where different tiles are displayed across
> > different ports, we need to synchronize the transcoders involved.
> > This patch implements the transcoder port sync
On Thu, Mar 21, 2019 at 02:44:31PM -0700, Radhakrishna Sripada wrote:
> Fixes the clock-gating issue when pipe scaling is enabled.
> (Lineage #2006604312)
>
> V2: Fix typo in headline(Chris)
> Handle the non double buffered nature of the register(Ville)
> V3: Fix checkpatch warning. BAT failur
== Series Details ==
Series: drm/i915/bios: iterate over child devices to initialize ddi_port_info
URL : https://patchwork.freedesktop.org/series/58407/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5794 -> Patchwork_12572
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