On 03.12.2018 22:38, Ville Syrjälä wrote:
> On Thu, Nov 29, 2018 at 10:08:07AM +0100, Andrzej Hajda wrote:
>> On 21.11.2018 19:19, Laurent Pinchart wrote:
>>> Hi Ville,
>>>
>>> Thank you for the patch.
>>>
>>> On Tuesday, 20 November 2018 18:13:42 EET Ville Syrjala wrote:
From: Ville Syrjälä
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, December 3, 2018 7:39 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Chauhan, Madhav
> ; Kulkarni, Vandita
> ; Lisovskiy, Stanislav
> ; Deak, Imre
> Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi ena
On 03.12.2018 22:48, Ville Syrjälä wrote:
> On Thu, Nov 29, 2018 at 09:46:16AM +0100, Andrzej Hajda wrote:
>> Quite late, hopefully not too late.
>>
>>
>> On 21.11.2018 12:51, Ville Syrjälä wrote:
>>> On Wed, Nov 21, 2018 at 01:40:43PM +0200, Jani Nikula wrote:
> return;
> diff --
+intel-gfx.
> -Original Message-
> From: Zhang, Yanmin
> Sent: Tuesday, December 04, 2018 10:31 AM
> To: Vivi, Rodrigo ; Deak, Imre
> Cc: Syrjala, Ville ; dri-de...@lists.freedesktop.org
> Subject: RE: DP1.2 MST HUB
>
> +People in community.
>
> Rodrigo,
>
> Thanks for the kind info.
>
Hi,
Just one BDW regression fix for tiling mode format return
on vfio gfx dmabuf.
Thanks
--
The following changes since commit 7513edbc096a006f967eaf39088091442e623b83:
drm/i915/gvt: Avoid use-after-free iterating the gtt list (2018-11-21
17:31:56 +0800)
are available in the Git repository
== Series Details ==
Series: Change KVMGT into self loadable module (rev2)
URL : https://patchwork.freedesktop.org/series/53379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5250_full -> Patchwork_11005_full
Summary
--
== Series Details ==
Series: drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
URL : https://patchwork.freedesktop.org/series/53449/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5250 -> Patchwork_11006
Su
== Series Details ==
Series: drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
URL : https://patchwork.freedesktop.org/series/53449/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3e6218c6f05e drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
== Series Details ==
Series: Change KVMGT into self loadable module (rev2)
URL : https://patchwork.freedesktop.org/series/53379/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5250 -> Patchwork_11005
Summary
---
**WAR
DSC can be supported per DP connector. This patch adds a per connector
debugfs node to expose DSC support capability by the kernel.
The same node can be used from userspace to force DSC enable.
force_dsc_en written through this debugfs node is used to force
DSC even for lower resolutions.
v5:
* N
== Series Details ==
Series: series starting with [v4,1/9] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53448/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5250_full -> Patchwork_11004_full
==
On Mon, 2018-12-03 at 17:54 -0800, Souza, Jose wrote:
> On Mon, 2018-12-03 at 17:33 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 18:31 -0800, José Roberto de Souza wrote:
> > > Changing the i915_edp_psr_debug was enabling, disabling or
> > > switching
> > > PSR version by directly ca
This trys to make 'kvmgt' module as self loadable instead of loading
by i915/gvt device model. So hypervisor specific module could be
stand-alone, e.g only after loading hypervisor specific module, GVT
feature could be enabled via specific hypervisor interface, e.g VFIO/mdev.
So this trys to use h
== Series Details ==
Series: series starting with [v3,1/9] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53447/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5250_full -> Patchwork_11003_full
==
On Mon, 2018-12-03 at 17:33 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:31 -0800, José Roberto de Souza wrote:
> > Changing the i915_edp_psr_debug was enabling, disabling or
> > switching
> > PSR version by directly calling intel_psr_disable_locked() and
> > intel_psr_enable_locked
On Thu, 2018-11-29 at 18:31 -0800, José Roberto de Souza wrote:
> Changing the i915_edp_psr_debug was enabling, disabling or switching
> PSR version by directly calling intel_psr_disable_locked() and
> intel_psr_enable_locked(), what is not the default PSR path that is
> executed in a regular modes
On Mon, 2018-12-03 at 16:58 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:31 -0800, José Roberto de Souza wrote:
> > There is no issues changing the PSR variables even if PSR will be
> > not
> > enabled but it avoid having misleading values like have
> > psr2_enabled
> > set but enab
== Series Details ==
Series: series starting with [v4,1/9] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53448/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5250 -> Patchwork_11004
Su
On Thu, 2018-11-29 at 18:31 -0800, José Roberto de Souza wrote:
> There is no issues changing the PSR variables even if PSR will be not
> enabled but it avoid having misleading values like have psr2_enabled
> set but enabled unset.
>
> Cc: Maarten Lankhorst
> Cc: Dhinakaran Pandiyan
> Cc: Rodrig
== Series Details ==
Series: series starting with [v4,1/9] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53448/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Disable PSR in Apple panels
Okay!
Commit: d
Selective updates have a default granularity requirements as stated
by eDP spec(PSR2 SELECTIVE UPDATE X GRANULARITY CAPABILITY register
definition), so check if HW can match those requirements before
enabling PSR2.
v3:
- Changes in the comments and commit message(Dhinakaran)
- Printing the hdispla
As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {'
and this bit is only set for PSR1 move it to that block to make it
more easy to read.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/int
eDP spec states 2 different bits to enable sink to trigger a
interruption when there is a CRC mismatch.
DP_PSR_CRC_VERIFICATION is for PSR only and
DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by:
For ICL the bit 12 of CHICKEN_TRANS is reserved so we should not
touch it and as by default VSC_DATA_SEL_SOFTWARE_CONTROL is already
unset in gen10 + GLK we can just drop it and fix for both gens.
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
driver
Our frontbuffer tracking improved over the years + the WA #0884
helped us keep PSR2 enabled while triggering screen updates when
necessary so this FIXME is not valid anymore.
Acked-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i
Source is required to comply to sink SU granularity when
DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
so adding the registers offsets.
v2: Also adding DP_PSR2_SU_Y_GRANULARITY(Rodrigo)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Rober
i915 yet don't support PSR in Apple panels, so lets keep it disabled
while we work on that.
v2: Renamed DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED to
DP_DPCD_QUIRK_NO_PSR (Ville)
v3:
Adding documentation to DP_DPCD_QUIRK_NO_PSR(Dhinakaran and Jani)
Fixed typo in comment of the new quirk entry(Jani
According to eDP spec, sink can required specific selective update
granularity that source must comply.
Here caching the value if required and checking if source supports
it.
v3:
- Returning the default granularity in case DPCD read fails(Dhinakaran)
- Changed DPCD error message level(Dhinakaran)
For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
misleading value.
v2: Moving the set of DP_PSR_CRC_VERIFICATION to the else block
of 'if (dev_priv->psr.psr2_enabled)' to another patch. (Rodrigo)
Cc: Dhinakaran Pandiyan
== Series Details ==
Series: series starting with [v3,1/9] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53447/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5250 -> Patchwork_11003
Su
== Series Details ==
Series: series starting with [v3,1/9] drm/i915: Disable PSR in Apple panels
URL : https://patchwork.freedesktop.org/series/53447/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Disable PSR in Apple panels
Okay!
Commit: d
According to eDP spec, sink can required specific selective update
granularity that source must comply.
Here caching the value if required and checking if source supports
it.
v2:
- Returning the default granularity in case DPCD read fails(Dhinakaran)
- Changed DPCD error message level(Dhinakaran)
i915 yet don't support PSR in Apple panels, so lets keep it disabled
while we work on that.
v2: Renamed DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED to
DP_DPCD_QUIRK_NO_PSR (Ville)
v3:
Adding documentation to DP_DPCD_QUIRK_NO_PSR(Dhinakaran and Jani)
Fixed typo in comment of the new quirk entry(Jani
On Thu, 2018-11-29 at 15:37 -0800, Rodrigo Vivi wrote:
> On Thu, Nov 29, 2018 at 10:54:50PM +, Atwood, Matthew S wrote:
> > On Thu, 2018-11-29 at 14:00 -0800, Manasi Navare wrote:
> > > From: Matt Atwood
> > >
> > > According to DP spec (2.9.3.1 of DP 1.4) if
> > > EXTENDED_RECEIVER_CAPABILIT
For ICL the bit 12 of CHICKEN_TRANS is reserved so we should not
touch it and as by default VSC_DATA_SEL_SOFTWARE_CONTROL is already
unset in gen10 + GLK we can just drop it and fix for both gens.
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
driver
Source is required to comply to sink SU granularity when
DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
so adding the registers offsets.
v2: Also adding DP_PSR2_SU_Y_GRANULARITY(Rodrigo)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Rober
eDP spec states 2 different bits to enable sink to trigger a
interruption when there is a CRC mismatch.
DP_PSR_CRC_VERIFICATION is for PSR only and
DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only.
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by:
Our frontbuffer tracking improved over the years + the WA #0884
helped us keep PSR2 enabled while triggering screen updates when
necessary so this FIXME is not valid anymore.
Acked-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i
As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {'
and this bit is only set for PSR1 move it to that block to make it
more easy to read.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/int
For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
misleading value.
v2: Moving the set of DP_PSR_CRC_VERIFICATION to the else block
of 'if (dev_priv->psr.psr2_enabled)' to another patch. (Rodrigo)
Cc: Dhinakaran Pandiyan
Selective updates have a default granularity requirements as stated
by eDP spec(PSR2 SELECTIVE UPDATE X GRANULARITY CAPABILITY register
definition), so check if HW can match those requirements before
enabling PSR2.
v2:
- Changes in the comments and commit message(Dhinakaran)
- Printing the hdispla
On Mon, 2018-12-03 at 15:12 -0800, Pandiyan, Dhinakaran wrote:
> On Mon, 2018-12-03 at 14:45 -0800, Souza, Jose wrote:
> > On Mon, 2018-12-03 at 12:59 -0800, Dhinakaran Pandiyan wrote:
> > > On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > > > According to eDP spec, sink can requ
On Mon, 2018-12-03 at 14:45 -0800, Souza, Jose wrote:
> On Mon, 2018-12-03 at 12:59 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > > According to eDP spec, sink can required specific selective
> > > update
> > > granularity that source must
On Mon, Dec 03, 2018 at 03:03:52PM -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > - Reusing the EDP_PSR2_FRAME_BEFORE_SU_SHIFT in
> > EDP_PSR2_FRAME_BEFORE_SU
> > - Removing unused EDP_PSR2_FRAME_BEFORE_SU_MASK
> > - Adding EDP_PSR2_FRAME_BEF
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> - Reusing the EDP_PSR2_FRAME_BEFORE_SU_SHIFT in
> EDP_PSR2_FRAME_BEFORE_SU
> - Removing unused EDP_PSR2_FRAME_BEFORE_SU_MASK
> - Adding EDP_PSR2_FRAME_BEFORE_SU_MAX
> - Adding EDP_PSR2_IDLE_FRAME()
> - Adding EDP_PSR2_IDLE_FRAME_MAX
On Sat, 2018-12-01 at 18:32 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and
> use it
> URL : https://patchwork.freedesktop.org/series/53341/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5237_fu
On Mon, 2018-12-03 at 14:45 -0800, Dhinakaran Pandiyan wrote:
> On Mon, 2018-12-03 at 12:14 -0800, Souza, Jose wrote:
> > On Fri, 2018-11-30 at 15:35 -0800, Dhinakaran Pandiyan wrote:
> > > On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > > > i915 yet don't support PSR in Apple p
On Tue, Nov 20, 2018 at 08:24:39PM +, Chris Wilson wrote:
> Always show the FEC capability as it is initialised to 0 before error.
That is a good point, do you think we should do the same for DSC DPCD and print
that unconditionally?
Manasi
> Fixing,
>
> drivers/gpu/drm/i915/intel_dp.c:3846
On Mon, 2018-12-03 at 12:14 -0800, Souza, Jose wrote:
> On Fri, 2018-11-30 at 15:35 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > > i915 yet don't support PSR in Apple panels, so lets keep it
> > > disabled
> > > while we work on that.
> >
On Mon, 2018-12-03 at 12:59 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > According to eDP spec, sink can required specific selective update
> > granularity that source must comply.
> > Here caching the value if required and checking if sour
>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Tuesday, November 20, 2018 12:25 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Chris Wilson ; Jani Nikula
>; Ville Syrjala ;
>Navare, Manasi D ; Srivatsa, Anusha
>
>Subject: [PATCH 2/2] drm/i915/dp: Fix incons
On Thu, Nov 29, 2018 at 09:46:16AM +0100, Andrzej Hajda wrote:
> Quite late, hopefully not too late.
>
>
> On 21.11.2018 12:51, Ville Syrjälä wrote:
> > On Wed, Nov 21, 2018 at 01:40:43PM +0200, Jani Nikula wrote:
> >>
> >>> return;
> >>> diff --git a/drivers/gpu/drm/bridge/sil-sii8620.
On Thu, Nov 29, 2018 at 10:08:07AM +0100, Andrzej Hajda wrote:
> On 21.11.2018 19:19, Laurent Pinchart wrote:
> > Hi Ville,
> >
> > Thank you for the patch.
> >
> > On Tuesday, 20 November 2018 18:13:42 EET Ville Syrjala wrote:
> >> From: Ville Syrjälä
> >>
> >> Make life easier for drivers by sim
On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> According to eDP spec, sink can required specific selective update
> granularity that source must comply.
> Here caching the value if required and checking if source supports
> it.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
>
On Mon, Dec 03, 2018 at 04:29:17AM -0800, Peres, Martin wrote:
> On 30/11/2018 19:27, Vivi, Rodrigo wrote:
> > On Fri, Nov 30, 2018 at 03:04:40PM +0200, Martin Peres wrote:
> >>
> >>
> >> On 29/11/2018 19:36, Rodrigo Vivi wrote:
> >>> On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote:
On 2018-11-28 4:14 a.m., Joonas Lahtinen wrote:
> Quoting Ho, Kenny (2018-11-27 17:41:17)
>> On Tue, Nov 27, 2018 at 4:46 AM Joonas Lahtinen
>> wrote:
>>> I think a more abstract property "% of GPU (processing power)" might
>>> be a more universal approach. One can then implement that through
>>
On Fri, 2018-11-30 at 16:37 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > Selective updates have a default granularity requirements as stated
> > by eDP spec
> Needs reference to the location in the spec.
Done
>
> > , so check if HW can m
On Fri, 2018-11-30 at 15:35 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > i915 yet don't support PSR in Apple panels, so lets keep it
> > disabled
> > while we work on that.
> >
> > v2: Renamed DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED to
>
On Fri, 2018-11-30 at 15:54 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > As we have a else block for the 'if (dev_priv->psr.psr2_enabled) {'
> > and this bit is only set for PSR1 move it to that block to make it
> > more easy to read.
> >
On Fri, 2018-11-30 at 15:35 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > i915 yet don't support PSR in Apple panels, so lets keep it
> > disabled
> > while we work on that.
> >
> > v2: Renamed DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED to
>
Thanks fo rthe reviw, pushed to dinq!
Manasi
On Mon, Dec 03, 2018 at 02:05:42PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 30, 2018 at 05:04:12PM -0800, Manasi Navare wrote:
> > Fix the intel_link_compute_m_n in case of display stream
> > compression. This patch passes the compressed_bpp to
> > i
On Mon, Dec 03, 2018 at 11:34:16AM -0800, Clint Taylor wrote:
>
>
> On 12/03/2018 04:19 AM, Ville Syrjälä wrote:
> > On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
> >> From: Clint Taylor
> >>
> >> In August 2018 the BSPEC changed the ICL port programming sequence to
On 12/03/2018 04:19 AM, Ville Syrjälä wrote:
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville Syrjälä
On Mon, Dec 03, 2018 at 06:46:01AM +, Ho, Kenny wrote:
> Hey Matt,
>
> On Fri, Nov 30, 2018 at 5:22 PM Matt Roper wrote:
> > I think Joonas is describing something closer in
> > design to the cgroup-v2 "cpu" controller, which partitions the general
> > time/usage allocated to via cgroup; afai
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
(rev2)
URL : https://patchwork.freedesktop.org/series/53341/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add HAS_DISPLAY() and use it
-drive
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
(rev2)
URL : https://patchwork.freedesktop.org/series/53341/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2ea25bb8bc83 drm/i915: Add HAS_DISPLAY() and use it
b7a8a1adc388 drm/i91
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate (rev2)
URL : https://patchwork.freedesktop.org/series/53396/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Complete t
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate (rev2)
URL : https://patchwork.freedesktop.org/series/53396/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0c7799b14282 drm/i915: Complete the fences as t
Quoting Tvrtko Ursulin (2018-12-03 17:11:59)
>
> On 03/12/2018 11:36, Chris Wilson wrote:
> > We inspect the requests under the assumption that they will be marked as
> > completed when they are removed from the queue. Currently however, in the
> > process of wedging the requests will be removed f
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev8)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
-drivers/
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev8)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e2c45229710e drm/i915: Record GT workarounds in a list
68a4800dce59 drm/i915:
On 03/12/2018 11:36, Chris Wilson wrote:
We inspect the requests under the assumption that they will be marked as
completed when they are removed from the queue. Currently however, in the
process of wedging the requests will be removed from the queue before they
are completed, so rearrange the c
Quoting Mika Kuoppala (2018-12-03 15:28:22)
> Chris Wilson writes:
>
> > Currently we allocate a scratch page for each engine, but since we only
> > ever write into it for post-sync operations, it is not exposed to
> > userspace nor do we care for coherency. As we then do not care about its
> > c
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-12-03 13:40:26)
>> Chris Wilson writes:
>>
>> > Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
>> > actually broke the force-mmio mode for our execlists implementation. No
>> > one noticed, so ergo no one is actually using a
Quoting Mika Kuoppala (2018-12-03 13:40:26)
> Chris Wilson writes:
>
> > Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
> > actually broke the force-mmio mode for our execlists implementation. No
> > one noticed, so ergo no one is actually using an old vGPU host (where we
> >
Chris Wilson writes:
> Currently we allocate a scratch page for each engine, but since we only
> ever write into it for post-sync operations, it is not exposed to
> userspace nor do we care for coherency. As we then do not care about its
> contents, we can use one page for all, reducing our alloc
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate
URL : https://patchwork.freedesktop.org/series/53396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5239_full -> Patchwork_10996_full
===
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev7)
URL : https://patchwork.freedesktop.org/series/53313/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5243 -> Patchwork_10999
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev7)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
-drivers/
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev7)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0d8922bbcea9 drm/i915: Record GT workarounds in a list
5f4bdd949a82 drm/i915:
On Tue, Nov 27, 2018 at 07:32:59PM +0530, Ramalingam C wrote:
> At enable/disable of the HDCP encryption, for encryption status change
> we need minimum one frame duration. And we might program this bit any
> point(start/End) in the previous frame.
>
> With 20mSec, observed the timeout for change
On Tue, Nov 27, 2018 at 07:32:58PM +0530, Ramalingam C wrote:
> Adding a debug log when the DP_AUX_NATIVE_REPLY_ACK is missing
> for aksv write. This helps to locate the possible non responding
> DP HDCP sinks.
>
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 +-
>
On Tue, Nov 27, 2018 at 07:32:57PM +0530, Ramalingam C wrote:
> HDCP1.4 is enabled and validated only on GEN9+ platforms.
>
> Signed-off-by: Ramalingam C
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git
On Tue, Nov 27, 2018 at 07:32:56PM +0530, Ramalingam C wrote:
> HDCP1.4 key load process varies between Intel platform to platform.
>
> For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using
> the GT Driver Mailbox interface. Instead of listing all the platforms
> for this method, adop
On Thu, 29 Nov 2018, Jani Nikula wrote:
> On Tue, 27 Nov 2018, Imre Deak wrote:
>> The requirement for the DDI port clock gating for a port in DSI mode is
>> the opposite wrt. the case when the port is in DDI mode: the clock
>> should be gated when the port is active and ungated when the port is
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5239_full -> Patchwork_10995_full
Summary
---
**WARNI
On Mon, 03 Dec 2018, Ville Syrjälä wrote:
> On Thu, Nov 29, 2018 at 01:57:15PM +0200, Jani Nikula wrote:
>> Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions
>> a bit by moving the pll to port mapping and unmapping functions to the
>> ddi encoder hooks. This allows removal o
On Thu, 29 Nov 2018, Jani Nikula wrote:
> v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL
> mapping and gating patches [3] from me and [4] from Imre.
>
> It made sense to squash some patches in [1] and [2] together, I've tried
> to set authorship and co-developed-by tags fai
On 03/12/2018 11:36, Chris Wilson wrote:
Change the on-cpu check to on-runqueue to catch if the waiter has been
woken (and reset its current_state back to TASK_UNINTERRUPTIBLE to
perform the seqno check) but is sleeping due to being preempted off the
cpu.
Signed-off-by: Chris Wilson
Cc: Tvrtko
Chris Wilson writes:
> Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
> actually broke the force-mmio mode for our execlists implementation. No
> one noticed, so ergo no one is actually using an old vGPU host (where we
> required the older method) and so can simply remove the
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev4)
URL : https://patchwork.freedesktop.org/series/53313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5240 -> Patchwork_10998
From: Tvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit
59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds").
Issue with this is that some of the GT workarounds live in the MMIO space
which gets lost during engine resets. So far
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration o
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
The added data structure is a simple array of register, mask and value
items, which is a
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev4)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
-drivers/
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev4)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2c7ee2141088 drm/i915: Record GT workarounds in a list
-:135: WARNING:ALLOC_WI
Quoting Tvrtko Ursulin (2018-12-03 12:50:08)
> From: Tvrtko Ursulin
>
> To enable later verification of GT workaround state at various stages of
> driver lifetime, we record the list of applicable ones per platforms to a
> list, from which they are also applied.
>
> The added data structure is a
Quoting Tvrtko Ursulin (2018-12-03 12:50:14)
> From: Tvrtko Ursulin
>
> The new workaround list allocator grows the list in chunks so will end up
> with some unused space. Trim it when the initialization phase is done to
> free up a tiny bit of slab.
>
> v2:
> * Simplify with kmemdup. (Chris Wi
On 03.12.2018 12:52, Hans Verkuil wrote:
> On 12/03/2018 12:23 PM, Andrzej Hajda wrote:
>> On 30.11.2018 15:48, Hans Verkuil wrote:
>>> On 11/30/18 15:29, Ville Syrjälä wrote:
On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
> Hi Ville,
>
> As Christoph cannot respond
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