LGTM..
Reviewed-by: Mahesh Kumar
-Mahesh
On Tue, Oct 23, 2018 at 11:52 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> The 16Gb DIMM w/a is not applicable to BXT or GLK. Limit it to
> the appropriate platforms.
>
> This was especially harsh on GLK since we don't even try to read
> the DIMM
== Series Details ==
Series: series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
URL : https://patchwork.freedesktop.org/series/51415/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10555_full =
== Summary - WARNING ==
Minor unkn
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, October 23, 2018 5:39 PM
> To: Kulkarni, Vandita
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> Chauhan, Madhav
> Subject: Re: [PATCH 3/3] drm/i915/icl: Add get_config functionality for dsi
>
> On Tue, Oct 23, 2018 a
== Series Details ==
Series: drm/dp_mst: Improve VCPI helpers, use in nouveau
URL : https://patchwork.freedesktop.org/series/51412/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10554_full =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: Check MST topology change on resume
URL : https://patchwork.freedesktop.org/series/51418/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10556 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10556 abso
From: Lyude
As observed with the latest ThinkPad docks, we unfortunately can't rely
on docks keeping us updated with hotplug events that happened while we
were suspended. On top of that, even if the number of connectors remains
the same between suspend and resume it's still not safe to assume tha
From: Lyude
A follow-up to the previous commit, we skip checking the status of the
MST device and completely reprobe it if drm_dp_mst_topology_mgr_resume()
returns -EINVAL.
Cc: sta...@vger.kernel.org
Signed-off-by: Lyude
Signed-off-by: Juston Li
---
drivers/gpu/drm/i915/intel_dp.c | 7 ++-
Updated and resending these patches from Lyude:
https://lkml.org/lkml/2016/5/19/361
https://lkml.org/lkml/2016/5/19/360
As Lyude explains in patch 1/2, we can't rely on MST hubs to handle
hotplugs during suspend. This patchset will check if any EDID's changed
upon resume and reset the MST connecti
On Fri, 2018-10-19 at 23:46 +, Souza, Jose wrote:
> On Fri, 2018-10-19 at 13:42 -0700, Dhinakaran Pandiyan wrote:
> > On Wednesday, October 10, 2018 5:41:20 PM PDT José Roberto de Souza
> > wrote:
> > > It should always wait for idle state when disabling PSR because
"It" is ambiguous here.
H
== Series Details ==
Series: Add support for Gen 11 pipe color features
URL : https://patchwork.freedesktop.org/series/51408/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10553_full =
== Summary - SUCCESS ==
No regressions found.
== Known iss
== Series Details ==
Series: series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
URL : https://patchwork.freedesktop.org/series/51415/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10555 =
== Summary - SUCCESS ==
No regressions found
== Series Details ==
Series: drm/i915: Enable Plane Input CSC for YUV to RGB Conversion
URL : https://patchwork.freedesktop.org/series/51404/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10552_full =
== Summary - WARNING ==
Minor unknown changes c
On Mon, Oct 22, 2018 at 09:26:06PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 22, 2018 at 06:04:28PM +, Srivatsa, Anusha wrote:
> >
> >
> > >-Original Message-
> > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > >Sent: Friday, October 19, 2018 4:12 PM
> > >To: Navare, M
== Series Details ==
Series: series starting with [RFC,1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
URL : https://patchwork.freedesktop.org/series/51415/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Rename IS_GEN to IS_GEN_RANGE.
Okay!
Co
== Series Details ==
Series: drm/dp_mst: Improve VCPI helpers, use in nouveau
URL : https://patchwork.freedesktop.org/series/51412/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10554 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork
commit ac657f6461e5 ("drm/i915: Introduce IS_GEN macro") introduced
GEN_FOREVER that was never used.
My first attempt was to rename it to FOREVER since GEN is
already part of the macro. Then I used coccinelle to change all
-INTEL_GEN(e1) >= e2
+INTEL_GEN_RANGE(e1, e2, FOREVER)
-INTEL_GEN(e1) <= e2
Whenever possible we should stick with IS_GEN checks.
Bitmaks has been introduced on commit ae7617f0ef18 ("drm/i915:
Allow optimized platform checks") for efficiency.
Let's stick with it whenever possible.
This patch was generated with coccinelle:
spatch -sp_file is_gen.cocci *{c,h} --in-place
RANGE makes it longer, but clear.
Diff generated with:
sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
Cc: Tvrtko Ursulin
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915
It occurred to me that we never actually check this! So let's start
doing that.
Signed-off-by: Lyude Paul
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_dp_mst_topology.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/d
There has been a TODO waiting for quite a long time in
drm_dp_mst_topology.c:
/* We cannot rely on port->vcpi.num_slots to update
* topology_state->avail_slots as the port may not exist if the parent
* branch device was unplugged. This should be fixed by tracking
Currently; private objects are mostly used just for driver-specific
atomic state, but not entirely. MST also uses private objects for
holding it's atomic state, but in order to make our MST helpers safer
for atomic we need to be able to check that state after the driver has
performed it's own check
There's no reason to track the atomic state three times. Unfortunately,
this is currently what we're doing, and even worse is that there is only
one actually correct state pointer: the one in mst_state->base.state.
mgr->state never seems to be used, along with the one in
mst_state->state.
This con
Currently, nouveau uses the yolo method of setting up MST displays: it
uses the old VCPI helpers (drm_dp_find_vcpi_slots()) for computing the
display configuration. These helpers don't take care to make sure they
take a reference to the mstb port that they're checking, and
additionally don't actual
This patchset does some cleaning up of the atomic VCPI helpers for MST,
and converts nouveau over to using them. I would have included amdgpu in
this patch as well, but at the moment moving them over to the atomic
helpers is nontrivial.
Cc: Daniel Vetter
Lyude Paul (6):
drm/dp_mst: Deprecate d
Because we have drm_dp_atomic_find_vcpi_slots(), which actually takes
care to update the atomic state of the MST topology, prints valuable
debugging output, and actually takes references to the ports it's
checking! This explains some incorrect usage I've been seeing across the
tree...
Signed-off-b
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Fix the macros for
DFLEXDPMLE register bits
URL : https://patchwork.freedesktop.org/series/51402/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10551_full =
== Summary - WARNING
== Series Details ==
Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off
(rev4)
URL : https://patchwork.freedesktop.org/series/49447/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10550_full =
== Summary - SUCCESS ==
No reg
== Series Details ==
Series: drm/i915: Don't apply the 16Gb DIMM wm latency w/a to BXT/GLK (rev2)
URL : https://patchwork.freedesktop.org/series/50815/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10549_full =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: Add support for Gen 11 pipe color features
URL : https://patchwork.freedesktop.org/series/51408/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10553 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://p
== Series Details ==
Series: Add support for Gen 11 pipe color features
URL : https://patchwork.freedesktop.org/series/51408/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2b3c9d4383c7 drm/i915/icl: Add degamma and gamma lut size to gen11 caps
e24af21b0a53 drm/i915/icl: Add icl
On Tue, Oct 23, 2018 at 01:34:54PM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 23, 2018 at 01:01:11PM -0700, James Ausmus wrote:
> > On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote:
> > > On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> > > > From: Animesh Manna
> > > >
== Series Details ==
Series: drm/i915: Enable Plane Input CSC for YUV to RGB Conversion
URL : https://patchwork.freedesktop.org/series/51404/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10552 =
== Summary - SUCCESS ==
No regressions found.
External
On Tue, Oct 23, 2018 at 01:01:11PM -0700, James Ausmus wrote:
> On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote:
> > On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> > > From: Animesh Manna
> > >
> > > ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, an
Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 7 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/d
Add support for icl pipe degamma and gamma.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 3 ++
drivers/gpu/drm/i915/intel_color.c | 75 ++
2 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm
Add the degamma and gamma lut sizes to gen11 capability
structure.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e7459..3c18ea2 100644
This patch series adds support for Gen11 pipe degamma, CSC
and gamma hardware blocks.
CRC checks are not working for 10bit gamma but works for 8bit
pallete modes which seems to be due to some rounding errors in pipe.
ToDo: Support for Multi Segmented Gamma will be added later.
Uma Shankar (3):
== Series Details ==
Series: drm/i915: Enable Plane Input CSC for YUV to RGB Conversion
URL : https://patchwork.freedesktop.org/series/51404/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Enable Plane Input CSC for YUV to RGB Conversion
+dri
== Series Details ==
Series: drm/i915: Enable Plane Input CSC for YUV to RGB Conversion
URL : https://patchwork.freedesktop.org/series/51404/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5dc1b15925ab drm/i915: Enable Plane Input CSC for YUV to RGB Conversion
-:54: CHECK:MACRO_
On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> > From: Animesh Manna
> >
> > ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> > DC5/6 when appropriate.
> >
> > v2: (James Ausmus)
> > -
Plane input CSC needs to be enabled to convert frambuffers from
YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
the planes have hardcoded conversion and taken care by the legacy
code.
This patch defines the plane input csc registers and co-efficient
values for YUV to RGB conversion
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Fix the macros for
DFLEXDPMLE register bits
URL : https://patchwork.freedesktop.org/series/51402/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10551 =
== Summary - SUCCESS ==
No
== Series Details ==
Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off
(rev4)
URL : https://patchwork.freedesktop.org/series/49447/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10550 =
== Summary - SUCCESS ==
No regressions f
Quoting Ville Syrjala (2018-09-25 20:37:12)
> +static bool intel_plane_needs_remap(const struct intel_plane_state
> *plane_state)
> +{
> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + co
On Tue, Oct 23, 2018 at 07:49:42PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-10-23 17:02:01)
> > From: Ville Syrjälä
> >
> > Let's try to make sure the fb offset computations never hit
> > an integer overflow by making sure the entire fb stays
> > below 32bits. framebuffer_check()
On Tue, Oct 23, 2018 at 08:02:16PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-10-23 17:03:01)
> > From: Ville Syrjälä
> >
> > Extend the rotated vma mock selftest to cover remapped vmas as
> > well.
> >
> > TODO: reindent the loops I guess? Left like this for now to
> > ease review
This patch fixes the macros used for defining the DFLEXDPMLE
register bit fields. This accounts for changes in the spec.
Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
Cc: Animesh Manna
Cc: Paulo Zanoni
Cc: Jose Roberto de Souza
Signed-off-by: Manasi Navare
Review
On Tue, Oct 23, 2018 at 07:56:58PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-10-23 17:02:36)
> > From: Ville Syrjälä
> >
> > To overcome display engine stride limits we'll want to remap the
> > pages in the GTT. To that end we need a new gtt_view type which
> > is just like the "ro
In case of Legacy DP connector on TypeC port, the
flex IO DPMLE register is set to number of lanes configured
by the display driver which will be programmed into DDI_BUF_CTL
PORT_WIDTH_SELECTION.
This needs to be programmed before enabling the shared PLLs hence
add a pre_pll_enable hook for ICL and
On Tue, Oct 23, 2018 at 10:23:39AM +0300, Jani Nikula wrote:
> On Mon, 22 Oct 2018, Rodrigo Vivi wrote:
> > Let's add a platform has_sagv instead of having a full
> > function that handle platform by platform.
> >
> > The specially case for SKL for not controlled sagv
> > is already taken care ins
Quoting Ville Syrjala (2018-10-23 17:03:17)
> From: Ville Syrjälä
>
> Add a live selftest to excercise rotated/remapped vmas. We simply
> write through the rotated/remapped vma, and confirm that the data
> appears in the right page when read through the normal vma.
>
> Not sure what the fallout
== Series Details ==
Series: drm/i915: Don't apply the 16Gb DIMM wm latency w/a to BXT/GLK (rev2)
URL : https://patchwork.freedesktop.org/series/50815/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10549 =
== Summary - SUCCESS ==
No regressions found.
Quoting Ville Syrjala (2018-10-23 17:03:01)
> From: Ville Syrjälä
>
> Extend the rotated vma mock selftest to cover remapped vmas as
> well.
>
> TODO: reindent the loops I guess? Left like this for now to
> ease review
>
> v2: Include the vma type in the error message (Chris)
>
> Cc: Chris Wil
On Tue, Oct 23, 2018 at 09:21:02PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The 16Gb DIMM w/a is not applicable to BXT or GLK. Limit it to
> the appropriate platforms.
>
> This was especially harsh on GLK since we don't even try to read
> the DIMM information on that platforms, henc
Quoting Ville Syrjala (2018-10-23 17:02:36)
> From: Ville Syrjälä
>
> To overcome display engine stride limits we'll want to remap the
> pages in the GTT. To that end we need a new gtt_view type which
> is just like the "rotated" type except not rotated.
>
> v2: Use intel_remapped_plane_info bas
On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> From: Animesh Manna
>
> ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> DC5/6 when appropriate.
>
> v2: (James Ausmus)
> - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
>i915_drm_suspend_
Quoting Ville Syrjala (2018-09-25 20:37:08)
> From: Ville Syrjälä
>
> In the future framebuffer stride alignment requirements won't exactly
> match the units in which skl+ plane stride is specified. So extract
> the code for the skl+ stuff into a separate helper.
>
> Signed-off-by: Ville Syrjälä
Quoting Ville Syrjala (2018-10-23 17:02:01)
> From: Ville Syrjälä
>
> Let's try to make sure the fb offset computations never hit
> an integer overflow by making sure the entire fb stays
> below 32bits. framebuffer_check() in the core already does
> the same check, but as it doesn't know about ti
>-Original Message-
>From: Navare, Manasi D
>Sent: Tuesday, October 23, 2018 11:43 AM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH v5 17/28] drm/i915/dsc: Compute Rate Control
>parameters for DSC
>
>On Mon, O
== Series Details ==
Series: drm/i915: Don't apply the 16Gb DIMM wm latency w/a to BXT/GLK (rev2)
URL : https://patchwork.freedesktop.org/series/50815/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Don't apply the 16Gb DIMM wm latency w/a to
Rodrigo, this patch is tested by Jyoti. Can you review it?
Anusha
>-Original Message-
>From: Srivatsa, Anusha
>Sent: Tuesday, October 23, 2018 11:32 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Manna, Animesh ; Deak, Imre
>; Vivi, Rodrigo ; Ausmus, James
>; Srivatsa, Anusha
>Subject: [P
== Series Details ==
Series: drm/i915: Ensure proper HDA suspend/resume ordering with a device link
(rev2)
URL : https://patchwork.freedesktop.org/series/51189/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10548 =
== Summary - WARNING ==
Minor unknown
On Mon, Oct 22, 2018 at 04:34:59PM -0700, Srivatsa, Anusha wrote:
>
>
> From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Manasi
> Navare [manasi.d.nav...@intel.com]
> Sent: Friday, October 05, 2018 4:22 PM
> To: intel-gfx@lists.freede
From: Animesh Manna
ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.
v2: (James Ausmus)
- Also handle ICL as GEN9_LP in i915_drm_suspend_late and
i915_drm_suspend_early
- Add DC9 to gen9_dc_mask for ICL
- Re-order GEN checks for newest platfo
From: Ville Syrjälä
The 16Gb DIMM w/a is not applicable to BXT or GLK. Limit it to
the appropriate platforms.
This was especially harsh on GLK since we don't even try to read
the DIMM information on that platforms, hence valid_dimm was
always false and thus we always tried to apply the w/a.
Furt
== Series Details ==
Series: drm/i915: GTT remapping for display (rev5)
URL : https://patchwork.freedesktop.org/series/50165/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5022_full -> Patchwork_10547_full =
== Summary - SUCCESS ==
No regressions found.
== Known iss
== Series Details ==
Series: drm/i915: GTT remapping for display (rev5)
URL : https://patchwork.freedesktop.org/series/50165/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5022 -> Patchwork_10547 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://p
== Series Details ==
Series: drm/i915: GTT remapping for display (rev5)
URL : https://patchwork.freedesktop.org/series/50165/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Make sure fb gtt offsets stay within 32bits
+drivers/gpu/drm/i915/int
On Tue, Oct 23, 2018 at 04:39:13PM +0530, Vandita Kulkarni wrote:
> From: Madhav Chauhan
>
> This patch calculate various DPLL dividers and
> parameters for DSI encoder and adjust AFE clock
> for DSI. For DSI, 8x clock is AFE clock.
>
> v2: Extend haswell_crtc_compute_clock() for Gen11 DSI
>
>
== Series Details ==
Series: drm/i915: GTT remapping for display (rev5)
URL : https://patchwork.freedesktop.org/series/50165/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7ecc46df21aa drm/i915: Make sure fb gtt offsets stay within 32bits
-:44: CHECK:MACRO_ARG_REUSE: Macro argu
On 23/10/18 01:50, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2018-10-18 21:48:30)
On 18/10/18 12:55, Chris Wilson wrote:
Propagate the timeout on transferring the fw back to the caller where it
may act upon it, usually by restarting the xfer before failing.
v2: Simplify the wait
From: Ville Syrjälä
Add a live selftest to excercise rotated/remapped vmas. We simply
write through the rotated/remapped vma, and confirm that the data
appears in the right page when read through the normal vma.
Not sure what the fallout of making all rotated/remapped vmas
mappable/fenceable wou
From: Ville Syrjälä
Extend the rotated vma mock selftest to cover remapped vmas as
well.
TODO: reindent the loops I guess? Left like this for now to
ease review
v2: Include the vma type in the error message (Chris)
Cc: Chris Wilson
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/selft
From: Ville Syrjälä
To overcome display engine stride limits we'll want to remap the
pages in the GTT. To that end we need a new gtt_view type which
is just like the "rotated" type except not rotated.
v2: Use intel_remapped_plane_info base type
s/unused/unused_mbz/ (Chris)
Separate BUILD
From: Ville Syrjälä
Let's try to make sure the fb offset computations never hit
an integer overflow by making sure the entire fb stays
below 32bits. framebuffer_check() in the core already does
the same check, but as it doesn't know about tiling some things
can slip through. Repeat the check in t
== Series Details ==
Series: ICL DSI PLL enable
URL : https://patchwork.freedesktop.org/series/51373/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5020_full -> Patchwork_10543_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the c
== Series Details ==
Series: drm/i915: Ensure proper HDA suspend/resume ordering with a device link
(rev2)
URL : https://patchwork.freedesktop.org/series/51189/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5021 -> Patchwork_10546 =
== Summary - FAILURE ==
Serious unkno
Op 23-10-18 om 16:36 schreef Ville Syrjälä:
> On Tue, Oct 23, 2018 at 04:25:14PM +0200, Maarten Lankhorst wrote:
>> Op 22-10-18 om 17:48 schreef Ville Syrjälä:
>>> On Mon, Oct 22, 2018 at 03:51:52PM +0200, Maarten Lankhorst wrote:
To make NV12 working on icl, we need to update 2 planes simulta
In order to ensure that our system suspend and resume callbacks are
called in the correct order wrt. those of the HDA driver add a device
link to the HDA driver during audio component binding time. With i915 as
the supplier and HDA as the consumer the PM framework will guarantee
the HDA->i915 suspe
On Tue, Oct 23, 2018 at 04:25:14PM +0200, Maarten Lankhorst wrote:
> Op 22-10-18 om 17:48 schreef Ville Syrjälä:
> > On Mon, Oct 22, 2018 at 03:51:52PM +0200, Maarten Lankhorst wrote:
> >> To make NV12 working on icl, we need to update 2 planes simultaneously.
> >> I've chosen to do this in the CRT
Op 22-10-18 om 17:48 schreef Ville Syrjälä:
> On Mon, Oct 22, 2018 at 03:51:52PM +0200, Maarten Lankhorst wrote:
>> To make NV12 working on icl, we need to update 2 planes simultaneously.
>> I've chosen to do this in the CRTC step after plane validation is done,
>> so we know what planes are (in)vi
== Series Details ==
Series: series starting with [1/2] drm/i915: Relocate SKL+ NV12 src width w/a
URL : https://patchwork.freedesktop.org/series/51215/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5020 -> Patchwork_10545 =
== Summary - FAILURE ==
Serious unknown change
== Series Details ==
Series: Enabling the IGT for HDCP1.4 (rev6)
URL : https://patchwork.freedesktop.org/series/51113/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5020_full -> Patchwork_10542_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_
On Tue, Oct 23, 2018 at 04:11:28PM +0530, Ramalingam C wrote:
> When a HDCP authentication is in progress, if the display sink is
> hot unplugged, all DDC/AUX transaction related to the HDCP
> authentication will fail.
>
> This patch moves those kind of HDCP DDC/AUX failures into the debug
> logs
On Tue, Oct 23, 2018 at 02:52:29PM +0530, Ramalingam C wrote:
> Add a debugfs entry for providing the hdcp capabilities of the sink
> connected to the HDCP capable connectors.
>
> v2:
> Squashed the sink's hdcp capability into this patch. [Daniel]
>
> Signed-off-by: Ramalingam C
Yeah lgtm. Re
== Series Details ==
Series: drm/i915/icl: Define MOCS table for Icelake (rev4)
URL : https://patchwork.freedesktop.org/series/51258/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5020 -> Patchwork_10544 =
== Summary - FAILURE ==
Serious unknown changes coming with Patch
On Mon, Oct 22, 2018 at 04:15:48PM +0200, Noralf Trønnes wrote:
>
> Den 17.10.2018 17.46, skrev Daniel Vetter:
> > On Wed, Oct 17, 2018 at 03:04:53PM +0200, Noralf Trønnes wrote:
> > > This adds a library for shmem backed GEM objects.
> > >
> > > v5:
> > > - Drop drm_gem_shmem_prime_mmap() (Danie
Op 23-10-18 om 15:40 schreef Ville Syrjälä:
> On Tue, Oct 23, 2018 at 03:25:03PM +0200, Maarten Lankhorst wrote:
>> Op 18-10-18 om 21:59 schreef Ville Syrjala:
>>> From: Ville Syrjälä
>>>
>>> The SKL+ NV12 src width alignment w/a is still living in an odd place.
>>> Everything else was already rel
On Mon, Oct 22, 2018 at 02:57:28PM +0200, Christian König wrote:
> Am 17.10.18 um 15:04 schrieb Noralf Trønnes:
> > This adds an optional function table on GEM objects.
> > The main benefit is for drivers that support more than one type of
> > memory (shmem,vram,cma) for their buffers depending on
On Tue, Oct 23, 2018 at 03:25:03PM +0200, Maarten Lankhorst wrote:
> Op 18-10-18 om 21:59 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > The SKL+ NV12 src width alignment w/a is still living in an odd place.
> > Everything else was already relocated closer to the main plane check
> > funct
Op 18-10-18 om 21:59 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> The SKL+ NV12 src width alignment w/a is still living in an odd place.
> Everything else was already relocated closer to the main plane check
> function. Move this workaround as well.
>
> As a bonus we avoid the funky rotated vs
The table has been unified across OSes to minimize virtualization overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Meaning
On 2018-10-22 19:40, Daniele Ceraolo Spurio wrote:
On 22/10/18 10:13, Tomasz Lis wrote:
The table has been unified across OSes to minimize virtualization
overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can b
Quoting Patchwork (2018-10-23 13:26:51)
> == Series Details ==
>
> Series: drm: fix deadlock of syncobj v6
> URL : https://patchwork.freedesktop.org/series/51369/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_5020_full -> Patchwork_10540_full =
>
> == Summary - FA
== Series Details ==
Series: drm: fix deadlock of syncobj v6
URL : https://patchwork.freedesktop.org/series/51369/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5020_full -> Patchwork_10540_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_1054
== Series Details ==
Series: ICL DSI PLL enable
URL : https://patchwork.freedesktop.org/series/51373/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5020 -> Patchwork_10543 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freedesktop.org
On Tue, 23 Oct 2018, Vandita Kulkarni wrote:
> This has been tested with other power-on related patches
> present at https://github.com/madhavchauhan/Intel-DSI-Driver
Please rebase on top of icl-dsi-2018-10-23 branch of
https://cgit.freedesktop.org/~jani/drm/
BR,
Jani.
--
Jani Nikula, Intel Op
Am 23.10.18 um 11:37 schrieb Chunming Zhou:
> v2:
> add a mutex between sync_cb execution and free.
> v3:
> clearly separating the roles for pt_lock and cb_mutex (Chris)
> v4:
> the cb_mutex should be taken outside of the pt_lock around
> this if() block. (Chris)
> v5:
> fix a corner case
> v6:
> t
On Tue, Oct 23, 2018 at 04:39:14PM +0530, Vandita Kulkarni wrote:
> From: Madhav Chauhan
>
> This patch implements the functionality for getting PIPE
> configuration to which DSI encoder is connected. Used during
> the atomic modeset.
>
> v2: use intel_dsi_bitrate instead of intel_dsi->pclk
>
>
On Mon, Oct 22, 2018 at 03:29:22PM -0700, Paulo Zanoni wrote:
> Em Qui, 2018-10-18 às 16:41 +0300, Ville Syrjälä escreveu:
> > On Tue, Oct 16, 2018 at 03:01:29PM -0700, Paulo Zanoni wrote:
> > > The goal of struct skl_wm_params is to cache every watermark
> > > parameter so the other functions can
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