== Series Details ==
Series: drm/i915/aml: Add new Amber Lake PCI ID
URL : https://patchwork.freedesktop.org/series/50037/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4865_full -> Patchwork_10257_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwor
On Fri, Sep 21, 2018 at 07:39:40PM +0200, Maarten Lankhorst wrote:
> To make NV12 working on icl, we need to update 2 planes simultaneously.
> I've chosen to do this in the CRTC step after plane validation is done,
> so we know what planes are (in)visible. The linked Y plane will get
> updated in i
On Fri, Sep 21, 2018 at 07:39:39PM +0200, Maarten Lankhorst wrote:
> Gen11 supports 7 planes + 1 cursor on each pipe. Bump
> I915_MAX_PLANES to 8, and set num_sprites correctly.
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
I notcie the comment above this if statement is a bit s
== Series Details ==
Series: series starting with [1/2] drm/i915: Match code to comment and enforce
ppgtt for execlists
URL : https://patchwork.freedesktop.org/series/50040/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
== Series Details ==
Series: series starting with [1/2] drm/i915: Match code to comment and enforce
ppgtt for execlists
URL : https://patchwork.freedesktop.org/series/50038/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4865 -> Patchwork_10258 =
== Summary - FAILURE ==
== Series Details ==
Series: drm/i915: Match code to comment and enforce ppgtt for execlists (rev2)
URL : https://patchwork.freedesktop.org/series/50034/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4863_full -> Patchwork_10256_full =
== Summary - WARNING ==
Minor unkno
== Series Details ==
Series: series starting with [1/2] drm/i915: Match code to comment and enforce
ppgtt for execlists
URL : https://patchwork.freedesktop.org/series/50038/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Match code to comment and enforce ppgtt for
== Series Details ==
Series: drm/i915/aml: Add new Amber Lake PCI ID
URL : https://patchwork.freedesktop.org/series/50037/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4865 -> Patchwork_10257 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patc
== Series Details ==
Series: drm/i915: introduce i915_gem_context_vm helper
URL : https://patchwork.freedesktop.org/series/50032/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4862_full -> Patchwork_10255_full =
== Summary - WARNING ==
Minor unknown changes coming with P
On Fri, Sep 21, 2018 at 10:46:43AM -0700, Souza, Jose wrote:
> On Fri, 2018-09-21 at 09:17 -0700, Lee, Shawn C wrote:
> > According to patch "drm/i915/aml: Introducing Amber Lake platform"
> > (e364672477a1). Amber Lake uses the same gen graphics as Kaby Lake.
> > And it is the member of KBL ULX se
== Series Details ==
Series: drm/i915: Match code to comment and enforce ppgtt for execlists (rev2)
URL : https://patchwork.freedesktop.org/series/50034/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4863 -> Patchwork_10256 =
== Summary - SUCCESS ==
No regressions found.
Now that we are confident in providing full-ppgtt where supported,
remove the ability to override the context isolation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c | 11
drivers/gpu/drm/i915/i915_drv.h | 13 ++--
Our execlist dispatch code requires a ppGTT so make sure we enforce that
option in intel_sanitize_enable_ppgtt(). The comment already tries to
explain that execlists requires ppgtt, but was written when gen8 may
have also taken the legacy path; so rewrite the code to match the
comment by using HAS_
== Series Details ==
Series: drm/i915/gen11: Enable planar format support on gen11.
URL : https://patchwork.freedesktop.org/series/50031/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4862_full -> Patchwork_10254_full =
== Summary - WARNING ==
Minor unknown changes comin
Our execlist dispatch code requires a ppGTT so make sure we enforce that
option in intel_sanitize_enable_ppgtt(). The comment already tries to
explain that execlists requires ppgtt, but was written when gen8 may
have also taken the legacy path; so rewrite the code to match the
comment by using HAS_
Now that we are confident in providing full-ppgtt where supported,
remove the ability to override the context isolation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c | 11 ---
drivers/gpu/drm/i915/i915_drv.h | 13 +
On Fri, 2018-09-21 at 11:27 +0200, Daniel Vetter wrote:
> On Tue, Sep 18, 2018 at 07:06:19PM -0400, Lyude Paul wrote:
> > Currently we set intel_connector->mst_port to NULL to signify that the
> > MST port has been removed from the system so that we can prevent further
> > action on the port such a
This new AML PCI ID uses the same gen graphics as Coffe Lake not a
Kaby Lake one like the other AMLs.
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 4
2 files changed, 5 insertions(+)
diff --git a/drivers
Our execlist dispatch code requires a ppGTT so make sure we enforce that
option in intel_sanitize_enable_ppgtt(). The comment already tries to
explain that execlists requires ppgtt, but was written when gen8 may
have also taken the legacy path; so rewrite the code to match the
comment by using HAS_
Our execlist dispatch code requires a ppGTT so make sure we enforce that
option in intel_sanitize_enable_ppgtt(). The comment already tries to
explain that execlists requires ppgtt, but was written when gen8 may
have also taken the legacy path; so rewrite the code to match the
comment by using HAS_
== Series Details ==
Series: drm/i915: introduce i915_gem_context_vm helper
URL : https://patchwork.freedesktop.org/series/50032/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4862 -> Patchwork_10255 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https
On Fri, Sep 21, 2018 at 09:35:52PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 21, 2018 at 07:39:40PM +0200, Maarten Lankhorst wrote:
> > To make NV12 working on icl, we need to update 2 planes simultaneously.
> > I've chosen to do this in the CRTC step after plane validation is done,
> > so we know
Quoting Matthew Auld (2018-09-21 19:45:18)
> Throughout the kernel it's a pretty common pattern to do:
>
> vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ctx->i915->ggtt.vm;
The plan has always been to work towards making ctx->ppgtt dtrt.
-Chris
___
Intel-gfx
On Wed, Sep 19, 2018 at 02:01:26PM +0530, Mahesh Kumar wrote:
> This cleanup patch makes changes to use for_each_pipe loop
> during bit-mask assignment of allowed crtc with encoder.
>
> changes:
> - use BIT(i) macro instead of (1 << i) (Chris)
> changes from V2:
> - use int for consistency (Jani
On Wed, 2018-09-19 at 21:05 +0300, Ville Syrjälä wrote:
> On Wed, Sep 19, 2018 at 05:49:33PM +, Pandiyan, Dhinakaran wrote:
> > On Wed, 2018-09-19 at 20:30 +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 18, 2018 at 12:20:09AM -0700, Dhinakaran Pandiyan
> > > wrote:
> > > > This way all short pul
On Fri, Sep 21, 2018 at 07:39:44PM +0200, Maarten Lankhorst wrote:
> The UV plane is the master plane that does all color correction etc.
> It needs to be programmed with the dimensions for color plane 1 (UV).
>
> The Y plane just feeds the Y pixels to it. Program the scaler from the
> master only
On Fri, Sep 21, 2018 at 07:39:43PM +0200, Maarten Lankhorst wrote:
> We configure the chroma upsampler with the same chroma siting as
> used by the scaler for consistency, the chroma upsampler is used
> instead of the scaler for YUV 4:2:0 on ICL's HDR planes.
>
> Signed-off-by: Maarten Lankhorst
On Fri, Sep 21, 2018 at 07:39:42PM +0200, Maarten Lankhorst wrote:
> The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
> upsampler to upscale YUV420 to YUV444 and the scaler should only be
> used for upscaling. Because of this we shouldn't program the scalers
> in planar mode if
Throughout the kernel it's a pretty common pattern to do:
vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ctx->i915->ggtt.vm;
in order to determine the correct vm, so why not roll into a helper.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matthew Auld
Cc: Tvrtko Ursulin
Cc: Chris Wilson
---
driver
== Series Details ==
Series: drm/i915/gen11: Enable planar format support on gen11.
URL : https://patchwork.freedesktop.org/series/50031/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4862 -> Patchwork_10254 =
== Summary - SUCCESS ==
No regressions found.
External URL
On Fri, Sep 21, 2018 at 07:39:40PM +0200, Maarten Lankhorst wrote:
> To make NV12 working on icl, we need to update 2 planes simultaneously.
> I've chosen to do this in the CRTC step after plane validation is done,
> so we know what planes are (in)visible. The linked Y plane will get
> updated in i
== Series Details ==
Series: drm/i915/gen11: Enable planar format support on gen11.
URL : https://patchwork.freedesktop.org/series/50031/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0f2019e00594 drm/i915/gen11: Enable 6 sprites on gen11
06f6be3d4c6f drm/i915/gen11: Link nv12
On Fri, 2018-09-21 at 09:17 -0700, Lee, Shawn C wrote:
> According to patch "drm/i915/aml: Introducing Amber Lake platform"
> (e364672477a1). Amber Lake uses the same gen graphics as Kaby Lake.
> And it is the member of KBL ULX series.
>
> So far, IS_KBL_ULX macro did not include AML platform. It
== Series Details ==
Series: drm/i915: Add AML id into KBL_ULX support list
URL : https://patchwork.freedesktop.org/series/50023/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4860_full -> Patchwork_10253_full =
== Summary - SUCCESS ==
No regressions found.
== Known
The UV plane is the master plane that does all color correction etc.
It needs to be programmed with the dimensions for color plane 1 (UV).
The Y plane just feeds the Y pixels to it. Program the scaler from the
master only, and set PLANE_CTL_YUV420_Y_PLANE on the slave plane.
Changes since v1:
- M
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index cea91235d498..1a069b90bbc2 100644
--- a/drivers/gpu/drm
With all the preparation patches upstreamed, time to enable NV12. :)
Maarten Lankhorst (7):
drm/i915/gen11: Enable 6 sprites on gen11
drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v3.
drm/i915/gen11: Handle watermarks correctly for separate Y/UV planes.
drm/i915/gen11: Pro
The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma
upsampler to upscale YUV420 to YUV444 and the scaler should only be
used for upscaling. Because of this we shouldn't program the scalers
in planar mode if NV12 and the chroma upsampler are used. Instead
program the scalers like on
Skylake style watermarks program the UV parameters into wm->uv_wm,
and have a separate DDB allocation for UV blocks into the same plane.
Gen11 watermarks have a separate plane for Y and UV, with separate
mechanisms. The simplest way to make it work is to keep the current
way of programming waterma
We configure the chroma upsampler with the same chroma siting as
used by the scaler for consistency, the chroma upsampler is used
instead of the scaler for YUV 4:2:0 on ICL's HDR planes.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
drivers
Gen11 supports 7 planes + 1 cursor on each pipe. Bump
I915_MAX_PLANES to 8, and set num_sprites correctly.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_device_info.c | 5 -
drivers/gpu/drm/i915/intel_display.h | 3 +++
2 files changed, 7 insertions(+), 1 deletion(-)
d
To make NV12 working on icl, we need to update 2 planes simultaneously.
I've chosen to do this in the CRTC step after plane validation is done,
so we know what planes are (in)visible. The linked Y plane will get
updated in intel_plane_update_planes_on_crtc(), by the call to
update_slave, which gets
Op 21-09-18 om 18:40 schreef Matt Roper:
> On Fri, Sep 21, 2018 at 04:44:37PM +0200, Maarten Lankhorst wrote:
>> On skylake we can switch to a high quality scaler mode when only 1 out
>> of 2 scalers are used, but on GLK and later bit 28 has a different
>> meaning. Don't set it, and make clear the
On Fri, Sep 21, 2018 at 05:15:40PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-09-21 14:06:02)
> > On Thu, Sep 20, 2018 at 09:07:35PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2018-09-20 20:10:18)
> > > > From: Ville Syrjälä
> > > >
> > > > Let's try to make sure the fb
== Series Details ==
Series: drm/i915: Infoframe precompute/check (rev4)
URL : https://patchwork.freedesktop.org/series/49983/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4860_full -> Patchwork_10252_full =
== Summary - SUCCESS ==
No regressions found.
== Known is
On Fri, Sep 21, 2018 at 04:44:37PM +0200, Maarten Lankhorst wrote:
> On skylake we can switch to a high quality scaler mode when only 1 out
> of 2 scalers are used, but on GLK and later bit 28 has a different
> meaning. Don't set it, and make clear the distinction between
> SKL and later PS values.
On Fri, Sep 21, 2018 at 06:20:37PM +0200, Maarten Lankhorst wrote:
> Op 21-09-18 om 18:15 schreef Ville Syrjälä:
> > On Fri, Sep 21, 2018 at 06:00:27PM +0200, Maarten Lankhorst wrote:
> >> Op 21-09-18 om 17:26 schreef Ville Syrjälä:
> >>> On Thu, Sep 20, 2018 at 12:27:06PM +0200, Maarten Lankhorst
== Series Details ==
Series: drm/i915: Preparations for adding gen11 planar formats. (rev2)
URL : https://patchwork.freedesktop.org/series/49956/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4860_full -> Patchwork_10251_full =
== Summary - WARNING ==
Minor unknown chang
Op 21-09-18 om 18:15 schreef Ville Syrjälä:
> On Fri, Sep 21, 2018 at 06:00:27PM +0200, Maarten Lankhorst wrote:
>> Op 21-09-18 om 17:26 schreef Ville Syrjälä:
>>> On Thu, Sep 20, 2018 at 12:27:06PM +0200, Maarten Lankhorst wrote:
We need to assume the plane has been visible before, even if no
On Fri, Sep 21, 2018 at 06:00:27PM +0200, Maarten Lankhorst wrote:
> Op 21-09-18 om 17:26 schreef Ville Syrjälä:
> > On Thu, Sep 20, 2018 at 12:27:06PM +0200, Maarten Lankhorst wrote:
> >> We need to assume the plane has been visible before, even if no CRTC
> >> is assigned to the plane. This is be
Quoting Ville Syrjälä (2018-09-21 14:06:02)
> On Thu, Sep 20, 2018 at 09:07:35PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-09-20 20:10:18)
> > > From: Ville Syrjälä
> > >
> > > Let's try to make sure the fb offset computations never hit
> > > an integer overflow by making sure th
== Series Details ==
Series: drm/i915: Add AML id into KBL_ULX support list
URL : https://patchwork.freedesktop.org/series/50023/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4860 -> Patchwork_10253 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_1
Op 21-09-18 om 17:26 schreef Ville Syrjälä:
> On Thu, Sep 20, 2018 at 12:27:06PM +0200, Maarten Lankhorst wrote:
>> We need to assume the plane has been visible before, even if no CRTC
>> is assigned to the plane. This is because nv12 will enable a a extra
>> plane and make it visible by marking it
== Series Details ==
Series: drm/i915: Add AML id into KBL_ULX support list
URL : https://patchwork.freedesktop.org/series/50023/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Add AML id into KBL_ULX support list
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3718:
== Series Details ==
Series: drm/i915: Infoframe precompute/check (rev4)
URL : https://patchwork.freedesktop.org/series/49983/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4860 -> Patchwork_10252 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://
According to patch "drm/i915/aml: Introducing Amber Lake platform"
(e364672477a1). Amber Lake uses the same gen graphics as Kaby Lake.
And it is the member of KBL ULX series.
So far, IS_KBL_ULX macro did not include AML platform. It may caused
driver load DDI translation table for KBL H/S series f
== Series Details ==
Series: drm/i915: Infoframe precompute/check (rev4)
URL : https://patchwork.freedesktop.org/series/49983/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: video/hdmi: Constify 'buffer' to the unpack functions
Okay!
Commit: video/hdmi: Pass buffer size to
On Thu, Sep 20, 2018 at 12:27:10PM +0200, Maarten Lankhorst wrote:
> This cleans the code up slightly, and will make other changes easier.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 90 +
> 1 file changed, 52 insertions(+), 38 d
On Thu, Sep 20, 2018 at 12:27:06PM +0200, Maarten Lankhorst wrote:
> We need to assume the plane has been visible before, even if no CRTC
> is assigned to the plane. This is because nv12 will enable a a extra
> plane and make it visible by marking it in crtc_state->active_planes
> for intel_update_
== Series Details ==
Series: drm/i915: Infoframe precompute/check (rev4)
URL : https://patchwork.freedesktop.org/series/49983/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bd2b9221d985 video/hdmi: Constify 'buffer' to the unpack functions
865f880ff261 video/hdmi: Pass buffer s
== Series Details ==
Series: drm/i915: Preparations for adding gen11 planar formats. (rev2)
URL : https://patchwork.freedesktop.org/series/49956/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4860 -> Patchwork_10251 =
== Summary - SUCCESS ==
No regressions found.
Exte
From: Ville Syrjälä
Add the code to deal with the NTSC VBI infoframe.
I decided against parsing the PES_data_field and just leave
it as an opaque blob, just dumping it out as hex in the log.
Blindly typed from the spec, and totally untested.
v2: Rebase
Cc: Thierry Reding
Cc: Hans Verkuil
Cc
From: Ville Syrjälä
Add the code to deal with the MPEG source infoframe.
Blindly typed from the spec, and totally untested.
v2: Rebase
Cc: Thierry Reding
Cc: Hans Verkuil
Cc: linux-me...@vger.kernel.org
Signed-off-by: Ville Syrjälä
---
drivers/video/hdmi.c | 229 +++
On Fri, Sep 21, 2018 at 04:12:36PM +0200, Hans Verkuil wrote:
> On 09/21/18 16:01, Ville Syrjälä wrote:
> > On Fri, Sep 21, 2018 at 10:41:46AM +0200, Hans Verkuil wrote:
> >> On 09/20/18 20:51, Ville Syrjala wrote:
> >>> From: Ville Syrjälä
> >>>
> >>> We'll be wanting to send more than just infof
On Fri, Sep 21, 2018 at 03:59:06PM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2018 at 09:51:36PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make life simpler by passing around intel_encoder instead of
> > drm_encoder.
> >
> > @r1@
> > identifier F =~ "infoframe";
> > identifi
== Series Details ==
Series: drm/i915: Preparations for adding gen11 planar formats. (rev2)
URL : https://patchwork.freedesktop.org/series/49956/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Clean up casts to crtc_state in intel_atomic_commit_tail()
Okay!
Commit
== Series Details ==
Series: drm/i915: Preparations for adding gen11 planar formats. (rev2)
URL : https://patchwork.freedesktop.org/series/49956/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aa09781991ac drm/i915: Clean up casts to crtc_state in
intel_atomic_commit_tail()
dad
On skylake we can switch to a high quality scaler mode when only 1 out
of 2 scalers are used, but on GLK and later bit 28 has a different
meaning. Don't set it, and make clear the distinction between
SKL and later PS values.
Changes since v1:
- Add missing break statement.
Signed-off-by: Maarten
== Series Details ==
Series: drm/i915: Infoframe precompute/check (rev2)
URL : https://patchwork.freedesktop.org/series/49983/
State : failure
== Summary ==
Applying: video/hdmi: Constify 'buffer' to the unpack functions
Applying: video/hdmi: Pass buffer size to infoframe unpack functions
Appl
From: Ville Syrjälä
Let's make the infoframe pack functions usable with a const infoframe
structure. This allows us to precompute the infoframe earlier, and still
pack it later when we're no longer allowed to modify the structure.
So now we end up with a _check()+_pack_only() or _pack() functions
On Fri, Sep 21, 2018 at 10:24:25AM +0200, Hans Verkuil wrote:
> On 09/20/18 20:51, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Let's make the infoframe pack functions usable with a const infoframe
> > structure. This allows us to precompute the infoframe earlier, and still
> > pack it la
On Thu, Sep 20, 2018 at 09:51:37PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have definitions and low level code for everything except the gamut
> metadata HDMI packet. Add the missing bits.
>
> Signed-off-by: Ville Syrjälä
Online Bspec seems to have dropped pre-cpt/snb stuff, b
On 09/21/18 16:01, Ville Syrjälä wrote:
> On Fri, Sep 21, 2018 at 10:41:46AM +0200, Hans Verkuil wrote:
>> On 09/20/18 20:51, Ville Syrjala wrote:
>>> From: Ville Syrjälä
>>>
>>> We'll be wanting to send more than just infoframes over HDMI. So add an
>>> enum for other packet types.
>>>
>>> TODO:
On Fri, Sep 21, 2018 at 10:41:46AM +0200, Hans Verkuil wrote:
> On 09/20/18 20:51, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We'll be wanting to send more than just infoframes over HDMI. So add an
> > enum for other packet types.
> >
> > TODO: Maybe just include the infoframe types in
On Thu, Sep 20, 2018 at 09:51:36PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make life simpler by passing around intel_encoder instead of
> drm_encoder.
>
> @r1@
> identifier F =~ "infoframe";
> identifier I, M;
> @@
> F(
> - struct drm_encoder *I
> + struct intel_encoder *I
> , ..
On Fri, Sep 21, 2018 at 10:30:16AM +0200, Hans Verkuil wrote:
> On 09/20/18 20:51, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add the code to deal with the NTSC VBI infoframe.
> >
> > I decided against parsing the PES_data_field and just leave
> > it as an opaque blob, just dumping it
On Fri, Sep 21, 2018 at 10:28:09AM +0200, Hans Verkuil wrote:
> On 09/20/18 20:51, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add the code to deal with the MPEG source infoframe.
> >
> > Blindly typed from the spec, and totally untested.
>
> I'm not sure this patch should be added at
On Thu, Sep 20, 2018 at 09:51:35PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the hand rolled memmove() with the real thing.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 4 +---
> 1 file changed, 1 insertion(+), 3
On Fri, Sep 21, 2018 at 01:34:00AM -0700, Manasi Navare wrote:
> On Wed, Sep 19, 2018 at 01:57:00PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 18, 2018 at 02:10:17PM -0700, Manasi Navare wrote:
> > > On Tue, Sep 18, 2018 at 10:46:46PM +0300, Ville Syrjälä wrote:
> > > > On Tue, Sep 18, 2018 at 12:
On 21/09/2018 10:13, kedar.j.kara...@intel.com wrote:
From: Praveen Diwakar
High resoluton timer is used for this purpose.
Debugfs is provided to enable/disable/update timer configuration
Change-Id: I35d692c5afe962fcad4573185bc6f744487711d0
Signed-off-by: Praveen Diwakar
Signed-off-by: Yoge
On 21/09/2018 10:13, kedar.j.kara...@intel.com wrote:
From: Praveen Diwakar
This patch will select optimum eu/slice/sub-slice configuration based on type
of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platfor
On Thu, Sep 20, 2018 at 09:07:35PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-09-20 20:10:18)
> > From: Ville Syrjälä
> >
> > Let's try to make sure the fb offset computations never hit
> > an integer overflow by making sure the entire fb stays
> > below 32bits. framebuffer_check()
== Series Details ==
Series: drm/i915/selftests: Smoketest preemption
URL : https://patchwork.freedesktop.org/series/50002/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4859_full -> Patchwork_10247_full =
== Summary - SUCCESS ==
No regressions found.
== Known issue
== Series Details ==
Series: drm/i915/selftests: Smoketest preemption (rev2)
URL : https://patchwork.freedesktop.org/series/50002/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4859 -> Patchwork_10249 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwor
On 21/09/2018 10:13, kedar.j.kara...@intel.com wrote:
From: Praveen Diwakar
This patch will update power clock state register at runtime base on the
flag update_render_config which can set by any governor which computes load
and want to update rpcs register.
subsequent patches will have a time
On 21/09/2018 10:13, kedar.j.kara...@intel.com wrote:
From: Praveen Diwakar
This patch gives us the active pending request count which is yet
to be submitted to the GPU
Change-Id: I10c2828ad0f1a0b7af147835737134e07a2d5b6d
Signed-off-by: Praveen Diwakar
Signed-off-by: Yogesh Marathe
Signed-o
== Series Details ==
Series: drm/i915/selftests: Smoketest preemption (rev2)
URL : https://patchwork.freedesktop.org/series/50002/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/selftests: Smoketest preemption
+./include/linux/slab.h:631:13: error: undefined identif
== Series Details ==
Series: drm/i915/selftests: Smoketest preemption (rev2)
URL : https://patchwork.freedesktop.org/series/50002/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f3a04f9d05fe drm/i915/selftests: Smoketest preemption
-:92: WARNING:LINE_SPACING: Missing a blank lin
Hi,
On 21/09/2018 10:13, kedar.j.kara...@intel.com wrote:
From: "Kedar J. Karanje"
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel
Current GPU configuration code for i915 does not allow us to change
EU/Slice/Sub-slice configuration dynamically. Its done only on
On Thu, Sep 20, 2018 at 08:46:42PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-09-20 20:41:30)
> > On Thu, Sep 20, 2018 at 09:09:03AM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjälä (2018-09-19 17:59:51)
> > > > On Thu, Sep 13, 2018 at 11:01:40PM +0300, Ville Syrjala wrote:
> >
Very light stress test to bombard the submission backends with a large
stream with requests of randomly assigned priorities. Preemption will be
occasionally requested, but never succeed!
v2: Include a second pattern with more frequent preemption
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
== Series Details ==
Series: Dynamic EU configuration of Slice/Subslice/EU.
URL : https://patchwork.freedesktop.org/series/50006/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/i915_debugfs.
Hi all,
This is the final set of changes going for kernel v4.20,
as per agreement with Dave, I did the tagging now before
-rc5, and we should run some heavy testing on this during
the beginning of next week.
Regards, Joonas
The following changes tagged drm-intel-testing-2018-09-21:
drm-intel-ne
== Series Details ==
Series: drm/i915/selftests: Smoketest preemption
URL : https://patchwork.freedesktop.org/series/50002/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4859 -> Patchwork_10247 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10247 n
== Series Details ==
Series: drm/i915/selftests: Smoketest preemption
URL : https://patchwork.freedesktop.org/series/50002/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/selftests: Smoketest preemption
+./include/linux/slab.h:631:13: error: undefined identifier
'_
== Series Details ==
Series: drm/i915/selftests: Smoketest preemption
URL : https://patchwork.freedesktop.org/series/50002/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9badaef7a3f0 drm/i915/selftests: Smoketest preemption
-:50: WARNING:LINE_SPACING: Missing a blank line after
Quoting Tvrtko Ursulin (2018-09-21 11:00:06)
>
> On 20/09/2018 20:59, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-09-20 15:21:47)
> >>
> >> On 19/09/2018 20:55, Chris Wilson wrote:
> >>> Fix up the error unwind for logical_ring_init() failing by moving the
> >>
> >> Could you say in the c
On 20/09/2018 20:59, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-20 15:21:47)
On 19/09/2018 20:55, Chris Wilson wrote:
Fix up the error unwind for logical_ring_init() failing by moving the
Could you say in the commit what was broken?
We didn't cleanup all the state we allocated in
From: Praveen Diwakar
High resoluton timer is used for this purpose.
Debugfs is provided to enable/disable/update timer configuration
Change-Id: I35d692c5afe962fcad4573185bc6f744487711d0
Signed-off-by: Praveen Diwakar
Signed-off-by: Yogesh Marathe
Signed-off-by: Aravindan Muthukumar
Signed-o
From: Praveen Diwakar
This patch will select optimum eu/slice/sub-slice configuration based on type
of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platform(CHT, KBL).
i915_set_optimum_config will select optimum
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