== Series Details ==
Series: drm/i915/psr: Enable AUX-A IO power well on ICL for PSR (rev3)
URL : https://patchwork.freedesktop.org/series/49682/
State : failure
== Summary ==
Applying: drm/i915/psr: Enable AUX-A IO power well on ICL for PSR
error: corrupt patch at line 27
error: could not bui
Hi Dhinakaran,
I tested this patch. Now I am not able to see those "AUX Error Interrupts".
Thanks for your patch.
Regards
Jyoti
-Original Message-
From: Pandiyan, Dhinakaran
Sent: Friday, September 14, 2018 5:48 AM
To: intel-gfx@lists.freedesktop.org
Cc: Souza, Jose ; Deak, Imre ;
Pan
== Series Details ==
Series: drm/i915: Recover batch pool caches from shrinker (rev2)
URL : https://patchwork.freedesktop.org/series/49757/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4833_full -> Patchwork_10200_full =
== Summary - FAILURE ==
Serious unknown changes c
== Series Details ==
Series: drm/i915: Recover batch pool caches from shrinker (rev2)
URL : https://patchwork.freedesktop.org/series/49757/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4833 -> Patchwork_10200 =
== Summary - SUCCESS ==
No regressions found.
External U
Discard all of our batch pools under mempressure to make their pages
available to the shrinker. We will quickly reacquire them when necessary
for more GPU relocations or for the command parser.
v2: Init the lists for mock_engine
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107936
Signed
== Series Details ==
Series: ICELAKE DSI DRIVER (rev6)
URL : https://patchwork.freedesktop.org/series/44823/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4833 -> Patchwork_10199 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10199 absolutely nee
== Series Details ==
Series: ICELAKE DSI DRIVER (rev6)
URL : https://patchwork.freedesktop.org/series/44823/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Configure lane sequencing of combo phy transmitter
Okay!
Commit: drm/i915/icl: DSI vswing programming se
== Series Details ==
Series: ICELAKE DSI DRIVER (rev6)
URL : https://patchwork.freedesktop.org/series/44823/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
33aac050cb0a drm/i915/icl: Configure lane sequencing of combo phy transmitter
-:59: CHECK:BRACES: Blank lines aren't necess
== Series Details ==
Series: Add Plane Color Properties (rev5)
URL : https://patchwork.freedesktop.org/series/30875/
State : failure
== Summary ==
Applying: drm: Add Enhanced Gamma LUT precision structure
Applying: drm: Add Plane Degamma properties
error: sha1 information is lacking or useless
This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.
v2: Changes:
- Remove redundant extra line
- Correct some of bitfield definition
This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.
v2: Rebase
v3: Remove step hard coding comments (Jani N)
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 19 +++
1 file change
From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
GPU/Display Engine and same could be extended for future Intel platforms as
well.
DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.
So, a new DSI driver has been added inside I915.
Given below patches ar
This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.
v2: Rebase
v3: Add empty line to make code more legible (Ville).
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/d
As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.
v2: Remove TRANS_TIMING_SHIFT usage
Signed-off-by: Madhav Chauhan
---
drive
This patch enables DSI transcoders by writing to
TRANS_CONF registers and wait for its state to be enabled.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/icl_dsi.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/
This patch adds _MMIO_DSI macros for accessing DSI
transcoder registers.
v2: Use _MMIO_TRANS() (Ville)
Credits-to: Jani N
Cc: Jani Nikula
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
v2: Changes
- Don't use KHz() macro (Ville/
This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.
v2: Changes (Jani N)
- Define mask/shift for bitfields
- Use bitfields name as per BSPEC
- Define remaining bitfields
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h
This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/icl_dsi.c | 9 +
drivers/gpu/drm/i915/intel_display.h | 6 --
2 files changed, 13 inserti
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 4
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i9
This is how a typical display color hardware pipeline looks like:
+---+
|RAM|
| +--++-++-+ |
| | FB 1 || FB 2 || FB N| |
| +--++-++-+
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/icl_dsi.c | 28
1 file changed, 28 insertions(
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
v4: Used extended function for LUT extraction (pointed by
Alexandru).
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pc
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
v2: Use newly defined bitfields for data and
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
v4: Rebase
v5: Moved helper function to drm_color_mgmt.c file to have all
color operations consolidated at one place. N
This patch defines registers and bitfields used for
programming DSI transcoder's horizontal and vertical
timings.
v2: Remove TRANS_TIMING_SHIFT definition
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/
Add Plane Degamma as a blob property and plane degamma size as
a range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Adde
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
v2: Changes (Jani N)
- Define _SHIFT and _MASK for bitfields
- Define values for fields already shifted in place
Signed-off-by: Madhav Chauh
This patch defines DSI_CMD_RXCTL, DSI_CMD_TXCTL registers,
bitfields, masks and macros used for configuring DSI panel.
v2: Define remaining bitfields
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 38 ++
1 file changed, 38 insertions(+)
Add a blob property for plane CSC usage.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.
v2: Rebase
v3: Use newly defined bitfields.
Signed
This patch select input PIPE for DSI, data lanes width,
enable port sync mode and wait for DSI link to become ready.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/icl_dsi.c | 61 +++---
1 file changed, 57 insertions(+), 4 deletions(-)
diff --git a/dr
This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.
v2: Define mask/shift for bitfields and keep names as per BSPEC (Jani N)
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 58 ++
This patch defines TRANS_CONF registers for DSI ports
0 and 1. Bitfields of these registers used for enabling
and reading the current state of transcoder.
v2: Add blank line before comment
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/i915_reg.h
This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.
v2: Rebase
v3: Remove step hard coding comments (Jani N)
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 22 ++
This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.
v2: Rebase
v3: Address various review comments related to VSWING
pr
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values. Also added the code,
for extracting the same from values passed from userspace.
v
Add plane gamma as blob property and size as a
range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documen
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h
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