== Series Details ==
Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev6)
URL : https://patchwork.freedesktop.org/series/48803/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4745 -> Patchwork_10057 =
== Summary - SUCCESS ==
No regressions found.
Extern
This patch resolves the DMC FW loading issue.
Earlier DMC FW package have only one DMC FW for one stepping. But as such
there is no such restriction from Package side.
For ICL icl_dmc_ver1_07.bin binary package has DMC FW for 2 steppings.
So while reading the dmc_offset from package header, for 1st
== Series Details ==
Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev5)
URL : https://patchwork.freedesktop.org/series/48803/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4745 -> Patchwork_10056 =
== Summary - SUCCESS ==
No regressions found.
Extern
== Series Details ==
Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev5)
URL : https://patchwork.freedesktop.org/series/48803/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5e4f9c90b0db drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL.
-:10: WARNING:COMMIT_
From: Jyoti
This patch resolves the DMC FW loading issue.
Earlier DMC FW package have only one DMC FW for one stepping. But as such
there is no such restriction from Package side.
For ICL icl_dmc_ver1_07.bin binary package has DMC FW for 2 steppings.
So while reading the dmc_offset from package h
From: Jyoti
BIOS programs few of PWM related registers during initial boot.
But during System suspend those registers are cleared.
This test aim to check whether display programs those registers properly after
system resume.
Also checks brightness programming during DPMS ON/OFF cycle to check bac
== Series Details ==
Series: drm/i915/ringbuffer: Delay after invalidating gen6+ xcs (rev2)
URL : https://patchwork.freedesktop.org/series/48813/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4741_full -> Patchwork_10055_full =
== Summary - WARNING ==
Minor unknown chang
On Wed, 2018-08-29 at 12:18 -0700, Wajdeczko, Michal wrote:
> Gen11 defines new register for checking HuC authentication status.
> Look into the right register and bit.
>
> BSpec: 19686
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: Tony Ye
> Cc: Vinay Belg
On Wed, 2018-08-29 at 12:10 -0700, Wajdeczko, Michal wrote:
> Definition of the parameters block passed to GuC is about to change.
> Slightly refactor code now to make upcoming patch smaller.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: John Spotswood
Reviewed-by: John Spots
On Wed, 2018-08-29 at 12:10 -0700, Wajdeczko, Michal wrote:
> Gen11 GuC boot parameter definitions are different than previously
> used for Gen9. Try to support both definitions until new firmwares
> for pre-Gen11 will be available.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc:
On Wed, 2018-08-29 at 12:10 -0700, Wajdeczko, Michal wrote:
> Upcoming Gen11 GuC firmware requires new interface that is
> incompatible
> with existing pre-Gen11 firmwares. Updated firmwares for pre-Gen11
> will
> arrive later. In the meantime sanitize the enable_guc option so that
> we
> can enabl
On 29/08/18 17:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which allo
== Series Details ==
Series: series starting with [v4,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/48960/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4740_full -> Patchwork_10054_full =
== Summary - FAILURE ==
Seriou
== Series Details ==
Series: Add XYUV format support (rev5)
URL : https://patchwork.freedesktop.org/series/48007/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4740_full -> Patchwork_10053_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10053
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4)
URL : https://patchwork.freedesktop.org/series/48906/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4740_full -> Patchwork_10052_full =
== Summary - SUCCESS ==
No regress
On Thu, Aug 30, 2018 at 06:48:45PM +0300, Ville Syrjälä wrote:
> On Tue, Aug 28, 2018 at 01:36:22PM -0700, Rodrigo Vivi wrote:
> > On Tue, Aug 28, 2018 at 06:32:01PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> >
== Series Details ==
Series: drm/i915: clear error registers after error capture (rev4)
URL : https://patchwork.freedesktop.org/series/48939/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10050_full =
== Summary - SUCCESS ==
No regressions found.
On Thu, 2018-08-30 at 13:57 +0100, Lisovskiy, Stanislav wrote:
> On Wed, 2018-08-29 at 12:16 -0700, Dhinakaran Pandiyan wrote:
> >
> > On Wed, 2018-08-29 at 21:10 +0300, Ville Syrjälä wrote:
> > > On Wed, Aug 29, 2018 at 02:28:47PM +0300, Stanislav Lisovskiy
> > > wrote:
> > > > PLANE_CTL_FORMAT_A
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions
and fourcc
URL : https://patchwork.freedesktop.org/series/48947/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10049_full =
== Summary - SUCCESS ==
== Series Details ==
Series: drm/i915/ringbuffer: Delay after invalidating gen6+ xcs (rev2)
URL : https://patchwork.freedesktop.org/series/48813/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4741 -> Patchwork_10055 =
== Summary - SUCCESS ==
No regressions found.
Exte
== Series Details ==
Series: drm/i915: Reduce context HW ID lifetime (rev2)
URL : https://patchwork.freedesktop.org/series/44134/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10046_full =
== Summary - SUCCESS ==
No regressions found.
== Known
On 08/08/2018 15:59, Chris Wilson wrote:
Normalize the variance to stddev, and remove some redundant steps in
computing the time from itself.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/perf_pmu.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
d
On 08/08/2018 15:59, Chris Wilson wrote:
Our observation is that the systematic error is proportional to the
number of iterations we perform; the suspicion is that it directly
correlates with the number of sleeps. Reduce the number of iterations,
to try and keep the error in check.
Signed-off-b
== Series Details ==
Series: series starting with [1/9] drm/i915/execlists: Avoid kicking priority
on the current context
URL : https://patchwork.freedesktop.org/series/48936/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739_full -> Patchwork_10045_full =
== Summary - SU
On 30/08/2018 11:24, Chris Wilson wrote:
Future gen reduce the number of bits we will have available to
differentiate between contexts, so reduce the lifetime of the ID
assignment from that of the context to its current active cycle (i.e.
only while it is pinned for use by the HW, will it have a
On 30/08/2018 15:11, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-08-30 14:24:24)
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
v3: Don't read gen8 register on < gen6 (Chris)
v4: D
== Series Details ==
Series: series starting with [v4,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/48960/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4740 -> Patchwork_10054 =
== Summary - SUCCESS ==
No regressions f
During stress testing of full-ppgtt (on Baytrail at least), we found
that the invalidation around a context/mm switch was insufficient (writes
would go astray). Adding a second MI_FLUSH_DW barrier prevents this, but
it is unclear as to whether this is merely a delaying tactic or if it is
truly seri
== Series Details ==
Series: Add XYUV format support (rev5)
URL : https://patchwork.freedesktop.org/series/48007/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4740 -> Patchwork_10053 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.fre
== Series Details ==
Series: series starting with [v4,1/2] drm: Add connector property to limit max
bpc
URL : https://patchwork.freedesktop.org/series/48960/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a2b1ae142db2 drm: Add connector property to limit max bpc
3555676ce4a1 dr
On Tue, Aug 28, 2018 at 01:36:22PM -0700, Rodrigo Vivi wrote:
> On Tue, Aug 28, 2018 at 06:32:01PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> > mgr into the clock readout function as well.
> >
> > Bugzilla: https://b
On Tue, Aug 28, 2018 at 06:04:29PM +0100, Chris Wilson wrote:
> During stress testing of full-ppgtt (on Baytrail at least), we found
> that the invalidation around a context/mm switch was insufficient (writes
> would go astray). Adding a second MI_FLUSH_DW barrier prevents this, but
> it is unclear
== Series Details ==
Series: Add XYUV format support (rev5)
URL : https://patchwork.freedesktop.org/series/48007/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
48d9e0cf5f5e drm: Introduce new DRM_FORMAT_XYUV
-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/g
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4)
URL : https://patchwork.freedesktop.org/series/48906/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4740 -> Patchwork_10052 =
== Summary - SUCCESS ==
No regressions found
Hi Dave,
Here's the first PR for 4.20 (Seth Rogan edition). It's super light compared to
most PRs after feature freeze. Perhaps we were all enjoying summer a bit too
much! Anyways, nothing controversial, tag description says it all.
drm-misc-next-2018-08-30:
drm-misc-next for 4.20:
UAPI Changes:
On Thu, Aug 30, 2018 at 08:06:48AM -0700, Radhakrishna Sripada wrote:
> At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> level shifters etc. To workaround them we may need to drive the output
> at a lower bpc. Currently the user space does not have a way to limit
> the bpc. The
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev4)
URL : https://patchwork.freedesktop.org/series/48906/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
41720addaafc drm/i915/selftests: Add a simple exerciser for suspend/hibernate
Use the newly added "max bpc" connector property to limit pipe bpp.
V3: Use drm_connector_state to access the "max bpc" property
V4: Initialize the drm property, add suuport to DP(Ville)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Kishore Kadiyala
Cc: Manasi Navare
Cc: Stanislav Lisovskiy
Signed-
At times 12bpc HDMI cannot be driven due to faulty cables, dongles
level shifters etc. To workaround them we may need to drive the output
at a lower bpc. Currently the user space does not have a way to limit
the bpc. The default bpc to be programmed is decided by the driver and
is run against conne
== Series Details ==
Series: linux/mei: Header for mei_hdcp driver interface
URL : https://patchwork.freedesktop.org/series/48922/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4738_full -> Patchwork_10043_full =
== Summary - SUCCESS ==
No regressions found.
== Know
On 30/08/2018 14:29, Lis, Tomasz wrote:
On 2018-08-30 02:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW
== Series Details ==
Series: Add XYUV format support (rev4)
URL : https://patchwork.freedesktop.org/series/48007/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10051 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.fre
== Series Details ==
Series: drm/i915: clear error registers after error capture (rev4)
URL : https://patchwork.freedesktop.org/series/48939/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10050 =
== Summary - SUCCESS ==
No regressions found.
External
== Series Details ==
Series: Add XYUV format support (rev4)
URL : https://patchwork.freedesktop.org/series/48007/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e971390c33e8 drm: Introduce new DRM_FORMAT_XYUV
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/g
Introduced new XYUV scan-in format for framebuffer and
added support for it to i915(SkyLake+).
Stanislav Lisovskiy (2):
drm: Introduce new DRM_FORMAT_XYUV
drm/i915: Adding YUV444 packed format support for skl+
drivers/gpu/drm/drm_fourcc.c | 1 +
drivers/gpu/drm/i915/i915_reg.h
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more
Uhh, sorry - answered on wrong patch.
Please ignore this one.
-Tomasz
On 2018-08-30 15:29, Lis, Tomasz wrote:
On 2018-08-30 02:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 2018-08-30 02:08, Lionel Landwerlin wrote:
On 29/08/2018 20:16, Michal Wajdeczko wrote:
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and
Quoting Lionel Landwerlin (2018-08-30 14:24:24)
> We need to clear the register in order to get correct value after the
> next potential hang.
>
> v2: Centralize error register clearing in i915_irq.c (Chris)
>
> v3: Don't read gen8 register on < gen6 (Chris)
>
> v4: Don't swap gen8+ & gen6+ code
== Series Details ==
Series: drm/i915: clear error registers after error capture (rev4)
URL : https://patchwork.freedesktop.org/series/48939/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: clear error registers after error capture
-drivers/gpu/drm/i915/selftests/..
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions
and fourcc
URL : https://patchwork.freedesktop.org/series/48947/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10049 =
== Summary - SUCCESS ==
No regre
On Thu, Aug 30, 2018 at 03:41:13PM +0300, Juha-Pekka Heikkila wrote:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> (Sharma, Swati2): removed unnecessary checks, changed debug error message
> to be more generic.
>
> Signed-off-
On Thu, Aug 30, 2018 at 04:40:27PM +0300, Stanislav Lisovskiy wrote:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
>
> v2: Edited commit message, removed redundant whitespaces.
>
> v3: Fixed fallthrough logic for the format switch cases.
>
> v4: Yet again f
Although we cannot do a full system-level test of suspend/hibernate from
deep with the kernel selftests, we can exercise the GEM subsystem in
isolation and simulate the external effects (such as losing stolen
contents and trashing the register state).
v2: Don't forget to hold rpm
v3: Suspend the G
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions
and fourcc
URL : https://patchwork.freedesktop.org/series/48947/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: Add P010, P012, P016 format definitions and fourcc
Okay!
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev3)
URL : https://patchwork.freedesktop.org/series/48906/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10048 =
== Summary - SUCCESS ==
No regressions found
== Series Details ==
Series: series starting with [1/4] drm: Add P010, P012, P016 format definitions
and fourcc
URL : https://patchwork.freedesktop.org/series/48947/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c67c3d800643 drm: Add P010, P012, P016 format definitions and fou
Introduced new XYUV scan-in format for framebuffer and
added support for it to i915(SkyLake+).
Stanislav Lisovskiy (2):
drm: Introduce new DRM_FORMAT_XYUV
drm/i915: Adding YUV444 packed format support for skl+
drivers/gpu/drm/drm_fourcc.c | 1 +
drivers/gpu/drm/i915/i915_reg.h |
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
v8: Edited commit message to be more
On Wed, Aug 29, 2018 at 03:57:05PM -0700, Radhakrishna Sripada wrote:
> On Mon, Aug 27, 2018 at 04:31:49PM +0300, Ville Syrjälä wrote:
> > On Fri, Aug 24, 2018 at 06:02:16PM -0700, Radhakrishna Sripada wrote:
> > > At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> > > level shift
On 2018-08-30 02:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which al
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
v3: Don't read gen8 register on < gen6 (Chris)
v4: Don't swap gen8+ & gen6+ code... (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chri
== Series Details ==
Series: drm/i915: clear error registers after error capture (rev3)
URL : https://patchwork.freedesktop.org/series/48939/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10047 =
== Summary - SUCCESS ==
No regressions found.
External
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev3)
URL : https://patchwork.freedesktop.org/series/48906/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c308e9f7b94b drm/i915/selftests: Add a simple exerciser for suspend/hibernate
== Series Details ==
Series: drm/i915: clear error registers after error capture (rev3)
URL : https://patchwork.freedesktop.org/series/48939/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: clear error registers after error capture
-drivers/gpu/drm/i915/selftests/..
== Series Details ==
Series: drm/i915: Reduce context HW ID lifetime (rev2)
URL : https://patchwork.freedesktop.org/series/44134/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10046 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https
On 30/08/2018 13:04, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-08-30 12:55:32)
+ if (INTEL_GEN(dev_priv) >= 8) {
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dev_priv, id) {
+
On Wed, 2018-08-29 at 12:16 -0700, Dhinakaran Pandiyan wrote:
>
> On Wed, 2018-08-29 at 21:10 +0300, Ville Syrjälä wrote:
> > On Wed, Aug 29, 2018 at 02:28:47PM +0300, Stanislav Lisovskiy
> > wrote:
> > > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > > specification.
> > >
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
(Sharma, Swati2) Rename glk format table to follow similar style as on skl.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_display.c | 24 +++-
drivers/gpu/drm/i
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
(Sharma, Swati2): removed unnecessary checks, changed debug error message
to be more generic.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +--
d
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f232178..2c959c8 100644
Add P010 definition, semi-planar yuv format where each component
is 16 bits 10 msb containing color value. First come Y plane [10:6]
followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
Add P012 definition, semi-planar yuv format where each component
is 16 bits 12 msb containing color value. First c
== Series Details ==
Series: drm/i915: Reduce context HW ID lifetime (rev2)
URL : https://patchwork.freedesktop.org/series/44134/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Reduce context HW ID lifetime
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3685:16: war
== Series Details ==
Series: drm/i915: Reduce context HW ID lifetime (rev2)
URL : https://patchwork.freedesktop.org/series/44134/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
30bb0eb3b07e drm/i915: Reduce context HW ID lifetime
-:50: CHECK:UNCOMMENTED_DEFINITION: struct mutex
== Series Details ==
Series: series starting with [1/9] drm/i915/execlists: Avoid kicking priority
on the current context
URL : https://patchwork.freedesktop.org/series/48936/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4739 -> Patchwork_10045 =
== Summary - SUCCESS ==
== Series Details ==
Series: series starting with [1/9] drm/i915/execlists: Avoid kicking priority
on the current context
URL : https://patchwork.freedesktop.org/series/48936/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/execlists: Avoid kicking priority on the c
== Series Details ==
Series: series starting with [1/9] drm/i915/execlists: Avoid kicking priority
on the current context
URL : https://patchwork.freedesktop.org/series/48936/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
463c9506f450 drm/i915/execlists: Avoid kicking priority
Although we cannot do a full system-level test of suspend/hibernate from
deep with the kernel selftests, we can exercise the GEM subsystem in
isolation and simulate the external effects (such as losing stolen
contents and trashing the register state).
v2: Don't forget to hold rpm
v3: Suspend the G
Quoting Lionel Landwerlin (2018-08-30 12:55:32)
> + if (INTEL_GEN(dev_priv) >= 8) {
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> +
> + for_each_engine(engine, dev_priv, id) {
> + I915_WRITE(RING_FAULT_REG(en
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
v3: Don't read gen8 register on < gen6 (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev2)
URL : https://patchwork.freedesktop.org/series/48906/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4738 -> Patchwork_10044 =
== Summary - SUCCESS ==
No regressions found
Quoting Lionel Landwerlin (2018-08-30 12:41:42)
> On 30/08/2018 12:23, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2018-08-30 12:15:07)
> >> We need to clear the register in order to get correct value after the
> >> next potential hang.
> >>
> >> v2: Centralize error register clearing in i91
On 30/08/2018 12:23, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-08-30 12:15:07)
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
Signed-off-by: Lionel Landwerlin
Ok, I was thinking
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate (rev2)
URL : https://patchwork.freedesktop.org/series/48906/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
87bb0faa6d38 drm/i915/selftests: Add a simple exerciser for suspend/hibernate
== Series Details ==
Series: linux/mei: Header for mei_hdcp driver interface
URL : https://patchwork.freedesktop.org/series/48922/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4738 -> Patchwork_10043 =
== Summary - SUCCESS ==
No regressions found.
External URL:
http
Quoting Lionel Landwerlin (2018-08-30 12:15:07)
> We need to clear the register in order to get correct value after the
> next potential hang.
>
> v2: Centralize error register clearing in i915_irq.c (Chris)
>
> Signed-off-by: Lionel Landwerlin
Ok, I was thinking of move the code around the fil
We need to clear the register in order to get correct value after the
next potential hang.
v2: Centralize error register clearing in i915_irq.c (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 18 ++
== Series Details ==
Series: linux/mei: Header for mei_hdcp driver interface
URL : https://patchwork.freedesktop.org/series/48922/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
45780f07f979 linux/mei: Header for mei_hdcp driver interface
-:22: WARNING:TYPO_SPELLING: 'uneeded' m
On 30/08/2018 11:55, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-08-30 11:52:28)
We need to clear the register in order to get correct value after the
next potential hang.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++
1 file changed, 2 insertions
Quoting Bartminski, Jakub (2018-08-30 11:47:21)
> On Thu, 2018-08-30 at 10:52 +0100, Chris Wilson wrote:
>
> > +static int igt_gem_suspend(void *arg)
> [...]
> > + if (i915_gem_suspend(i915)) {
> > + pr_err("i915_gem_suspend failed\n");
> > + err = -EINVAL;
> > +
Quoting Lionel Landwerlin (2018-08-30 11:52:28)
> We need to clear the register in order to get correct value after the
> next potential hang.
>
> Signed-off-by: Lionel Landwerlin
> ---
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gp
We need to clear the register in order to get correct value after the
next potential hang.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error
On Thu, 2018-08-30 at 10:52 +0100, Chris Wilson wrote:
> +static int igt_gem_suspend(void *arg)
[...]
> + if (i915_gem_suspend(i915)) {
> + pr_err("i915_gem_suspend failed\n");
> + err = -EINVAL;
> + goto out;
> + }
> +
> + i915_gem_suspend_late(i915
On Thu, Aug 30, 2018 at 09:44:33AM +0100, Chris Wilson wrote:
> Currently we wrap our fd inside a FILE* stream to make use of vfprintf,
> but the man page leaves the question of errno and signal handling in
> doubt. It is documented as returning a negative value and setting
> ferror(), but we have
Future gen reduce the number of bits we will have available to
differentiate between contexts, so reduce the lifetime of the ID
assignment from that of the context to its current active cycle (i.e.
only while it is pinned for use by the HW, will it have a constant ID).
This means that instead of a
That we use a WB mapping for updating the RING_TAIL register inside the
context image even on !llc machines has been a source of consternation
for every reader. It appears to work on bsw+, but it may just have been
that we have been incredibly bad at detecting the errors.
v2: With extra enthusiasm
The information presented here is not relevant to current development.
We can either use the context information, but more often we want to
inspect the active gpu state.
The ulterior motive is to eradicate dev->filelist.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 119
In the sequence
<0>[ 531.960431] drv_self-48067 527402570us : intel_gpu_reset:
engine_mask=1, ret=0, retry=0
<0>[ 531.960431] drv_self-48067 527402571us : execlists_reset: rcs0
request global=115de, current=71133
<0>[ 531.960431] drv_self-48067d..1 527402571us :
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