Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

Hi Matt, On 7/27/2018 9:21 AM, Matt Turner wrote: On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote: Bspec: 4381 Do we know that these numbers are stable? yes these numbers are fixed in Bspec I don't know if this form is common in the kernel, but in Mesa we specify the name of the page w

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote: > Bspec: 4381 Do we know that these numbers are stable? I don't know if this form is common in the kernel, but in Mesa we specify the name of the page which should always allow readers to find it. __

Re: [Intel-gfx] [PATCH] drm/i915: Allow control of PSR at runtime through debugfs, v3.

On Thu, 2018-07-26 at 11:06 +0200, Maarten Lankhorst wrote: > Currently tests modify i915.enable_psr and then do a modeset cycle > to change PSR. We can write a value to i915_edp_psr_status to force > a certain value without a modeset. > > To retain compatibility with older userspace, we also stil

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: WaPsrDisableDpfcClkGating for glk and cnl

== Series Details == Series: drm/i915: WaPsrDisableDpfcClkGating for glk and cnl URL : https://patchwork.freedesktop.org/series/47310/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4554_full -> Patchwork_9787_full = == Summary - WARNING == Minor unknown changes coming wi

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: WaPsrDisableDpfcClkGating for glk and cnl

== Series Details == Series: drm/i915: WaPsrDisableDpfcClkGating for glk and cnl URL : https://patchwork.freedesktop.org/series/47310/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4554 -> Patchwork_9787 = == Summary - SUCCESS == No regressions found. External URL: h

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations

== Series Details == Series: series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations URL : https://patchwork.freedesktop.org/series/47309/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4554 -> Patchwork_9786 = == Summary - FAILURE == Serious unknown

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm: Let userspace check if driver supports modeset

== Series Details == Series: series starting with [01/10] drm: Let userspace check if driver supports modeset URL : https://patchwork.freedesktop.org/series/47305/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4554_full -> Patchwork_9785_full = == Summary - FAILURE == S

Re: [Intel-gfx] [PATCH] drm/i915/psr: Limit psr2 to skl+

1;5202;0cOn Wed, Jul 25, 2018 at 11:47:21PM -0700, Dhinakaran Pandiyan wrote: > On Thu, 2018-07-26 at 11:32 +0530, vathsala nagaraju wrote: > > From: Vathsala Nagaraju > > > > PSR2 is supported from skl+. > > So Limiting it to skl+. > > We restrict PSR2 to gen9+ in intel_psr_init_dpcd(), avoids

[Intel-gfx] [PATCH] drm/i915: WaPsrDisableDpfcClkGating for glk and cnl

"Host modification in FBC does not trigger PSR to exit sleep state" Since we are relying more on HW tracking lately it is better to protect this gen10 displays. Cc: Arthur J Runyan Cc: Dhinakaran Pandiyan Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i

[Intel-gfx] [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction

For a TBT sequence, we need to set the IO type to TBT in DDI_AUX_CTL. v2: Avoid duplications.(Paulo) Cc: Paulo Zanoni Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 26 +- 2 files changed, 18 insertions(+),

[Intel-gfx] [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations

Add missing TBT check in the Pll calculation. v2: do not use a auxiliary function to check if status is TBT or not. (Paulo) v3: Code style changes. (Paulo) Cc: Paulo Zanoni Cc: Lucas De Marchi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +++- 1 file changed,

Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations

>-Original Message- >From: Zanoni, Paulo R >Sent: Wednesday, July 25, 2018 3:41 PM >To: Srivatsa, Anusha ; intel- >g...@lists.freedesktop.org >Cc: De Marchi, Lucas >Subject: Re: [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations > >Em Qua, 2018-07-25 às 14:28 -0700, Anusha Sri

Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction

>-Original Message- >From: Zanoni, Paulo R >Sent: Wednesday, July 25, 2018 4:08 PM >To: Srivatsa, Anusha ; intel- >g...@lists.freedesktop.org >Subject: Re: [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction > >Em Qua, 2018-07-25 às 14:28 -0700, Anusha Srivatsa escreveu: >> For a TBT

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/10] drm: Let userspace check if driver supports modeset

== Series Details == Series: series starting with [01/10] drm: Let userspace check if driver supports modeset URL : https://patchwork.freedesktop.org/series/47305/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4554 -> Patchwork_9785 = == Summary - SUCCESS == No regressi

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/10] drm: Let userspace check if driver supports modeset

== Series Details == Series: series starting with [01/10] drm: Let userspace check if driver supports modeset URL : https://patchwork.freedesktop.org/series/47305/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: Let userspace check if driver supports modeset Okay! Comm

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm: Let userspace check if driver supports modeset

== Series Details == Series: series starting with [01/10] drm: Let userspace check if driver supports modeset URL : https://patchwork.freedesktop.org/series/47305/ State : warning == Summary == $ dim checkpatch origin/drm-tip 567aacc6c2de drm: Let userspace check if driver supports modeset 78

[Intel-gfx] [PATCH 04/10] drm/i915: Move out non-display related calls from display/modeset init/cleanup

i915_load_modeset_init() and intel_modeset_cleanup() was initializing and cleaning up things that is not display only. This will make easy initialize driver without display block. Also moving VLV/CHV/BYT czclk as it is a core clock used as base by several other GPU blocks not only display, includi

[Intel-gfx] [PATCH 02/10] drm/i915: Set PCH as NOP when display is disabled

num_pipes is set to 0 if disable_display is set inside intel_device_info_runtime_init() but when that happen PCH will already be set in intel_detect_pch(). i915_driver_load() i915_driver_init_early() ... intel_detect_pch() ... ...

[Intel-gfx] [PATCH 05/10] drm/i915: Move drm_vblank_init() to i915_load_modeset_init()

i915_load_modeset_init() is a more suitable place than i915_driver_load() as vblank is part of modeset. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv

[Intel-gfx] [PATCH 09/10] drm/i915: Do not call modeset related functions when display is disabled

No need to run i915_load_modeset_init() when num_pipes == 0 also kms depends on things initialized in i915_load_modeset_init() so not initializing it too. fbdev and audio have guards against num_pipes == 0 but lets move it to the if block to make it explicit to readers. Also as planes, CRTCs, enco

[Intel-gfx] [PATCH 01/10] drm: Let userspace check if driver supports modeset

GPU accelerators usually don't have display block or the display driver part can be disabled when building driver(for servers it saves some resources) so it is important let userspace check this capability too. Right now we are checking drmModeGetResources()/drm_mode_getresources() for a error to

[Intel-gfx] [PATCH 08/10] drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()

IPC(Isochronous Priority Control not Inter-process communication btw) is a display feature, so i915_load_modeset_init() is the right place to initialize it. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --

[Intel-gfx] [PATCH 06/10] drm/i915: Move FBC init and cleanup calls to modeset functions

Although FBC helps save power it do not belongs to power management also the cleanup was placed in i915_driver_unload() also not a good place. intel_modeset_init()/intel_modeset_cleanup() are better places also this will help make easy disable features that depends in display being enabled in drive

[Intel-gfx] [PATCH 07/10] drm/i915: Do not modifiy reserved bit in gens that do not have IPC

IPC was only added in SKL+(actually we don't even enable for SKL due WA) so without this change, driver was writing to a reserved bit. Also check for the WA in intel_init_ipc() to avoid further writes to ipc_enabled. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_pm.c | 8 +

[Intel-gfx] [PATCH 10/10] drm/i915: Remove redundant checks for num_pipes == 0

This 'if's will always be false because of previous changes so let's drop then. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 12 +++- drivers/gpu/drm/i915/intel_audio.c | 3 --- drivers/gpu/drm/i915/intel_display.c | 3 --- drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH 03/10] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake

Instead of have the same code spread into 4 platforms lets share it. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++--- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers

Re: [Intel-gfx] [PATCH] drm/i915/psr: Print PSR_STATUS when PSR idle wait times out.

On Wed, Jul 25, 2018 at 09:54:44PM -0700, Dhinakaran Pandiyan wrote: > Knowing the status of the PSR HW state machine is useful for debug, > especially since we are seeing errors with PSR2 in CI. > > Cc: Rodrigo Vivi > Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi > --- > driv

Re: [Intel-gfx] [PATCH] drm/i915/icl: don't set CNL_DDI_CLOCk_REG_ACCESS_ON anymore

On Wed, 2018-07-25 at 17:12 -0700, Paulo Zanoni wrote: > The new recommendation from the spec is to simply not set this bit > anymore. Not setting the bit would prevent some hangs that our driver > manages to avoid since commit c8af5274c3cb ("drm/i915: enable the > pipe/transcoder/planes later on H

[Intel-gfx] [PATCH i-g-t] igt/gem_mocs_settings: Use i915_pmu to measure rc6 residency

Use the perf pmu interface for lowlevel rc6 measurement, hopefully for greater stability. Signed-off-by: Chris Wilson --- tests/Makefile.am | 1 + tests/gem_mocs_settings.c | 47 ++- tests/meson.build | 8 ++- 3 files changed, 40 insertio

[Intel-gfx] [PATCH i-g-t] igt/gem_mocs_settings: Use i915_pmu to measure rc6 residency

Use the perf pmu interface for lowlevel rc6 measurement, hopefully for greater stability. Signed-off-by: Chris Wilson --- tests/Makefile.am | 1 + tests/gem_mocs_settings.c | 45 +++ tests/meson.build | 8 ++- 3 files changed, 39 insertio

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Downgrade Gen9 Plane WM latency error

== Series Details == Series: drm/i915: Downgrade Gen9 Plane WM latency error URL : https://patchwork.freedesktop.org/series/47296/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4554_full -> Patchwork_9784_full = == Summary - WARNING == Minor unknown changes coming with P

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Downgrade Gen9 Plane WM latency error

== Series Details == Series: drm/i915: Downgrade Gen9 Plane WM latency error URL : https://patchwork.freedesktop.org/series/47296/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4554 -> Patchwork_9784 = == Summary - SUCCESS == No regressions found. External URL: https

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, Here goes drm-intel-fixes-2018-07-26: - Only a quirk for GLK NUC HDMI port issues Thanks, Rodrigo. The following changes since commit d72e90f33aa4709ebecc5005562f52335e106a60: Linux 4.18-rc6 (2018-07-22 14:12:20 -0700) are available in the Git repository at: git://anongit.freede

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

== Series Details == Series: series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias URL : https://patchwork.freedesktop.org/series/47201/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4554 -> Patchwork_9783 = == Summary - FAILURE == S

[Intel-gfx] [PATCH] drm/i915: Downgrade Gen9 Plane WM latency error

According to intel_read_wm_latency() it is perfectly legal for one WM and all subsequent levels to be 0 (and the deeper powersaving states disabled), so don't shout *ERROR*, over and over again. Signed-off-by: Chris Wilson Cc: Maarten Lankhorst Cc: Ville Syrjala --- drivers/gpu/drm/i915/intel_

[Intel-gfx] ✓ Fi.CI.IGT: success for Decode memdev info and bandwidth and implemnt latency WA (rev2)

== Series Details == Series: Decode memdev info and bandwidth and implemnt latency WA (rev2) URL : https://patchwork.freedesktop.org/series/46481/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4551_full -> Patchwork_9782_full = == Summary - WARNING == Minor unknown chang

[Intel-gfx] ✓ Fi.CI.IGT: success for Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit.

== Series Details == Series: Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit. URL : https://patchwork.freedesktop.org/series/47286/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4551_full -> Patchwork_9781_full = == Summary - WARNING ==

[Intel-gfx] ✓ Fi.CI.BAT: success for Decode memdev info and bandwidth and implemnt latency WA (rev2)

== Series Details == Series: Decode memdev info and bandwidth and implemnt latency WA (rev2) URL : https://patchwork.freedesktop.org/series/46481/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4551 -> Patchwork_9782 = == Summary - SUCCESS == No regressions found. Exte

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Decode memdev info and bandwidth and implemnt latency WA (rev2)

== Series Details == Series: Decode memdev info and bandwidth and implemnt latency WA (rev2) URL : https://patchwork.freedesktop.org/series/46481/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/bxt: Decode memory bandwidth and parameters -drivers/gpu/drm/i915/selfte

[Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

Memory with 16GB dimms require an increase of 1us in level-0 latency. This patch implements the same. Bspec: 4381 changes since V1: - s/memdev_info/dram_info - make skl_is_16gb_dimm pure function Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.c | 40

[Intel-gfx] [PATCH 4/5] drm/i915/kbl+: Enable IPC only for symmetric memory configurations

IPC may cause underflows if not used with dual channel symmetric memory configuration. Disable IPC for non symmetric configurations in affected platforms. Display WA #1141 Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.c | 43 - drivers/gpu/

[Intel-gfx] [PATCH 5/5] drm/i915/skl+: don't trust IPC value set by BIOS

If KMS decide to disable IPC make sure we override IPC configuration set by BIOS. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 39e400d

[Intel-gfx] [PATCH 1/5] drm/i915/bxt: Decode memory bandwidth and parameters

This patch adds support to decode system memory bandwidth and other parameters for broxton platform, which will be used for arbitrated display memory bandwidth calculation in GEN9 based platforms and WM latency level-0 Work-around calculation on GEN9+ platforms. Changes since V1: - s/memdev_info/

[Intel-gfx] [PATCH 0/5] Decode memdev info and bandwidth and implemnt latency WA

This series adds support to calculate system memdev parameters and calculate total system memory bandwidth. This parameters and BW will be used to enable WM level-0 latency workaround and display memory bandwidth related WA for gen9. while we are here to enable IPC based on memory configuration le

[Intel-gfx] [PATCH 2/5] drm/i915/skl+: Decode memory bandwidth and parameters

This patch adds support to decode system memory bandwidth and other parameters for skylake and Gen9+ platforms, which will be used for arbitrated display memory bandwidth calculation in GEN9 based platforms and WM latency level-0 Work-around calculation on GEN9+. Changes Since V1: - s/memdev_info

[Intel-gfx] ✓ Fi.CI.BAT: success for Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit.

== Series Details == Series: Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit. URL : https://patchwork.freedesktop.org/series/47286/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4551 -> Patchwork_9781 = == Summary - SUCCESS == No regr

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit.

== Series Details == Series: Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit. URL : https://patchwork.freedesktop.org/series/47286/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: Added max_bpp property to limit maximum bpp even if HDMI TV

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit.

== Series Details == Series: Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit. URL : https://patchwork.freedesktop.org/series/47286/ State : warning == Summary == $ dim checkpatch origin/drm-tip e194ce13c27e Added max_bpp property to limit maximum bpp even i

[Intel-gfx] [PATCH v1] Added max_bpp property to limit maximum bpp even if HDMI TV advertises higher limit.

From: Stanislav Lisovskiy This was inspired, by a bugs like this: Bugzilla: https://bugs.freedesktop.org/93361 In short, when TV advertises 12bpc, the refresh rate might get inaccurate causing some playback issues. The temporary solution was to hack the EDID, so that it doesn't advertise deep

Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise resetting in the middle of a wait-on-fence

Quoting Matthew Auld (2018-07-26 13:26:08) > On 19 July 2018 at 20:47, Chris Wilson wrote: > > On older HW, gen2/3, fence registers are used for detiling GPU commands > > and as such changing those registers requires serialisation with the > > requests on the GPU. Anything running on the GPU is su

Re: [Intel-gfx] [PATCH] drm/i915: Allow control of PSR at runtime through debugfs.

Op 26-07-18 om 08:32 schreef Dhinakaran Pandiyan: > On Thu, 2018-03-22 at 10:41 +0100, Maarten Lankhorst wrote: >> Op 22-03-18 om 02:45 schreef Pandiyan, Dhinakaran: >>> On Thu, 2018-03-15 at 11:28 +0100, Maarten Lankhorst wrote: Currently tests modify i915.enable_psr and then do a modeset >>>

Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise resetting in the middle of a wait-on-fence

On 19 July 2018 at 20:47, Chris Wilson wrote: > On older HW, gen2/3, fence registers are used for detiling GPU commands > and as such changing those registers requires serialisation with the > requests on the GPU. Anything running on the GPU is subject to a hang, > and so we must be able to recove

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Protect guc_fini_wq() against module load abort

Quoting Michał Winiarski (2018-07-26 12:44:08) > On Thu, Jul 26, 2018 at 09:50:31AM +0100, Chris Wilson wrote: > > Prevent > > [ 397.873143] general protection fault: [#1] PREEMPT SMP PTI > > [ 397.873154] CPU: 4 PID: 4799 Comm: drv_module_relo Tainted: G U > > 4.18.0-rc6-CI-

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Control PSR at runtime through debugfs only (rev4)

== Series Details == Series: drm/i915: Control PSR at runtime through debugfs only (rev4) URL : https://patchwork.freedesktop.org/series/39955/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4548_full -> Patchwork_9778_full = == Summary - WARNING == Minor unknown changes

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Protect guc_fini_wq() against module load abort

On Thu, Jul 26, 2018 at 09:50:31AM +0100, Chris Wilson wrote: > Prevent > [ 397.873143] general protection fault: [#1] PREEMPT SMP PTI > [ 397.873154] CPU: 4 PID: 4799 Comm: drv_module_relo Tainted: G U > 4.18.0-rc6-CI-CI_DRM_4534+ #1 > [ 397.873162] Hardware name: Micro-Sta

Re: [Intel-gfx] [PATCH] drm/i915: Avoid computing tile_row_size() for untiled objects

Quoting Matthew Auld (2018-07-26 12:22:52) > On 26 July 2018 at 11:47, Chris Wilson wrote: > > i915_gem_tile_height() asserts that the object is tiled, but inside the > > error printer for the selftest we computed the row size regardless of > > tiling, tripping over the assert. > > > > Signed-off-

Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Use a full emulation of a user ppgtt context

On 19 July 2018 at 20:47, Chris Wilson wrote: > To test eviction from a ppgtt, we just want a ppgtt i.e. something other > than the Global GTT which is shared and used by the kernel for HW > features like fencing and scanout. However, we also need it to pass > !i915_is_ggtt() and the simplest way

Re: [Intel-gfx] [PATCH] drm/i915: Avoid computing tile_row_size() for untiled objects

On 26 July 2018 at 11:47, Chris Wilson wrote: > i915_gem_tile_height() asserts that the object is tiled, but inside the > error printer for the selftest we computed the row size regardless of > tiling, tripping over the assert. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld __

Re: [Intel-gfx] [PATCH] drm/i915: Mark up object tiling-and-stride getters as const

On 25 July 2018 at 16:54, Chris Wilson wrote: > For that little bit of defense against a tired programmer. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.or

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Avoid computing tile_row_size() for untiled objects

== Series Details == Series: drm/i915: Avoid computing tile_row_size() for untiled objects URL : https://patchwork.freedesktop.org/series/47279/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4548 -> Patchwork_9780 = == Summary - FAILURE == Serious unknown changes coming

[Intel-gfx] [PATCH] drm/i915: Avoid computing tile_row_size() for untiled objects

i915_gem_tile_height() asserts that the object is tiled, but inside the error printer for the selftest we computed the row size regardless of tiling, tripping over the assert. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/i915_gem_object.c | 2 +- 1 file changed, 1 insertion(+),

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Protect guc_fini_wq() against module load abort

== Series Details == Series: series starting with [1/3] drm/i915: Protect guc_fini_wq() against module load abort URL : https://patchwork.freedesktop.org/series/47272/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4548_full -> Patchwork_9777_full = == Summary - WARNING ==

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Control PSR at runtime through debugfs only (rev4)

== Series Details == Series: drm/i915: Control PSR at runtime through debugfs only (rev4) URL : https://patchwork.freedesktop.org/series/39955/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4548 -> Patchwork_9778 = == Summary - SUCCESS == No regressions found. Externa

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Control PSR at runtime through debugfs only (rev4)

== Series Details == Series: drm/i915: Control PSR at runtime through debugfs only (rev4) URL : https://patchwork.freedesktop.org/series/39955/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Allow control of PSR at runtime through debugfs, v3. -drivers/gpu/drm/i915

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Control PSR at runtime through debugfs only (rev4)

== Series Details == Series: drm/i915: Control PSR at runtime through debugfs only (rev4) URL : https://patchwork.freedesktop.org/series/39955/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7f03d7801144 drm/i915: Allow control of PSR at runtime through debugfs, v3. -:76: WARNIN

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Protect guc_fini_wq() against module load abort

== Series Details == Series: series starting with [1/3] drm/i915: Protect guc_fini_wq() against module load abort URL : https://patchwork.freedesktop.org/series/47272/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4548 -> Patchwork_9777 = == Summary - WARNING == Minor u

[Intel-gfx] [PATCH] drm/i915: Allow control of PSR at runtime through debugfs, v3.

Currently tests modify i915.enable_psr and then do a modeset cycle to change PSR. We can write a value to i915_edp_psr_status to force a certain value without a modeset. To retain compatibility with older userspace, we also still allow the override through the module parameter, and add some tracki

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Restore sane defaults for KMS on GEM error load (rev2)

== Series Details == Series: drm/i915: Restore sane defaults for KMS on GEM error load (rev2) URL : https://patchwork.freedesktop.org/series/47266/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4548 -> Patchwork_9776 = == Summary - FAILURE == Serious unknown changes comi

[Intel-gfx] [PATCH 3/3] drm/i915: Don't disable the GPU for older gen on wedging

If we issue a device level GPU reset on the older gen, it will disable key components of the GMCH and the display engine. The purpose of wedging is to simply prevent further GEM usage without disabling KMS, so we need to be careful when we do issue the reset on wedging. Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 1/3] drm/i915: Protect guc_fini_wq() against module load abort

Prevent [ 397.873143] general protection fault: [#1] PREEMPT SMP PTI [ 397.873154] CPU: 4 PID: 4799 Comm: drv_module_relo Tainted: G U 4.18.0-rc6-CI-CI_DRM_4534+ #1 [ 397.873162] Hardware name: Micro-Star International Co., Ltd. MS-7B54/Z370M MORTAR (MS-7B54), BIOS 1.10 12/

[Intel-gfx] [PATCH 2/3] drm/i915: Restore sane defaults for KMS on GEM error load

If we fail during GEM initialisation, we scrub the HW state by performing a device level GPU resuet. However, we want to leave the system in a usable state (with functioning KMS but no GEM) so after scrubbing the HW state, we need to restore some sane defaults and re-enable the low-level common par

[Intel-gfx] [PATCH] drm/i915: Restore sane defaults for KMS on GEM error load

If we fail during GEM initialisation, we scrub the HW state by performing a device level GPU resuet. However, we want to leave the system in a usable state (with functioning KMS but no GEM) so after scrubbing the HW state, we need to restore some sane defaults and re-enable the low-level common par

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/mst: Continue state updates even if AUX writes fail.

On Wed, 2018-07-25 at 11:39 -0700, Dhinakaran Pandiyan wrote: > On Thu, 2018-07-19 at 16:37 -0700, Rodrigo Vivi wrote: > > > > On Thu, Jul 19, 2018 at 11:51:40AM -0700, Dhinakaran Pandiyan > > wrote: > > > > > > > > > On Wed, 2018-07-18 at 22:43 -0700, Rodrigo Vivi wrote: > > > > > > > > > > >

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Restore sane defaults for KMS on GEM error load

== Series Details == Series: drm/i915: Restore sane defaults for KMS on GEM error load URL : https://patchwork.freedesktop.org/series/47266/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4547 -> Patchwork_9775 = == Summary - FAILURE == Serious unknown changes coming with