[Intel-gfx] [PATCH] drm/i915: Restore sane defaults for KMS on GEM error load

If we fail during GEM initialisation, we scrub the HW state by performing a device level GPU resuet. However, we want to leave the system in a usable state (with functioning KMS but no GEM) so after scrubbing the HW state, we need to restore some sane defaults and re-enable the low-level common par

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Limit psr2 to skl+

== Series Details == Series: drm/i915/psr: Limit psr2 to skl+ URL : https://patchwork.freedesktop.org/series/47263/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4547 -> Patchwork_9774 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9774 absolutel

Re: [Intel-gfx] [PATCH] drm/i915/psr: Limit psr2 to skl+

On Thu, 2018-07-26 at 11:32 +0530, vathsala nagaraju wrote: > From: Vathsala Nagaraju > > PSR2 is supported from skl+. > So Limiting it to skl+. We restrict PSR2 to gen9+ in intel_psr_init_dpcd(), avoids a few extra dpcd reads by checking early. > > Cc: Dhinakaran Pandiyan > Signed-off-by: V

Re: [Intel-gfx] [PATCH] drm/i915: Allow control of PSR at runtime through debugfs.

On Thu, 2018-03-22 at 10:41 +0100, Maarten Lankhorst wrote: > Op 22-03-18 om 02:45 schreef Pandiyan, Dhinakaran: > > > > On Thu, 2018-03-15 at 11:28 +0100, Maarten Lankhorst wrote: > > > > > > Currently tests modify i915.enable_psr and then do a modeset > > > cycle > > > to change PSR. We can wri

Re: [Intel-gfx] [PATCH] drm/i915: inline skl_copy_ddb_for_pipe() to its only caller

Hi, Patch LGTM. Reviewed-by: Mahesh Kumar thanks, -Mahesh On 6/8/2018 4:37 AM, Paulo Zanoni wrote: While things may have been different before, right now the function is very simple and has a single caller. IMHO any possible benefits from an abstraction here are gone and not worth the price

[Intel-gfx] [PATCH] drm/i915/psr: Limit psr2 to skl+

From: Vathsala Nagaraju PSR2 is supported from skl+. So Limiting it to skl+. Cc: Dhinakaran Pandiyan Signed-off-by: Vathsala Nagaraju --- drivers/gpu/drm/i915/intel_psr.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Print PSR_STATUS when PSR idle wait times out.

== Series Details == Series: drm/i915/psr: Print PSR_STATUS when PSR idle wait times out. URL : https://patchwork.freedesktop.org/series/47262/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4547 -> Patchwork_9773 = == Summary - FAILURE == Serious unknown changes coming w

[Intel-gfx] linux-next: manual merge of the mfd tree with the drm-intel tree

Hi Lee, Today's linux-next merge of the mfd tree got a conflict in: drivers/gpu/drm/i915/intel_display.h between commit: 6075546f57f8 ("drm/i915/icl: store the port type for TC ports") from the drm-intel tree and commit: 9c229127aee2 ("drm/i915: hdmi: add CEC notifier to intel_hdmi") f

[Intel-gfx] [PATCH] drm/i915/psr: Print PSR_STATUS when PSR idle wait times out.

Knowing the status of the PSR HW state machine is useful for debug, especially since we are seeing errors with PSR2 in CI. Cc: Rodrigo Vivi Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_drv.h| 3 ++- drivers/gpu/drm/i915/intel_psr.c| 9 ++--- drivers/gpu/drm/i915

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/mst: Do not retrain new links

== Series Details == Series: series starting with [v2,1/2] drm/i915/mst: Do not retrain new links URL : https://patchwork.freedesktop.org/series/46797/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4547 -> Patchwork_9772 = == Summary - FAILURE == Serious unknown changes

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/mst: Do not retrain new links

On Wed, 2018-07-25 at 20:28 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v2,1/2] drm/i915/mst: Do not retrain > new links > URL   : https://patchwork.freedesktop.org/series/46797/ > State : failure > > == Summary == > > = CI Bug Log - changes from CI_DRM_4541_

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: don't set CNL_DDI_CLOCk_REG_ACCESS_ON anymore

== Series Details == Series: drm/i915/icl: don't set CNL_DDI_CLOCk_REG_ACCESS_ON anymore URL : https://patchwork.freedesktop.org/series/47259/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4547 -> Patchwork_9771 = == Summary - FAILURE == Serious unknown changes coming wi

[Intel-gfx] [PATCH] drm/i915/icl: don't set CNL_DDI_CLOCk_REG_ACCESS_ON anymore

The new recommendation from the spec is to simply not set this bit anymore. Not setting the bit would prevent some hangs that our driver manages to avoid since commit c8af5274c3cb ("drm/i915: enable the pipe/transcoder/planes later on HSW+"), and the theoretical downside of not setting the bit does

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations

== Series Details == Series: series starting with [1/2] drm/i915/icl: Add TBT checks for PLL calculations URL : https://patchwork.freedesktop.org/series/47248/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4547 -> Patchwork_9770 = == Summary - FAILURE == Serious unknown

Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction

Em Qua, 2018-07-25 às 14:28 -0700, Anusha Srivatsa escreveu: > For a TBT sequence, we need to set the IO type to TBT > in DDI_AUX_CTL. > > Cc: Paulo Zanoni > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_dp.c | 34 ++

Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations

Em Qua, 2018-07-25 às 14:28 -0700, Anusha Srivatsa escreveu: > Add missing TBT check in the Pll calculation. > > v2: do not use a auxiliary function to check if status is > TBT or not. (Paulo) > > Cc: Paulo Zanoni > Cc: Lucas De Marchi > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/

Re: [Intel-gfx] sad output names

On Wed, Jul 25, 2018 at 02:21:24PM -0400, Felix Miata wrote: > Rodrigo Vivi composed on 2018-07-25 09:20 (UTC-0700): > > > On Wed, Jul 25, 2018 at 03:37:52AM -0400, Felix Miata wrote: > > >> Asus B250 LGA 1151 (Kaby Lake) Motherboard (4 total physical video > >> outputs): > >> https://www.asus.c

[Intel-gfx] [PATCH i-g-t] igt: Another combinatorial exercise for blits

The aim of this test is to combine gem_linear_blits, gem_tiled_blits etc into one test runner that covers investigation into HW alignment issues as well as driver boundaries (relocs, access, thrashing). Signed-off-by: Chris Wilson Cc: Katarzyna Dec --- tests/Makefile.sources | 1 + tests/gem_

Re: [Intel-gfx] sad output names

On Wed, 2018-07-25 at 14:21 -0400, Felix Miata wrote: > Rodrigo Vivi composed on 2018-07-25 09:20 (UTC-0700): > > > > > On Wed, Jul 25, 2018 at 03:37:52AM -0400, Felix Miata wrote: > > > > > > > > Asus B250 LGA 1151 (Kaby Lake) Motherboard (4 total physical > > > video outputs): > > > https://w

[Intel-gfx] [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction

For a TBT sequence, we need to set the IO type to TBT in DDI_AUX_CTL. Cc: Paulo Zanoni Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_dp.c | 34 +- 2 files changed, 26 insertions(+), 9 deletions(-) diff --g

[Intel-gfx] [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations

Add missing TBT check in the Pll calculation. v2: do not use a auxiliary function to check if status is TBT or not. (Paulo) Cc: Paulo Zanoni Cc: Lucas De Marchi Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-)

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: implement icl_digital_port_connected() (rev3)

== Series Details == Series: drm/i915/icl: implement icl_digital_port_connected() (rev3) URL : https://patchwork.freedesktop.org/series/47151/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4542 -> Patchwork_9769 = == Summary - FAILURE == Serious unknown changes coming wi

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Use correct error code for GuC initialization failure

Quoting Patchwork (2018-07-25 21:19:41) > == Series Details == That wasn't a particularly successful rebase: <7>[2.811183] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/kbl_guc_ver9_39.bin <7>[2.811208] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING <7>[2.812408] [drm:guc_fw_

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/2] drm/i915/mst: Do not retrain new links

== Series Details == Series: series starting with [v2,1/2] drm/i915/mst: Do not retrain new links URL : https://patchwork.freedesktop.org/series/46797/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4541_full -> Patchwork_9767_full = == Summary - FAILURE == Serious unknow

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/icl: implement icl_digital_port_connected() (rev3)

== Series Details == Series: drm/i915/icl: implement icl_digital_port_connected() (rev3) URL : https://patchwork.freedesktop.org/series/47151/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/icl: implement icl_digital_port_connected() Okay! Commit: drm/i915/icl: sto

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: implement icl_digital_port_connected() (rev3)

== Series Details == Series: drm/i915/icl: implement icl_digital_port_connected() (rev3) URL : https://patchwork.freedesktop.org/series/47151/ State : warning == Summary == $ dim checkpatch origin/drm-tip 82dbbab3500e drm/i915/icl: implement icl_digital_port_connected() -:7: WARNING:COMMIT_LOG

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Use correct error code for GuC initialization failure

== Series Details == Series: drm/i915/guc: Use correct error code for GuC initialization failure URL : https://patchwork.freedesktop.org/series/47241/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4542 -> Patchwork_9768 = == Summary - FAILURE == Serious unknown changes c

Re: [Intel-gfx] sad output names

Em Qua, 2018-07-25 às 09:20 -0700, Rodrigo Vivi escreveu: > On Wed, Jul 25, 2018 at 03:37:52AM -0400, Felix Miata wrote: > > Asus B250 LGA 1151 (Kaby Lake) Motherboard (4 total physical video > > outputs): > > https://www.asus.com/us/Motherboards/PRIME-B250M-C-CSM/ > > > > G4600 HD Graphics 630 CP

Re: [Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

On Wed, Jul 25, 2018 at 10:59:32AM -0700, Paulo Zanoni wrote: > Em Qua, 2018-07-25 às 10:27 -0700, Paulo Zanoni escreveu: > > Em Ter, 2018-07-24 às 18:19 -0700, Lucas De Marchi escreveu: > > > On Tue, Jul 24, 2018 at 05:28:09PM -0700, Paulo Zanoni wrote: > > > > Do like the other functions and chec

[Intel-gfx] [PATCH v4 1/5] drm/i915/icl: implement icl_digital_port_connected()

Do like the other functions and check for the status bits. The "Hot Plug Detection" page from our documentation says we can't just use the ISR bits on the CPU side (North Display, which has the TC and TBT modes), so use the correct register: DFLEXDPSP, TC Live State field. v2: Rebase. v3: - Simp

[Intel-gfx] [PATCH] drm/i915/guc: Use correct error code for GuC initialization failure

From: Michal Wajdeczko Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure") we believed that we correctly handle all errors encountered during GuC initialization, including special one that indicates request to run driver with disabled GPU submission (-EIO). Unfortunately since

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/mst: Do not retrain new links

== Series Details == Series: series starting with [v2,1/2] drm/i915/mst: Do not retrain new links URL : https://patchwork.freedesktop.org/series/46797/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4541 -> Patchwork_9767 = == Summary - SUCCESS == No regressions found.

Re: [Intel-gfx] sad output names

Rodrigo Vivi composed on 2018-07-25 09:20 (UTC-0700): > On Wed, Jul 25, 2018 at 03:37:52AM -0400, Felix Miata wrote: >> Asus B250 LGA 1151 (Kaby Lake) Motherboard (4 total physical video outputs): >> https://www.asus.com/us/Motherboards/PRIME-B250M-C-CSM/ >> G4600 HD Graphics 630 CPU >> Server

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/mst: Continue state updates even if AUX writes fail.

On Thu, 2018-07-19 at 16:37 -0700, Rodrigo Vivi wrote: > On Thu, Jul 19, 2018 at 11:51:40AM -0700, Dhinakaran Pandiyan wrote: > > > > On Wed, 2018-07-18 at 22:43 -0700, Rodrigo Vivi wrote: > > > > > > On Wed, Jul 18, 2018 at 10:19:43AM -0700, Dhinakaran Pandiyan > > > wrote: > > > > > > > > > >

Re: [Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

Em Qua, 2018-07-25 às 10:27 -0700, Paulo Zanoni escreveu: > Em Ter, 2018-07-24 às 18:19 -0700, Lucas De Marchi escreveu: > > On Tue, Jul 24, 2018 at 05:28:09PM -0700, Paulo Zanoni wrote: > > > Do like the other functions and check for the status bits. The > > > "Hot > > > Plug Detection" page from

Re: [Intel-gfx] [PATCH v5 4/5] drm/i915: Add a fault injection point to WOPCM init

On Wed, 25 Jul 2018 12:56:55 +0200, Jakub Bartmiński wrote: Missing commit message ... at minimum just repeat commit title v4: Move the injection inside the WOPCM init. Signed-off-by: Jakub Bartmiński Cc: Chris Wilson Cc: Michał Winiarski Cc: Michal Wajdeczko --- drivers/gpu/drm/i915/i

Re: [Intel-gfx] [PATCH v5 3/5] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context

On Wed, 25 Jul 2018 12:56:54 +0200, Jakub Bartmiński wrote: Since ggtt_offset_bias is now stored in ggtt.pin_bias, it is duplicated inside i915_gem_context, and can instead be accessed directly from ggtt. I'm tempted to merge this patch with previous one (without renames) v3: Added a hel

Re: [Intel-gfx] [PATCH v5 2/5] drm/i915/guc: Move the pin bias value from GuC to GGTT

On Wed, 25 Jul 2018 12:56:53 +0200, Jakub Bartmiński wrote: Removing the pin bias from GuC allows us to not check for GuC every time we pin a context, which fixes the assertion error on unresolved GuC platform default in mock contexts selftest. It also seems that we were using uninitialized

Re: [Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

Em Ter, 2018-07-24 às 18:19 -0700, Lucas De Marchi escreveu: > On Tue, Jul 24, 2018 at 05:28:09PM -0700, Paulo Zanoni wrote: > > Do like the other functions and check for the status bits. The "Hot > > Plug Detection" page from our documentation says we can't just use > > the > > ISR bits on the CPU

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Mark up object tiling-and-stride getters as const

== Series Details == Series: drm/i915: Mark up object tiling-and-stride getters as const URL : https://patchwork.freedesktop.org/series/47230/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4540_full -> Patchwork_9765_full = == Summary - SUCCESS == No regressions found.

Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Update FIA supported lane count for hpd.

On Wed, Jul 25, 2018 at 09:52:25AM -0700, Rodrigo Vivi wrote: > On Tue, Jul 24, 2018 at 05:28:11PM -0700, Paulo Zanoni wrote: > > From: Animesh Manna > > > > In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1, > > tbt and display controller. In DP alt mode FIA configure the > > nu

Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Update FIA supported lane count for hpd.

Em Qua, 2018-07-25 às 09:52 -0700, Rodrigo Vivi escreveu: > On Tue, Jul 24, 2018 at 05:28:11PM -0700, Paulo Zanoni wrote: > > From: Animesh Manna > > > > In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1, > > tbt and display controller. In DP alt mode FIA configure the > > number

Re: [Intel-gfx] [PATCH 2/5] drm/i915/icl: store the port type for TC ports

On Wed, Jul 25, 2018 at 09:41:18AM -0700, Rodrigo Vivi wrote: > On Tue, Jul 24, 2018 at 05:28:10PM -0700, Paulo Zanoni wrote: > > The type is detected based on the live status bits. Once detected, > > it's not supposed to be changed, so we have some sanity checks for > > that. > > > > v2: Rebase.

Re: [Intel-gfx] [PATCH] drm/i915/dp: Improve clock recovery loop limit comment

On Tue, Jul 24, 2018 at 05:17:53PM -0700, Marc Herbert wrote: > Reviewed-by: Marc Herbert pushed, thanks. > > Thx Nathan, I think this helps. I'm still curious how training normally > converges much faster than the total number of possibilities but - unlike > this latest clarification below - I

Re: [Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

Em Ter, 2018-07-24 às 18:19 -0700, Lucas De Marchi escreveu: > On Tue, Jul 24, 2018 at 05:28:09PM -0700, Paulo Zanoni wrote: > > Do like the other functions and check for the status bits. The "Hot > > Plug Detection" page from our documentation says we can't just use > > the > > ISR bits on the CPU

Re: [Intel-gfx] [PATCH] drm/i915/psr: Enable PSR1 by default on gen9+ platforms

On Wed, Jul 25, 2018 at 09:52:44AM -0700, Dhinakaran Pandiyan wrote: > On Wed, 2018-07-25 at 09:12 -0700, Rodrigo Vivi wrote: > > On Wed, Jul 25, 2018 at 12:22:28AM -0700, Dhinakaran Pandiyan wrote: > > > > > > We have merged several fixes, re-written some tests and improved > > > debug > > > capa

Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Update FIA supported lane count for hpd.

On Tue, Jul 24, 2018 at 05:28:11PM -0700, Paulo Zanoni wrote: > From: Animesh Manna > > In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1, > tbt and display controller. In DP alt mode FIA configure the > number of lanes and will be used apart from DPCD read to calculate max > ava

Re: [Intel-gfx] [PATCH 2/5] drm/i915/icl: store the port type for TC ports

On Tue, Jul 24, 2018 at 05:28:10PM -0700, Paulo Zanoni wrote: > The type is detected based on the live status bits. Once detected, > it's not supposed to be changed, so we have some sanity checks for > that. > > v2: Rebase. > > Cc: Animesh Manna > Signed-off-by: Rodrigo Vivi > Signed-off-by: Pa

Re: [Intel-gfx] [PATCH] drm/i915/psr: Enable PSR1 by default on gen9+ platforms

On Wed, 2018-07-25 at 09:12 -0700, Rodrigo Vivi wrote: > On Wed, Jul 25, 2018 at 12:22:28AM -0700, Dhinakaran Pandiyan wrote: > > > > We have merged several fixes, re-written some tests and improved > > debug > > capability in the past several months, so this is a good time to > > give PSR1 > > an

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Mark up object tiling-and-stride getters as const

== Series Details == Series: drm/i915: Mark up object tiling-and-stride getters as const URL : https://patchwork.freedesktop.org/series/47230/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4540 -> Patchwork_9765 = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Protect guc_fini_wq() against module load abort (rev3)

== Series Details == Series: drm/i915: Protect guc_fini_wq() against module load abort (rev3) URL : https://patchwork.freedesktop.org/series/47127/ State : failure == Summary == Applying: drm/i915: Protect guc_fini_wq() against module load abort error: corrupt patch at line 8 error: could not

Re: [Intel-gfx] sad output names

On Wed, Jul 25, 2018 at 03:37:52AM -0400, Felix Miata wrote: > Asus B250 LGA 1151 (Kaby Lake) Motherboard (4 total physical video outputs): > https://www.asus.com/us/Motherboards/PRIME-B250M-C-CSM/ > > G4600 HD Graphics 630 CPU > > Server 1.20.0 (openSUSE Tumbleweed) > > kernel 4.17.4 > > Xorg

Re: [Intel-gfx] [PATCH v2] drm/i915: Protect guc_fini_wq() against module load abort

On Tue, 24 Jul 2018 16:19:36 +0200, Chris Wilson wrote: Prevent [ 397.873143] general protection fault: [#1] PREEMPT SMP PTI [ 397.873154] CPU: 4 PID: 4799 Comm: drv_module_relo Tainted: G U4.18.0-rc6-CI-CI_DRM_4534+ #1 [ 397.873162] Hardware name: Micro-Star Interna

Re: [Intel-gfx] [PATCH] drm/i915/psr: Enable PSR1 by default on gen9+ platforms

On Wed, Jul 25, 2018 at 12:22:28AM -0700, Dhinakaran Pandiyan wrote: > We have merged several fixes, re-written some tests and improved debug > capability in the past several months, so this is a good time to give PSR1 > another try. PSR1 has not been tested on HSW and BDW recently, so let's > enab

[Intel-gfx] [PATCH] drm/i915: Mark up object tiling-and-stride getters as const

For that little bit of defense against a tired programmer. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c| 4 ++-- drivers/gpu/drm/i915/i915_gem_object.h | 10 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/dr

[Intel-gfx] ✗ Fi.CI.BAT: failure for mm, oom: distinguish blockable mode for mmu notifiers (rev9)

== Series Details == Series: mm, oom: distinguish blockable mode for mmu notifiers (rev9) URL : https://patchwork.freedesktop.org/series/45263/ State : failure == Summary == Applying: mm, oom: distinguish blockable mode for mmu notifiers error: sha1 information is lacking or useless (mm/oom_ki

Re: [Intel-gfx] [PATCH] mm, oom: distinguish blockable mode for mmu notifiers

On Tue, 24 Jul 2018, Michal Hocko wrote: > oom_reap_task_mm should return false when __oom_reap_task_mm return > false. This is what my patch did but it seems this changed by > http://www.ozlabs.org/~akpm/mmotm/broken-out/mm-oom-remove-oom_lock-from-oom_reaper.patch > so that one should be fixed.

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: implement icl_digital_port_connected() (rev2)

== Series Details == Series: drm/i915/icl: implement icl_digital_port_connected() (rev2) URL : https://patchwork.freedesktop.org/series/47151/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4539_full -> Patchwork_9762_full = == Summary - WARNING == Minor unknown changes c

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

== Series Details == Series: series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias URL : https://patchwork.freedesktop.org/series/47201/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4539 -> Patchwork_9763 = == Summary - FAILURE == S

[Intel-gfx] sad output names

Asus B250 LGA 1151 (Kaby Lake) Motherboard (4 total physical video outputs): https://www.asus.com/us/Motherboards/PRIME-B250M-C-CSM/ G4600 HD Graphics 630 CPU Server 1.20.0 (openSUSE Tumbleweed) kernel 4.17.4 Xorg driver: modesetting Xrandr Actual Cable Reports Connectors DP-1

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

== Series Details == Series: series starting with [v5,1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias URL : https://patchwork.freedesktop.org/series/47201/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/guc: Avoid wasting memory on incorrect GuC p

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: implement icl_digital_port_connected() (rev2)

== Series Details == Series: drm/i915/icl: implement icl_digital_port_connected() (rev2) URL : https://patchwork.freedesktop.org/series/47151/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4539 -> Patchwork_9762 = == Summary - SUCCESS == No regressions found. External

[Intel-gfx] [PATCH v5 3/5] drm/i915: Remove unnecessary ggtt_offset_bias from i915_gem_context

Since ggtt_offset_bias is now stored in ggtt.pin_bias, it is duplicated inside i915_gem_context, and can instead be accessed directly from ggtt. v3: Added a helper function to retrieve the ggtt.pin_bias from the vma. v4: Moved the helper function to the previous patch in the series. Dropped the b

[Intel-gfx] [PATCH v5 5/5] HAX enable GuC for CI

From: Michal Wajdeczko Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index aebe0469ddaa..3e4e128237ac 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH v5 4/5] drm/i915: Add a fault injection point to WOPCM init

v4: Move the injection inside the WOPCM init. Signed-off-by: Jakub Bartmiński Cc: Chris Wilson Cc: Michał Winiarski Cc: Michal Wajdeczko --- drivers/gpu/drm/i915/intel_wopcm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/int

[Intel-gfx] [PATCH v5 1/5] drm/i915/guc: Avoid wasting memory on incorrect GuC pin bias

It would appear that the calculated GuC pin bias was larger than it should be, as the GuC address space does NOT contain the "HW contexts RSVD" part of the WOPCM. Thus, the GuC pin bias is simply the GuC WOPCM size. v5: Clarify the diagram to better represent the GuC address space. Since we now do

[Intel-gfx] [PATCH v5 2/5] drm/i915/guc: Move the pin bias value from GuC to GGTT

Removing the pin bias from GuC allows us to not check for GuC every time we pin a context, which fixes the assertion error on unresolved GuC platform default in mock contexts selftest. It also seems that we were using uninitialized WOPCM variables when setting the GuC pin bias. The pin bias has to

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Enable PSR1 by default on gen9+ platforms

== Series Details == Series: drm/i915/psr: Enable PSR1 by default on gen9+ platforms URL : https://patchwork.freedesktop.org/series/47188/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4538_full -> Patchwork_9761_full = == Summary - WARNING == Minor unknown changes comin

Re: [Intel-gfx] [PATCH i-g-t 4/4] igt/gem_exec_capture: Capture many, many objects

On Mon, Jul 23, 2018 at 09:07:36PM +0100, Chris Wilson wrote: > Exercise O(N^2) behaviour in reading the error state, and push it to the > extreme. > > Reported-by: Jason Ekstrand > Signed-off-by: Chris Wilson LGTM, Reviewed-by: Katarzyna Dec Kasia :) __

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Enable PSR1 by default on gen9+ platforms

== Series Details == Series: drm/i915/psr: Enable PSR1 by default on gen9+ platforms URL : https://patchwork.freedesktop.org/series/47188/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4538 -> Patchwork_9761 = == Summary - SUCCESS == No regressions found. External URL

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/4] igt/gem_tiled_fence_blits: Remove libdrm_intel dependence

On Mon, Jul 23, 2018 at 09:07:34PM +0100, Chris Wilson wrote: > Modernise the test to use igt's ioctl library as opposed to the > antiquated libdrm_intel. > > Signed-off-by: Chris Wilson LGTM, Reviewed-by: Katarzyna Dec Kasia :) ___ Intel-gfx mailing

Re: [Intel-gfx] sad output names

Felix Miata composed on 2018-07-25 03:37 (UTC-0400): > Asus B250 LGA 1151 (Kaby Lake) Motherboard (4 total physical video outputs): > https://www.asus.com/us/Motherboards/PRIME-B250M-C-CSM/ > G4600 HD Graphics 630 CPU > Server 1.20.0 (openSUSE Tumbleweed) > kernel 4.17.4 > Xorg driver: modeset

[Intel-gfx] [PATCH] drm/i915/psr: Enable PSR1 by default on gen9+ platforms

We have merged several fixes, re-written some tests and improved debug capability in the past several months, so this is a good time to give PSR1 another try. PSR1 has not been tested on HSW and BDW recently, so let's enable only on gen9+ now. Cc: Rodigo Vivi Cc: José Roberto de Souza Signed-off

Re: [Intel-gfx] [PATCH] drm/i915: Skip repeated calls to i915_gem_set_wedged()

Quoting Rodrigo Vivi (2018-07-23 23:23:32) > On Mon, Jul 23, 2018 at 03:53:35PM +0100, Chris Wilson wrote: > > If we already wedged, i915_gem_set_wedged() becomes a complicated no-op. > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=107343 > > Signed-off-by: Chris Wilson > > Revi