Quoting Matthew Auld (2018-06-14 22:32:09)
> On 14 June 2018 at 20:24, Chris Wilson wrote:
> > From: Jon Bloomfield
> >
> > Hook up the flags to allow read-only ppGTT mappings for gen8+
> >
> > v2: Include a selftest to check that writes to a readonly PTE are
> > dropped
> >
> > Signed-off-by: Jo
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/psr: Remove intel_crtc_state
parameter from disable()
URL : https://patchwork.freedesktop.org/series/44780/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4321_full -> Patchwork_9311_full =
== Summary - SUC
On Thu, Jun 14, 2018 at 05:45:03PM -0700, Manasi Navare wrote:
> On Thu, Jun 14, 2018 at 12:24:32PM -0700, Rodrigo Vivi wrote:
> > On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> > > Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > > > On Thu, May 24, 2018 at 04:42:37PM
On Thu, Jun 14, 2018 at 05:11:53PM -0700, Souza, Jose wrote:
> On Thu, 2018-06-14 at 16:59 -0700, Rodrigo Vivi wrote:
> > On Thu, Jun 14, 2018 at 04:46:48PM -0700, Souza, Jose wrote:
> > > On Thu, 2018-06-14 at 14:09 -0700, Rodrigo Vivi wrote:
> > > > On Thu, Jun 14, 2018 at 01:34:30PM -0700, José
On Thu, Jun 14, 2018 at 05:02:41PM -0700, Souza, Jose wrote:
> On Thu, 2018-06-14 at 14:19 -0700, Rodrigo Vivi wrote:
> > On Thu, Jun 14, 2018 at 01:34:33PM -0700, José Roberto de Souza
> > wrote:
> > > Sink can be configured to calculate the CRC over the static frame
> > > and
> > > compare with t
== Series Details ==
Series: series starting with [1/2] drm/i915/gtt: Enable full-ppgtt by default
everywhere
URL : https://patchwork.freedesktop.org/series/44778/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4321_full -> Patchwork_9310_full =
== Summary - WARNING ==
M
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode
URL : https://patchwork.freedesktop.org/series/44776/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4320_full -> Patchwork_9308_full =
== Summary - FAILURE ==
Se
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gtt: Cache the PTE encoding of
the scratch page
URL : https://patchwork.freedesktop.org/series/44773/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4320_full -> Patchwork_9307_full =
== Summary - WARNING =
== Series Details ==
Series: drm/i915: s/IS_G4X && !IS_GM45/IS_G45/
URL : https://patchwork.freedesktop.org/series/44772/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4319_full -> Patchwork_9306_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_
== Series Details ==
Series: series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x
(rev2)
URL : https://patchwork.freedesktop.org/series/44589/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4318_full -> Patchwork_9305_full =
== Summary - WARNING ==
Mino
On Thu, Jun 14, 2018 at 12:24:32PM -0700, Rodrigo Vivi wrote:
> On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> > Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > > From: Manasi Navare
> > > >
> > >
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/whl: Introducing Whiskey Lake
platform
URL : https://patchwork.freedesktop.org/series/44787/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4322 -> Patchwork_9315 =
== Summary - WARNING ==
Minor unknown
On Thu, 2018-06-14 at 16:59 -0700, Rodrigo Vivi wrote:
> On Thu, Jun 14, 2018 at 04:46:48PM -0700, Souza, Jose wrote:
> > On Thu, 2018-06-14 at 14:09 -0700, Rodrigo Vivi wrote:
> > > On Thu, Jun 14, 2018 at 01:34:30PM -0700, José Roberto de Souza
> > > wrote:
> > > > eDP spec states that sink devic
On Thu, 2018-06-14 at 14:19 -0700, Rodrigo Vivi wrote:
> On Thu, Jun 14, 2018 at 01:34:33PM -0700, José Roberto de Souza
> wrote:
> > Sink can be configured to calculate the CRC over the static frame
> > and
> > compare with the CRC calculated and transmited in the VSC SDP by
> > source, if there i
On Thu, Jun 14, 2018 at 04:37:19PM -0700, José Roberto de Souza wrote:
> Whiskey Lake uses the same gen graphics as Coffe Lake, including some
> ids that were previously marked as reserved on Coffe Lake, but that
> now are moved to WHL page.
>
> So, let's just move them to WHL macros that will fee
On Thu, Jun 14, 2018 at 04:46:48PM -0700, Souza, Jose wrote:
> On Thu, 2018-06-14 at 14:09 -0700, Rodrigo Vivi wrote:
> > On Thu, Jun 14, 2018 at 01:34:30PM -0700, José Roberto de Souza
> > wrote:
> > > eDP spec states that sink device will do a short pulse in HPD
> > > line when there is a PSR/PSR
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/whl: Introducing Whiskey Lake
platform
URL : https://patchwork.freedesktop.org/series/44787/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7cf5c8bc3840 drm/i915/whl: Introducing Whiskey Lake platform
-:76: ERR
On Thu, 2018-06-14 at 14:09 -0700, Rodrigo Vivi wrote:
> On Thu, Jun 14, 2018 at 01:34:30PM -0700, José Roberto de Souza
> wrote:
> > eDP spec states that sink device will do a short pulse in HPD
> > line when there is a PSR/PSR2 error that needs to be handled by
> > source, this is handling the fi
Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.
So, let's just move them to WHL macros that will feed into CFL macro
just to keep it better organized to make easier future code revi
Amber Lake uses the same gen graphics as Kaby Lake, including a id
that were previously marked as reserved on Kaby Lake, but that
now is moved to AML page.
So, let's just move it to AML macro that will feed into KBL macro
just to keep it better organized to make easier future code review
but it wi
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/icl: implement DVFS for ICL
URL : https://patchwork.freedesktop.org/series/44784/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4322 -> Patchwork_9314 =
== Summary - WARNING ==
Minor unknown changes comi
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/icl: implement DVFS for ICL
URL : https://patchwork.freedesktop.org/series/44784/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: implement DVFS for ICL
+drivers/gpu/drm/i915/intel_cdclk.c:2519:
== Series Details ==
Series: series starting with [1/2] drm/i915/whl: Introducing Whiskey Lake
platform
URL : https://patchwork.freedesktop.org/series/44782/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4322 -> Patchwork_9313 =
== Summary - SUCCESS ==
No regressions fo
On Thu, Jun 14, 2018 at 03:08:31PM -0700, José Roberto de Souza wrote:
> Whiskey Lake uses the same gen graphics as Coffe Lake, including some
> ids that were previously marked as reserved on Coffe Lake, but that
> now are moved to WHL page.
>
> So, let's just move them to WHL macros that will fee
On Thu, Jun 14, 2018 at 03:08:32PM -0700, José Roberto de Souza wrote:
> Amber Lake uses the same gen graphics as Kaby Lake, including a id
> that were previously marked as reserved on Kaby Lake, but that
> now is moved to AML page.
>
> So, let's just move it to AML macro that will feed into KBL m
== Series Details ==
Series: series starting with [1/2] drm/i915/whl: Introducing Whiskey Lake
platform
URL : https://patchwork.freedesktop.org/series/44782/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eca7a90b2b57 drm/i915/whl: Introducing Whiskey Lake platform
-:65: ERROR:
== Series Details ==
Series: drm/i915: Enable provoking vertex fix on Gen9+ systems.
URL : https://patchwork.freedesktop.org/series/44781/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4322 -> Patchwork_9312 =
== Summary - FAILURE ==
Serious unknown changes coming with P
>-Original Message-
>From: Mateo Lozano, Oscar
>Sent: Wednesday, June 13, 2018 3:08 PM
>To: Wajdeczko, Michal ; intel-
>g...@lists.freedesktop.org
>Cc: Joonas Lahtinen ; Rogovin, Kevin
>; Spotswood, John A ;
>Srivatsa, Anusha ; Ceraolo Spurio, Daniele
>; Thierry, Michel ;
>Chris Wilson ;
== Series Details ==
Series: drm/i915: Enable provoking vertex fix on Gen9+ systems.
URL : https://patchwork.freedesktop.org/series/44781/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1fee0a9a8734 drm/i915: Enable provoking vertex fix on Gen9+ systems.
-:74: ERROR:MISSING_SIGN
Amber Lake uses the same gen graphics as Kaby Lake, including a id
that were previously marked as reserved on Kaby Lake, but that
now is moved to AML page.
So, let's just move it to AML macro that will feed into KBL macro
just to keep it better organized to make easier future code review
but it wi
ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK
table. Implement it just like CNL does.
References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage
on CNL")
References: commit 53e9bf5e8159 ("drm/i915: Adjust system agent
voltage on CNL if required by DDI ports")
Cc: Vill
Some bits from the flags2 field are going to be used in the next
patches, so replace the whole-byte definition with the actual bits and
document their versions.
This patch is based on a patch by Animesh Manna.
Cc: Animesh Manna
Credits-to: Animesh Manna
Reviewed-by: Rodrigo Vivi
Signed-off-by:
Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.
So, let's just move them to WHL macros that will feed into CFL macro
just to keep it better organized to make easier future code revi
The SF and clipper units mishandle the provoking vertex in some cases,
which can cause misrendering with shaders that use flat shaded inputs.
There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN
(for the clipper) that work around the issue. These registers are
unfortunately not par
On Thu, Jun 14, 2018 at 02:50:38PM -0700, Dhinakaran Pandiyan wrote:
> On Thu, 2018-06-14 at 14:13 -0700, Rodrigo Vivi wrote:
> > On Thu, Jun 14, 2018 at 01:34:32PM -0700, José Roberto de Souza
> > wrote:
> > >
> > > Specification requires that max time should be masked from bdw and
> > > forward
On Thu, 2018-06-14 at 14:50 -0700, Dhinakaran Pandiyan wrote:
> On Thu, 2018-06-14 at 14:13 -0700, Rodrigo Vivi wrote:
> >
> > On Thu, Jun 14, 2018 at 01:34:32PM -0700, José Roberto de Souza
> > wrote:
> > >
> > >
> > > Specification requires that max time should be masked from bdw
> > > and
> >
On Thu, 2018-06-14 at 14:09 -0700, Rodrigo Vivi wrote:
> On Thu, Jun 14, 2018 at 01:34:30PM -0700, José Roberto de Souza
> wrote:
> >
> > eDP spec states that sink device will do a short pulse in HPD
> > line when there is a PSR/PSR2 error that needs to be handled by
> > source, this is handling t
On 14 June 2018 at 20:24, Chris Wilson wrote:
> From: Jon Bloomfield
>
> Hook up the flags to allow read-only ppGTT mappings for gen8+
>
> v2: Include a selftest to check that writes to a readonly PTE are
> dropped
>
> Signed-off-by: Jon Bloomfield
> Signed-off-by: Chris Wilson
> Cc: Joonas Lah
On Thu, 2018-06-14 at 14:19 -0700, Rodrigo Vivi wrote:
> On Thu, Jun 14, 2018 at 01:34:33PM -0700, José Roberto de Souza
> wrote:
> >
> > Sink can be configured to calculate the CRC over the static frame
> > and
> > compare with the CRC calculated and transmited in the VSC SDP by
> > source, if th
On Thu, 2018-06-14 at 14:13 -0700, Rodrigo Vivi wrote:
> On Thu, Jun 14, 2018 at 01:34:32PM -0700, José Roberto de Souza
> wrote:
> >
> > Specification requires that max time should be masked from bdw and
> > forward but it can be also safely enabled to hsw.
> > This will make PSR exits more deter
On Thu, Jun 14, 2018 at 01:34:33PM -0700, José Roberto de Souza wrote:
> Sink can be configured to calculate the CRC over the static frame and
> compare with the CRC calculated and transmited in the VSC SDP by
> source, if there is a mismatch sink will do a short pulse in HPD
> and set DP_PSR_LINK_
Hi Ville,
Looks like we have right fix from audio and we will not need powerwell 2
reset workaround when changing cdclk.
we need only one patch in this series to get merged.
drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled.
Regards,
Abhay
On 6/13/2018 11:41 AM, Abhay
On Thu, Jun 14, 2018 at 01:34:32PM -0700, José Roberto de Souza wrote:
> Specification requires that max time should be masked from bdw and
> forward but it can be also safely enabled to hsw.
> This will make PSR exits more deterministic and only when really
> needed. If this was used to fix a issu
On Thu, Jun 14, 2018 at 01:34:30PM -0700, José Roberto de Souza wrote:
> eDP spec states that sink device will do a short pulse in HPD
> line when there is a PSR/PSR2 error that needs to be handled by
> source, this is handling the first and most simples error:
> DP_PSR_SINK_INTERNAL_ERROR.
>
> He
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/psr: Remove intel_crtc_state
parameter from disable()
URL : https://patchwork.freedesktop.org/series/44780/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4321 -> Patchwork_9311 =
== Summary - SUCCESS ==
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/psr: Remove intel_crtc_state
parameter from disable()
URL : https://patchwork.freedesktop.org/series/44780/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/psr: Remove intel_crtc_state parameter fro
Em Qui, 2018-06-14 às 12:07 -0700, Rodrigo Vivi escreveu:
> On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> > From: Mahesh Kumar
> >
> > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins
> > 9/10/11/12
> > mapped to tc ports[1-4].
> > This patch defines GPIOCTL registers
== Series Details ==
Series: series starting with [v4,1/5] drm/i915/psr: Remove intel_crtc_state
parameter from disable()
URL : https://patchwork.freedesktop.org/series/44780/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2068bdba7b19 drm/i915/psr: Remove intel_crtc_state para
== Series Details ==
Series: series starting with [1/2] drm/i915/gtt: Enable full-ppgtt by default
everywhere
URL : https://patchwork.freedesktop.org/series/44778/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4321 -> Patchwork_9310 =
== Summary - SUCCESS ==
No regressi
Sink will interrupt source when it have any problem saving or reading
the remote frame buffer.
v3:
disabling PSR instead of exiting on error
Cc: Rodrigo Vivi
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 14 ++
1 file
Specification requires that max time should be masked from bdw and
forward but it can be also safely enabled to hsw.
This will make PSR exits more deterministic and only when really
needed. If this was used to fix a issue in some panel than can
only self-refresh for a few seconds, that panel will i
Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR in DP_PSR_ERROR_STATUS.
Spec: 7723
v4:
patch moved to after 'drm/i9
It was only used in VLV/CHV so after the removal of the PSR support
for those platforms it is not necessary any more.
Reviewed-by: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
drivers/gpu/drm/i915/intel_psr.c | 5 ++---
eDP spec states that sink device will do a short pulse in HPD
line when there is a PSR/PSR2 error that needs to be handled by
source, this is handling the first and most simples error:
DP_PSR_SINK_INTERNAL_ERROR.
Here taking the safest approach and disabling PSR(at least until
the next modeset), t
== Series Details ==
Series: series starting with [1/2] drm/i915/gtt: Enable full-ppgtt by default
everywhere
URL : https://patchwork.freedesktop.org/series/44778/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e6d49115297f drm/i915/gtt: Enable full-ppgtt by default everywhere
== Series Details ==
Series: More ICL display patches (rev13)
URL : https://patchwork.freedesktop.org/series/43546/
State : failure
== Summary ==
Applying: drm/i915/icl: Extend AUX F interrupts to ICL
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_irq.c
Fallin
We believe we have all the kinks worked out, even for the early
Valleyview devices, for whom we currently disable all ppgtt.
References: 62942ed7279d ("drm/i915/vlv: disable PPGTT on early revs v3")
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915
We should we have all the kinks worked out and full-ppgtt now works
reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can
let userspace have full control over their own ppgtt, it makes softpinning
far more effective, in turn making GPU dispatch far more efficient and
more secure
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode
URL : https://patchwork.freedesktop.org/series/44776/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4320 -> Patchwork_9308 =
== Summary - WARNING ==
Minor unknow
On Mon, May 21, 2018 at 05:25:53PM -0700, Paulo Zanoni wrote:
> The type is detected based on the interrupt ISR bit. Once detected,
> it's not supposed to be changed, so we have some sanity checks for
> that.
>
> Cc: Animesh Manna
> Signed-off-by: Paulo Zanoni
> Signed-off-by: Rodrigo Vivi
> --
On Thu, 2018-06-14 at 13:32 +0300, Ville Syrjälä wrote:
> On Wed, Jun 13, 2018 at 06:51:37PM -0700, Dhinakaran Pandiyan wrote:
> >
> > On Fri, 2018-05-25 at 20:56 +0100, Chris Wilson wrote:
> > >
> > > Quoting Dhinakaran Pandiyan (2018-05-25 20:43:13)
> > > >
> > > >
> > > > The Graphics System
The Graphics System Event(GSE) interrupt bit has a new location in the
GU_MISC_INTERRUPT_{IIR, ISR, IMR, IER} registers. Since GSE was the only
DE_MISC interrupt that was enabled, with this change we don't enable/handle
any of DE_MISC interrupts for gen11. Credits to Paulo for pointing out
the regi
On Thu, May 24, 2018 at 04:42:39PM -0700, Paulo Zanoni wrote:
> ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK
> table. Implement it just like CNL does.
>
> References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage
> on CNL")
> References: commit 53e9bf5e8159 ("drm/i91
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode
URL : https://patchwork.freedesktop.org/series/44776/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/gtt: Add read only pages to gen8_pte_encode
Okay!
Comm
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode
URL : https://patchwork.freedesktop.org/series/44776/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a55b1e45685a drm/i915/gtt: Add read only pages to gen8_pte_encode
6a
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gtt: Cache the PTE encoding of
the scratch page
URL : https://patchwork.freedesktop.org/series/44773/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4320 -> Patchwork_9307 =
== Summary - WARNING ==
Minor
On Thu, May 24, 2018 at 04:42:41PM -0700, Paulo Zanoni wrote:
> Some bits from the flags2 field are going to be used in the next
> patches, so replace the whole-byte definition with the actual bits and
> document their versions.
>
> This patch is based on a patch by Animesh Manna.
>
> Cc: Animesh
On Thu, May 24, 2018 at 05:36:37PM -0700, Lucas De Marchi wrote:
> On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> > From: Mahesh Kumar
> >
> > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> > mapped to tc ports[1-4].
> > This patch defines GPIOCTL registe
If the user has created a read-only object, they should not be allowed
to circumvent the write protection by using a GGTT mmapping. Deny it.
Also most machines do not support read-only GGTT PTEs, so again we have
to reject attempted writes. Fortunately, this is known a priori, so we
can at least r
From: Jon Bloomfield
Hook up the flags to allow read-only ppGTT mappings for gen8+
v2: Include a selftest to check that writes to a readonly PTE are
dropped
Signed-off-by: Jon Bloomfield
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen #v1
Revie
On gen8 and onwards, we can mark GPU accesses through the ppGTT as being
read-only, that is cause any GPU write onto that page to be discarded
(not triggering a fault). This is all that we need to finally support
the read-only flag for userptr!
Testcase: igt/gem_userptr_blits/readonly*
Signed-off-
On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > From: Manasi Navare
> > >
> > > For ICL, on Combo PHY the allowed max rates are:
> > > - HBR3 8.1 eDP
If the user created a read-only object, they should not be allowed to
circumvent the write protection using the pwrite ioctl.
Signed-off-by: Chris Wilson
Cc: Jon Bloomfield
Cc: Joonas Lahtinen
Cc: Matthew Auld
Reviewed-by: Jon Bloomfield
Reviewed-by: Joonas Lahtinen
Reviewed-by: Matthew Auld
From: Jon Bloomfield
We can set a bit inside the ppGTT PTE to indicate a page is read-only;
writes from the GPU will be discarded. We can use this to protect pages
and in particular support read-only userptr mappings (necessary for
importing PROT_READ vma).
Signed-off-by: Jon Bloomfield
Signed-
On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare
>
> For ICL, on Combo PHY the allowed max rates are:
> - HBR3 8.1 eDP (DDIA)
> - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
> - HBR3 8.1 DisplayPort (DP alternate mode, DP o
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gtt: Cache the PTE encoding of
the scratch page
URL : https://patchwork.freedesktop.org/series/44773/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ce53d8e68c84 drm/i915/gtt: Cache the PTE encoding of the scra
On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
> mapped to tc ports[1-4].
> This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
> pin mapping table.
>
Fixes:?
>
== Series Details ==
Series: drm/i915: s/IS_G4X && !IS_GM45/IS_G45/
URL : https://patchwork.freedesktop.org/series/44772/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4319 -> Patchwork_9306 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchw
On Wed, Jun 13, 2018 at 09:55:38AM +0300, Jani Nikula wrote:
> On Tue, 12 Jun 2018, Lucas De Marchi wrote:
> > On Tue, Jun 12, 2018 at 3:15 AM Jani Nikula wrote:
> >>
> >> On Tue, 12 Jun 2018, Tvrtko Ursulin wrote:
> >> > On 12/06/2018 10:19, Jani Nikula wrote:
> >> >> Semi-RFC. Do we want to do
We can stop asserting using WARN_ON as given sufficient CI coverage, we
can rely on using GEM_BUG_ON() to catch problems before merging.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
As the most frequent PTE encoding is for the scratch page, cache it upon
creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Matthew Auld
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++--
drivers/gpu/drm/i915/i915_gem_gtt
Quoting Mika Kuoppala (2018-06-14 16:06:39)
> Chris Wilson writes:
>
> > Hangcheck is our back up in case the GPU or the driver gets stuck. It
> > detects when the GPU is not making any progress and issues a GPU reset.
> > However, if the driver is failing to make any progress, we can get
> > our
Quoting Mika Kuoppala (2018-06-14 16:48:48)
> Chris Wilson writes:
>
> > In the unlikely case where we have failed to keep submitting to the GPU,
> > we end up with the ELSP queue empty but a pending queue of requests.
> > Here, we skip the per-engine reset as there is no guilty request, but in
>
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gtt: Lazily allocate page
directories for gen7
URL : https://patchwork.freedesktop.org/series/44757/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4315_full -> Patchwork_9303_full =
== Summary - WARNING ==
== Series Details ==
Series: series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x
(rev2)
URL : https://patchwork.freedesktop.org/series/44589/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4318 -> Patchwork_9305 =
== Summary - SUCCESS ==
No regressions
On Mon, Jun 11, 2018 at 09:53:52PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-06-11 21:02:55)
> > From: Ville Syrjälä
> >
> > On i965/g4x IIR is edge triggered. So in order for IIR to notice that
> > there is still a pending interrupt we have to force and edge in ISR.
> > For the IS
On Thu, Jun 14, 2018 at 03:42:42PM +0300, Jani Nikula wrote:
> On Wed, 13 Jun 2018, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > While Bspec doesn't list a specific sequence for turning off the DP port
> > on g4x we are getting an underrun if the port is disabled in the
> > .disable() hoo
Quoting Ville Syrjala (2018-06-14 19:05:00)
> From: Ville Syrjälä
>
> We have IS_G45 these days. Let's use it instead of the
> 'IS_G4X && !IS_GM45' construct.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> driver
From: Ville Syrjälä
We have IS_G45 these days. Let's use it instead of the
'IS_G4X && !IS_GM45' construct.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_crt.c | 2 +-
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
3 files changed, 3 insertion
From: Ville Syrjälä
Just like with PIPESTAT, the edge triggered IIR on i965/g4x
also causes problems for hotplug interrupts. To make sure
we don't get the IIR port interrupt bit stuck low with the
ISR bit high we must force an edge in ISR. Unfortunately
we can't borrow the PIPESTAT trick and togg
On Wed, Jun 13, 2018 at 10:03:02PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/icl: Fix HDMI infoframe setting (rev2)
> URL : https://patchwork.freedesktop.org/series/44709/
> State : success
Pushed to -dinq with the missing conversion you noticed in patch 1 done
while a
On Tue, Jun 12, 2018 at 04:56:54PM -0700, Paulo Zanoni wrote:
> While I don't see any issue with the way these macros are being called
> today, let's protect them against operator precedence issues before
> they happen.
>
> Signed-off-by: Paulo Zanoni
Reviewed-by: Rodrigo Vivi
> ---
> drivers
On Tue, Jun 12, 2018 at 04:56:53PM -0700, Paulo Zanoni wrote:
> Since I'm touching the file I might as well fix this class of errors
> since they are just a few. Also drive-by fix the styling of the
> VLV_TURBO_SOC_OVERRIDE definitions instead of just the spaces before
> the tabs.
>
> Signed-off-b
On Thu, 2018-06-14 at 16:56 +, Nagaraju, Vathsala wrote:
> + Ashutosh(VBT team) + maulik
>
> 209 is confirmed version on kbl both by vbt team (Maulik) and google,
> so we had used it.
>
> DK's suggestion is
> if ((bdb->version >= 203 && IS_GEN9_BC(dev_priv)) ||
> IS_GEMINILAKE(dev_priv) ||
== Series Details ==
Series: drm/i915/selftests: Initialise request to silence a compiler
URL : https://patchwork.freedesktop.org/series/44752/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4314_full -> Patchwork_9301_full =
== Summary - WARNING ==
Minor unknown changes
+ Ashutosh(VBT team) + maulik
209 is confirmed version on kbl both by vbt team (Maulik) and google, so we had
used it.
DK's suggestion is
if ((bdb->version >= 203 && IS_GEN9_BC(dev_priv)) ||
IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
/* new mapping */
As per Ashutosh, 203 Is no
> -Original Message-
> From: Chris Wilson
> Sent: Thursday, June 14, 2018 5:00 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson ; Bloomfield, Jon
> ; Joonas Lahtinen
> ; Matthew Auld
>
> Subject: [PATCH 4/5] drm/i915: Reject attempted pwrites into a read-only
> object
>
> If t
> -Original Message-
> From: Chris Wilson
> Sent: Thursday, June 14, 2018 5:00 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson ; Bloomfield, Jon
> ; Joonas Lahtinen
>
> Subject: [PATCH 5/5] drm/i915/userptr: Enable read-only support on gen8+
>
> On gen8 and onwards, we can ma
On Thu, Jun 14, 2018 at 09:00:15AM -0700, Pandiyan, Dhinakaran wrote:
> On Thu, 2018-06-14 at 11:59 +0530, Nagaraju, Vathsala wrote:
> >
> > On 6/13/2018 11:10 PM, Dhinakaran Pandiyan wrote:
> > >
> > > On Wed, 2018-06-13 at 10:32 -0700, Dhinakaran Pandiyan wrote:
> > > >
> > > > On Wed, 2018-06
Quoting Bloomfield, Jon (2018-06-14 17:36:29)
> > -Original Message-
> > From: Chris Wilson
> > Sent: Thursday, June 14, 2018 9:07 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-de...@lists.freedesktop.org; Chris Wilson
> > ;
> > Bloomfield, Jon ; Joonas Lahtinen
> > ; Matthew Aul
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