== Series Details ==
Series: drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits
(rev2)
URL : https://patchwork.freedesktop.org/series/43420/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209_full -> Patchwork_9057_full =
== Summary - WARNING ==
Minor
== Series Details ==
Series: drm/i915: Promote .format_mod_supported() to the lead role (rev2)
URL : https://patchwork.freedesktop.org/series/40207/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209_full -> Patchwork_9056_full =
== Summary - WARNING ==
Minor unknown cha
== Series Details ==
Series: drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset
URL : https://patchwork.freedesktop.org/series/43404/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209_full -> Patchwork_9055_full =
== Summary - WARNING ==
Minor unknown c
On 5/18/2018 3:39 PM, Yunwei Zhang wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value wil
On 5/18/2018 3:41 PM, Yunwei Zhang wrote:
L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a
== Series Details ==
Series: series starting with [1/7] drm/i915: Move
intel_ddi_get_crtc_new_encoder() out from ddi code
URL : https://patchwork.freedesktop.org/series/43426/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209_full -> Patchwork_9054_full =
== Summary - WAR
On 5/18/2018 3:40 PM, Yunwei Zhang wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.
References: HSD#1405586840, BSID#0575
v2:
- GEN11 mask is different from its predecessors. (Oscar)
- Better separate GEN10 and GEN11. (Oscar)
Cc: Oscar Mateo
Cc: Michel T
== Series Details ==
Series: series starting with [v4,1/3] drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev9)
URL : https://patchwork.freedesktop.org/series/43159/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9061 =
== Summary -
== Series Details ==
Series: series starting with [v4,1/3] drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev9)
URL : https://patchwork.freedesktop.org/series/43159/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/cnl: Implement WaProgramMgsr
L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 inst
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.
References: HSD#1405586840, BSID#0575
v2:
- GEN11 mask is different from its predecessors. (Oscar)
- Better separate GEN10 and GEN11. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
C
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subse
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev6)
URL : https://patchwork.freedesktop.org/series/43159/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9060 =
== Summary -
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Use intel_fb_obj() everywhere
URL : https://patchwork.freedesktop.org/series/43421/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209_full -> Patchwork_9053_full =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev6)
URL : https://patchwork.freedesktop.org/series/43159/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/cnl: Implement WaProgramMgsr
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.
References: HSD#1405586840, BSID#0575
v2:
- GEN11 mask is different from its predecessors. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subse
On 5/17/2018 3:59 PM, Paulo Zanoni wrote:
Em Qui, 2018-05-17 às 10:04 -0700, Oscar Mateo Lozano escreveu:
On 5/17/2018 9:55 AM, Michel Thierry wrote:
On 5/16/2018 4:39 PM, Paulo Zanoni wrote:
Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:
Stop reading some now deprecated interrupt
On 5/18/2018 11:12 AM, Yunwei Zhang wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value wi
On 5/18/2018 11:13 AM, Yunwei Zhang wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.
References: HSD#1405586840, BSID#0575
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei
Quoting Tvrtko Ursulin (2018-05-17 14:13:00)
>
> On 17/05/2018 08:40, Chris Wilson wrote:
> > Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
> > bottom half"), we came to the conclusion that running our CSB processing
> > and ELSP submission from inside the irq handler was
== Series Details ==
Series: drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits
URL : https://patchwork.freedesktop.org/series/43420/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4208_full -> Patchwork_9052_full =
== Summary - WARNING ==
Minor unknown
On 11/05/18 08:45, Tomasz Lis wrote:
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result from
Context Status Buffer.
Preemption in previous gens required a special batch buffer to be executed,
so the Com
== Series Details ==
Series: drm/i915/icl: Disable pipe CSC and gamma in cursor plane
URL : https://patchwork.freedesktop.org/series/43443/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9059 =
== Summary - SUCCESS ==
No regressions found.
External UR
== Series Details ==
Series: drm/i915/icl: Disable pipe CSC and gamma in cursor plane
URL : https://patchwork.freedesktop.org/series/43443/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9052b8404e85 drm/i915/icl: Disable pipe CSC and gamma in cursor plane
-:10: ERROR:GIT_COMMIT
'Pipe CSC enable' bit is more than just deprecated in ICL+, it was
disabled in 077ef1f09c25 'drm/i915/icl: Don't set pipe CSC/Gamma in
PLANE_COLOR_CTL' for primary and sprite planes as it was causing
those planes to be rendered as always black but it was not disabled
in cursor plane, also causing i
On Thursday, May 17, 2018 12:44:30 PM PDT Dhinakaran Pandiyan wrote:
> On Thu, 2018-05-17 at 10:33 +0300, Jani Nikula wrote:
> > On Thu, 17 May 2018, Jani Nikula wrote:
> > > On Wed, 16 May 2018, Dhinakaran Pandiyan > >
> > > .com> wrote:
> > > > On Wed, 2018-05-16 at 11:01 +0300, Jani Nikula wr
Quoting Tvrtko Ursulin (2018-05-18 09:06:03)
>
> On 17/05/2018 18:07, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-05-17 14:13:00)
> >>
> >> On 17/05/2018 08:40, Chris Wilson wrote:
> >>> Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
> >>> bottom half"), we came t
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Use intel_fb_obj() everywhere
URL : https://patchwork.freedesktop.org/series/43418/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4206_full -> Patchwork_9051_full =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev4)
URL : https://patchwork.freedesktop.org/series/43159/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9058 =
== Summary -
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads (rev4)
URL : https://patchwork.freedesktop.org/series/43159/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/cnl: Implement WaProgramMgsr
L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
programed to point to a disabled bank pair, a MMIO read into L3Bank range
will return 0 inst
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.
References: HSD#1405586840, BSID#0575
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei Zhang
---
drivers/gpu/drm/i915/intel_engine_c
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subse
== Series Details ==
Series: drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits
(rev2)
URL : https://patchwork.freedesktop.org/series/43420/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9057 =
== Summary - SUCCESS ==
No regressions
On Thu, May 10, 2018 at 05:54:19PM -0700, Dhinakaran Pandiyan wrote:
> Entry corresponding to 220 us setup time was missing. I am not aware of
> any specific bug this fixes, but this could potentially result in enabling
> PSR on a panel with a higher setup time requirement than supported by the
> h
Quoting Lionel Landwerlin (2018-05-18 18:14:52)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 196a0eb79272..86ab1303724a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2531,6 +2531,9 @@ enum i915_power_well_id
On Gen8+ this register is not priviledged and we want to use it in
Mesa to implement a feature required by GPA called Null Hardware. The
idea is to have the command parser turn 3DPRIMITIVE/GPGPU_WALKER into
NOOPs.
This patch just whitelists the bits that we need and that are
currently not used by
On Fri, May 18, 2018 at 7:15 AM Ville Syrjälä
wrote:
> On Fri, May 18, 2018 at 03:25:26PM +0300, Ville Syrjälä wrote:
> > On Thu, May 17, 2018 at 12:07:14PM -0700, Fritz Koenig wrote:
> > > Planes with an odd width will appear to have an incorrect
> > > stride. When the start position is odd the
== Series Details ==
Series: Revert "drm/i915/edp: Do not do link training fallback or prune modes
on EDP" (rev2)
URL : https://patchwork.freedesktop.org/series/43278/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4206_full -> Patchwork_9049_full =
== Summary - WARNING ==
== Series Details ==
Series: drm/i915: Promote .format_mod_supported() to the lead role (rev2)
URL : https://patchwork.freedesktop.org/series/40207/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9056 =
== Summary - SUCCESS ==
No regressions found.
Ex
Quoting Matthew Auld (2018-05-18 17:42:27)
> On 17 May 2018 at 07:03, Chris Wilson wrote:
> > static int
> > i915_gem_wait_for_error(struct i915_gpu_error *error)
> > {
> > @@ -2422,6 +2403,8 @@ __i915_gem_object_unset_pages(struct
> > drm_i915_gem_object *obj)
> >
> > spin_lock(&i915-
On Thu, May 17, 2018 at 12:28 AM, Jani Nikula
wrote:
> On Wed, 16 May 2018, Manasi Navare wrote:
>> This patch fixes the original commit c0cfb10d9e1de49 ("drm/i915/edp:
>> Do not do link training fallback or prune modes on EDP") that causes
>> a blank screen in case of certain eDP panels (Eg: see
On 17 May 2018 at 07:03, Chris Wilson wrote:
> Currently, we try to report to the shrinker the precise number of
> objects (pages) that are available to be reaped at this moment. This
> requires searching all objects with allocated pages to see if they
> fulfill the search criteria, and this count
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
On Friday 18 May 2018 06:03 PM, Shankar, Uma wrote:
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Ramalingam C
Sent: Tuesday, April 3, 2018 7:28 PM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
seanp...@chromiu
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
== Series Details ==
Series: drm/i915: Promote .format_mod_supported() to the lead role (rev2)
URL : https://patchwork.freedesktop.org/series/40207/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
42558aaba961 drm/i915: Promote .format_mod_supported() to the lead role
-:22: WARNI
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
== Series Details ==
Series: drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset
URL : https://patchwork.freedesktop.org/series/43404/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9055 =
== Summary - WARNING ==
Minor unknown changes com
Quoting Tvrtko Ursulin (2018-05-18 17:12:25)
> From: Tvrtko Ursulin
>
> Trivial "set but unused" cleanup.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.free
From: Ville Syrjälä
Up to now we've used the plane's modifier list as the primary
source of information for which modifiers are supported by a
given plane. In order to allow auxiliary metadata to be embedded
within the bits of the modifier we need to stop doing that.
Thus we have to make .format
Hi Neil,
2018-05-18 15:05 GMT+02:00 Neil Armstrong :
> The EC can expose a CEC bus, this patch adds the CEC related definitions
> needed by the cros-ec-cec driver.
> Having a 16 byte mkbp event size makes it possible to send CEC
> messages from the EC to the AP directly inside the mkbp event
> ins
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
== Series Details ==
Series: drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset
URL : https://patchwork.freedesktop.org/series/43404/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
100fe331b0d3 drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset
From: Tvrtko Ursulin
Trivial "set but unused" cleanup.
Signed-off-by: Tvrtko Ursulin
---
overlay/x11/x11-overlay.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/overlay/x11/x11-overlay.c b/overlay/x11/x11-overlay.c
index ae6494295c5a..ac6b5f39a696 100644
--- a/overl
== Series Details ==
Series: series starting with [1/7] drm/i915: Move
intel_ddi_get_crtc_new_encoder() out from ddi code
URL : https://patchwork.freedesktop.org/series/43426/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9054 =
== Summary - WARNING ==
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:28 PM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Use intel_fb_obj() everywhere
URL : https://patchwork.freedesktop.org/series/43421/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4209 -> Patchwork_9053 =
== Summary - SUCCESS ==
No regressions found.
On Fri, May 18, 2018 at 03:05:00PM +0200, Neil Armstrong wrote:
> In non device-tree world, we can need to get the notifier by the driver
> name directly and eventually defer probe if not yet created.
>
> This patch adds a variant of the get function by using the device name
> instead and will not
On 18/05/18 15:40, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-05-18 15:29:21)
On 18/05/18 15:26, Lionel Landwerlin wrote:
On Gen8+ this register is not priviledged and we want to use it in
Mesa to implement a feature required by GPA called Null Hardware. The
idea is to have the command
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Use intel_fb_obj() everywhere
URL : https://patchwork.freedesktop.org/series/43421/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Use intel_fb_obj() everywhere
-O:drivers/gpu/drm/i915/intel_displ
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Use intel_fb_obj() everywhere
URL : https://patchwork.freedesktop.org/series/43421/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0fde58b9b092 drm/i915: Use intel_fb_obj() everywhere
ea66e36be55d drm/i915: Mov
From: Ville Syrjälä
Clean up the DP pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state(),
the port state asserts, and the VLV power sequencer code.
v2: Return PIPE_A for cpt/ppt when the port isn't selected by
any transcoder
From: Ville Syrjälä
The power sequencer has bits to allow DP C to be used for eDP.
Currently we assume this will never happen, but I guess it could
theoretically be a thing. Make the code do the right thing in that
case, and toss in a MISSING_CASE() for any other port.
Signed-off-by: Ville Syrjä
From: Ville Syrjälä
We don't support using the power sequencer with other ports besides LVDS
on pre-ilk platforms. WARN if someone has mistakenly connected the power
sequencer to the wrong port.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 5 +
1 file changed, 5
From: Ville Syrjälä
Parametrize the TRANS_DP_PORT_SEL macros.
v2: WARN for bogus ports (Jani)
Order the defines mask,value (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++-
drivers/gpu/drm/i915/intel_display.c | 24 ++
From: Ville Syrjälä
Add the missing eDP port handling into assert_panel_unlocked(). We now
have intel_dp_port_enabled() which makes this trivial.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
dif
From: Ville Syrjälä
for_each_encoder_on_crtc() is legacy and shouldn't be used by atomic
drivers. Let's throw out intel_trans_dp_port_sel() and replace it
with intel_get_crtc_new_encoder() which looks the atomic state instead.
Since we now have to call intel_get_crtc_new_encoder() during the com
From: Ville Syrjälä
The ddi code no longer uses intel_ddi_get_crtc_new_encoder(). Move it
elsewhere where we have some users left.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 29 -
drivers/gpu/drm/i915/intel_disp
== Series Details ==
Series: drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits
URL : https://patchwork.freedesktop.org/series/43420/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4208 -> Patchwork_9052 =
== Summary - WARNING ==
Minor unknown changes c
On 2018.05.18 12:03:02 +0100, Chris Wilson wrote:
> Quoting Patchwork (2018-05-18 11:55:01)
> > == Series Details ==
> >
> > Series: drm/i915/gvt: Fix crash after request->hw_context change
> > URL : https://patchwork.freedesktop.org/series/43406/
> > State : failure
> >
> > == Summary ==
> >
Hi Neil,
2018-05-18 15:05 GMT+02:00 Neil Armstrong :
> The Chrome OS Embedded Controller can expose a CEC bus, this patch add the
A minor nit, there is a "consensus" on tell cros-ec as "ChromeOS
Embedded Controller" or "ChromeOS EC". Yes, I know that you can see in
the kernel many other ways to r
From: Ville Syrjälä
VBT seems to have some bits to tell us whether the internal LVDS port
has something hooked up. In theory one might expect the VBT to not have
a child device for the LVDS port if there's no panel hooked up, but
in practice many VBTs still add the child device. The "LVDS config"
== Series Details ==
Series: drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits
URL : https://patchwork.freedesktop.org/series/43420/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2fac9bc00108 drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable
== Series Details ==
Series: drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset
URL : https://patchwork.freedesktop.org/series/43404/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4205_full -> Patchwork_9047_full =
== Summary - FAILURE ==
Serious unknown
On 18/05/2018 15:13, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-05-18 13:36:52)
On 18/05/2018 13:28, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-05-18 12:50:41)
On 18/05/2018 12:10, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-05-18 12:05:17)
On 18/05/2018 11:09, Chris Wil
Quoting Lionel Landwerlin (2018-05-18 15:29:21)
> On 18/05/18 15:26, Lionel Landwerlin wrote:
> > On Gen8+ this register is not priviledged and we want to use it in
> > Mesa to implement a feature required by GPA called Null Hardware. The
> > idea is to have the command parser turn 3DPRIMITIVE/GPGP
Since drm_framebuffer can now store GEM objects directly, place them
there rather than in our own subclass.
v2: Only hold a single reference per framebuffer, not per plane. (Ville)
v3: Drop NULL check in intel_fb_obj. (Ville)
Signed-off-by: Daniel Stone
Reviewed-by: Ville Syrjälä
Cc: Jani Nikul
We already have a macro to pull the GEM object from a FB, so use it
everywhere. We'll make use of this later to move the object storage.
Signed-off-by: Daniel Stone
Reviewed-by: Ville Syrjälä
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: intel-gfx@lists.freedesktop.org
---
drivers
On 18/05/18 15:26, Lionel Landwerlin wrote:
On Gen8+ this register is not priviledged and we want to use it in
Mesa to implement a feature required by GPA called Null Hardware. The
idea is to have the command parser turn 3DPRIMITIVE/GPGPU_WALKER into
NOOPs.
This patch just whitelists the bits th
On Fri, Mar 09, 2018 at 11:22:04PM +0100, Ondrej Zary wrote:
> Radiant P845 does not have LVDS, only VGA.
>
> Signed-off-by: Ondrej Zary
Since we failed with the VBT approach I've gone and pushed this
as is to dinq (with cc:stable and the bugzilla link added).
Thanks for the patch.
> ---
> dr
On Thu, May 17, 2018 at 08:49:27PM +0300, Jani Nikula wrote:
> On Thu, 17 May 2018, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > i965 does not have native DP. Let's rename the remaining gen4 references
> > in the DP code to g4x.
> >
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Jani
On Gen8+ this register is not priviledged and we want to use it in
Mesa to implement a feature required by GPA called Null Hardware. The
idea is to have the command parser turn 3DPRIMITIVE/GPGPU_WALKER into
NOOPs.
This patch just whitelists the bits that we need and that are
currently not used by
Quoting Fritz Koenig (2018-05-17 20:07:14)
> Planes with an odd width will appear to have an incorrect
> stride. When the start position is odd the controller
> can lock up.
>
> Signed-off-by: Fritz Koenig
> ---
>
> Hi,
>
> This appears to be a limitation of the hardware that is not being
> che
On Fri, May 18, 2018 at 03:25:26PM +0300, Ville Syrjälä wrote:
> On Thu, May 17, 2018 at 12:07:14PM -0700, Fritz Koenig wrote:
> > Planes with an odd width will appear to have an incorrect
> > stride. When the start position is odd the controller
> > can lock up.
>
> Just remove the strange NV12 c
Quoting Tvrtko Ursulin (2018-05-18 13:36:52)
>
> On 18/05/2018 13:28, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-05-18 12:50:41)
> >>
> >> On 18/05/2018 12:10, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2018-05-18 12:05:17)
>
> On 18/05/2018 11:09, Chris Wilson wrote:
>
On Fri, May 18, 2018 at 02:48:44PM +0100, Daniel Stone wrote:
> Since drm_framebuffer can now store GEM objects directly, place them
> there rather than in our own subclass.
>
> v2: Only hold a single reference per framebuffer, not per plane. (Ville)
>
> Signed-off-by: Daniel Stone
> Cc: Ville S
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Use intel_fb_obj() everywhere
URL : https://patchwork.freedesktop.org/series/43418/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4206 -> Patchwork_9051 =
== Summary - SUCCESS ==
No regressions found.
Hi Neil,
2018-05-18 15:04 GMT+02:00 Neil Armstrong :
> Hi All,
>
> The new Google "Fizz" Intel-based ChromeOS device is gaining CEC support
> through it's Embedded Controller, to enable the Linux CEC Core to communicate
> with it and get the CEC Physical Address from the correct HDMI Connector, th
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Use intel_fb_obj() everywhere
URL : https://patchwork.freedesktop.org/series/43418/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Use intel_fb_obj() everywhere
-O:drivers/gpu/drm/i915/intel_displ
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Use intel_fb_obj() everywhere
URL : https://patchwork.freedesktop.org/series/43418/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a498ec6deeb8 drm/i915: Use intel_fb_obj() everywhere
a7a2fce7f362 drm/i915: Mov
We already have a macro to pull the GEM object from a FB, so use it
everywhere. We'll make use of this later to move the object storage.
Signed-off-by: Daniel Stone
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org
---
drivers/gpu/drm/
Since drm_framebuffer can now store GEM objects directly, place them
there rather than in our own subclass.
v2: Only hold a single reference per framebuffer, not per plane. (Ville)
Signed-off-by: Daniel Stone
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: intel-gf
2018-05-18 15:05 GMT+02:00 Neil Armstrong :
> The EC can expose a CEC bus, thus add the cros-ec-cec MFD sub-device
> when the CEC feature bit is present.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/mfd/cros_ec_dev.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/
On 17 May 2018 at 07:03, Chris Wilson wrote:
> As i915_gem_object_phys_attach() wants to play dirty and mess around
> with obj->mm.pages itself (replacing the shmemfs with a DMA allocation),
> refactor the gubbins so into i915_gem_object_unset_pages() that we don't
> have to duplicate all the secr
On Fri, May 18, 2018 at 03:05:01PM +0200, Neil Armstrong wrote:
> This patchs adds the cec_notifier feature to the intel_hdmi part
> of the i915 DRM driver. It uses the HDMI DRM connector name to differentiate
> between each HDMI ports.
> The changes will allow the i915 HDMI code to notify EDID and
== Series Details ==
Series: GMBUS changes (rev5)
URL : https://patchwork.freedesktop.org/series/41632/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4204_full -> Patchwork_9045_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9045_full need to
== Series Details ==
Series: Add ChromeOS EC CEC Support (rev4)
URL : https://patchwork.freedesktop.org/series/43162/
State : failure
== Summary ==
Applying: media: cec-notifier: Get notifier by device and connector name
Applying: drm/i915: hdmi: add CEC notifier to intel_hdmi
Applying: mfd: c
The Chrome OS Embedded Controller can expose a CEC bus, this patch add the
driver for such feature of the Embedded Controller.
This driver is part of the cros-ec MFD and will be add as a sub-device when
the feature bit is exposed by the EC.
The controller will only handle a single logical address
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