Quoting Matthew Auld (2018-05-10 22:12:13)
> On 10 May 2018 at 20:56, Chris Wilson wrote:
> > Quoting Matthew Auld (2018-05-10 20:00:06)
> >> We write out all PTEs when operating in 64K mode, which is acceptable
> >> given the assertion that the hw only cares about every 16th PTE and so
> >> will
On 2018.05.10 16:17:35 +0100, Matthew Auld wrote:
> > @@ -934,6 +944,20 @@ static int ppgtt_invalidate_spt(struct
> > intel_vgpu_ppgtt_spt *spt)
> > return ret;
> > }
> >
> > +static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
> > +{
> > + if (INTEL_GEN(vgpu->gvt->dev_priv) == 9)
== Series Details ==
Series: drm/psr: Fix missed entry in PSR setup time table.
URL : https://patchwork.freedesktop.org/series/43032/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4164_full -> Patchwork_8978_full =
== Summary - FAILURE ==
Serious unknown changes coming w
== Series Details ==
Series: drm/psr: Fix missed entry in PSR setup time table.
URL : https://patchwork.freedesktop.org/series/43032/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4164 -> Patchwork_8978 =
== Summary - SUCCESS ==
No regressions found.
External URL:
ht
Entry corresponding to 220 us setup time was missing. I am not aware of
any specific bug this fixes, but this could potentially result in enabling
PSR on a panel with a higher setup time requirement than supported by the
hardware.
I verified the value is present in eDP spec versions 1.3, 1.4 and 1
== Series Details ==
Series: drm/i915/icl: Read the correct Gen11 interrupt registers (rev2)
URL : https://patchwork.freedesktop.org/series/43027/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4164_full -> Patchwork_8977_full =
== Summary - WARNING ==
Minor unknown chang
== Series Details ==
Series: drm/i915/icl: Read the correct Gen11 interrupt registers (rev2)
URL : https://patchwork.freedesktop.org/series/43027/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4164 -> Patchwork_8977 =
== Summary - WARNING ==
Minor unknown changes coming
Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt repartitioning scheme.
Note that the equivalent to the PM ISR & IIR cannot be read without
affecting the current state of the system, so I've opted for lea
== Series Details ==
Series: drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
URL : https://patchwork.freedesktop.org/series/43024/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4164_full -> Patchwork_8975_full =
== Summary - WARNING ==
Minor unknown changes com
== Series Details ==
Series: drm/i915/icl: Read the correct Gen11 interrupt registers
URL : https://patchwork.freedesktop.org/series/43027/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsreleas
Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt repartitioning scheme.
Note that the equivalent to the PM ISR & IIR cannot be read without
affecting the current state of the system, so I've opted for lea
On 10 May 2018 at 20:56, Chris Wilson wrote:
> Quoting Matthew Auld (2018-05-10 20:00:06)
>> We write out all PTEs when operating in 64K mode, which is acceptable
>> given the assertion that the hw only cares about every 16th PTE and so
>> will ignore everything else. However this may hide potent
== Series Details ==
Series: drm/i915/selftests: scrub 64K
URL : https://patchwork.freedesktop.org/series/43023/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4164_full -> Patchwork_8974_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8974_full
On Fri, 30 Mar 2018 10:31:51 +0200, Sagar Arun Kamble
wrote:
Populate SLPC shared data with required default values for slice count,
power source/plan, IA perf MSRs.
v1: Update for SLPC interface version 2015.2.4. intel_slpc_active()
returns 1 if slpc initialized (Paulo)
change defau
== Series Details ==
Series: drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
URL : https://patchwork.freedesktop.org/series/43024/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4164 -> Patchwork_8975 =
== Summary - SUCCESS ==
No regressions found.
External U
On Fri, 30 Mar 2018 10:31:48 +0200, Sagar Arun Kamble
wrote:
SLPC operates based on parameters setup in shared data between i915 and
GuC SLPC. This is to be created/initialized in intel_guc_slpc_init. From
there onwards i915 can control the SLPC operations by enabling, disabling
complete SLPC
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#160184
Signed-off-by: Michel Thierry
Cc: mesa-...@lists.freedesktop.org
Cc: Mika Kuoppala
Cc: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarou
== Series Details ==
Series: drm/i915/selftests: scrub 64K
URL : https://patchwork.freedesktop.org/series/43023/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4164 -> Patchwork_8974 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.freed
Quoting Matthew Auld (2018-05-10 20:00:06)
> We write out all PTEs when operating in 64K mode, which is acceptable
> given the assertion that the hw only cares about every 16th PTE and so
> will ignore everything else. However this may hide potential issues,
> for example the hw could be sneakily
We write out all PTEs when operating in 64K mode, which is acceptable
given the assertion that the hw only cares about every 16th PTE and so
will ignore everything else. However this may hide potential issues,
for example the hw could be sneakily operating in 4K mode and we would
be none the wiser
Quoting Tvrtko Ursulin (2018-05-10 18:26:31)
>
> On 10/05/2018 17:25, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-05-10 17:09:14)
> >>
> >> On 09/05/2018 15:27, Chris Wilson wrote:
> >>> Bypass using the tasklet to submit the first request to HW, as the
> >>> tasklet may be deferred unto
On 10/05/2018 17:25, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-05-10 17:09:14)
On 09/05/2018 15:27, Chris Wilson wrote:
Bypass using the tasklet to submit the first request to HW, as the
tasklet may be deferred unto ksoftirqd and at a minimum will add in
excess of 10us (and maybe tens
On 10/05/2018 17:19, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-05-10 17:15:46)
On 10/05/2018 17:03, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-05-10 16:49:03)
On 09/05/2018 15:27, Chris Wilson wrote:
In the next few patches, we want to abuse tasklet to avoid ksoftirqd
latency
Quoting Tvrtko Ursulin (2018-05-10 17:09:14)
>
> On 09/05/2018 15:27, Chris Wilson wrote:
> > Bypass using the tasklet to submit the first request to HW, as the
> > tasklet may be deferred unto ksoftirqd and at a minimum will add in
> > excess of 10us (and maybe tens of milliseconds) to our execut
Quoting Tvrtko Ursulin (2018-05-10 17:15:46)
>
> On 10/05/2018 17:03, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-05-10 16:49:03)
> >>
> >> On 09/05/2018 15:27, Chris Wilson wrote:
> >>> In the next few patches, we want to abuse tasklet to avoid ksoftirqd
> >>> latency along critical path
On 10/05/2018 17:03, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-05-10 16:49:03)
On 09/05/2018 15:27, Chris Wilson wrote:
In the next few patches, we want to abuse tasklet to avoid ksoftirqd
latency along critical paths. To make that abuse easily to swallow,
first coat the tasklet in a l
On 09/05/2018 15:27, Chris Wilson wrote:
Bypass using the tasklet to submit the first request to HW, as the
tasklet may be deferred unto ksoftirqd and at a minimum will add in
excess of 10us (and maybe tens of milliseconds) to our execution
latency. This latency reduction is most notable when ex
Quoting Tvrtko Ursulin (2018-05-10 16:49:03)
>
> On 09/05/2018 15:27, Chris Wilson wrote:
> > In the next few patches, we want to abuse tasklet to avoid ksoftirqd
> > latency along critical paths. To make that abuse easily to swallow,
> > first coat the tasklet in a little syntactic sugar.
> >
>
== Series Details ==
Series: drm/i915/guc: Don't store runtime GuC log level in modparam
URL : https://patchwork.freedesktop.org/series/43013/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8973_full =
== Summary - WARNING ==
Minor unknown changes c
On 09/05/2018 15:27, Chris Wilson wrote:
In the next few patches, we want to abuse tasklet to avoid ksoftirqd
latency along critical paths. To make that abuse easily to swallow,
first coat the tasklet in a little syntactic sugar.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gp
On 8 May 2018 at 10:05, wrote:
> From: Changbin Du
>
> This change help us detect the real entry type per PSE and IPS setting.
> For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA.
>
> Signed-off-by: Changbin Du
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 68
> +
== Series Details ==
Series: drm/i915/guc: Don't store runtime GuC log level in modparam
URL : https://patchwork.freedesktop.org/series/43013/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8973 =
== Summary - SUCCESS ==
No regressions found.
External
From: Piotr Piórkowski
Currently we are using modparam as placeholder for GuC log level.
Stop doing this and keep runtime GuC level in intel_guc_log struct.
Signed-off-by: Piotr Piórkowski
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i9
On 8 May 2018 at 10:05, wrote:
> From: Changbin Du
>
> To support huge gtt, we need to support huge pages in kvmgt first.
> This patch adds a 'size' param to the intel_gvt_mpt::dma_map_guest_page
> API and implements it in kvmgt.
>
> v2: rebase.
>
> Signed-off-by: Changbin Du
> ---
> drivers/g
On Wed, Apr 18, 2018 at 12:32 AM, Souptick Joarder wrote:
> Use new return type vm_fault_t for fault handler. For
> now, this is just documenting that the function returns
> a VM_FAULT value rather than an errno. Once all instances
> are converted, vm_fault_t will become a distinct type.
>
> Refer
Quoting Chris Wilson (2018-05-09 15:28:00)
> Continuing the theme of bypassing ksoftirqd latency, also first try to
> directly submit from the CS interrupt handler to clear the ELSP and
> queue the next.
>
> In the past, we have been hesitant to do this as the context switch
> processing has been
From: Tvrtko Ursulin
We want to make sure RT tasks which use a lot of CPU times can submit
batch buffers with roughly the same latency (and certainly not worse)
compared to normal tasks.
v2: Add tests to run across all engines simultaneously to encourage
ksoftirqd to kick in even more often.
Si
From: Tvrtko Ursulin
Incomplete requests (no notify, no context complete) have to be corrected
by looking at the engine timeline, and not the sorted-by-start-time view
as was previously used.
Per-engine timelines are generated on demand and cached for later use.
v2: Find end of current context
From: Tvrtko Ursulin
Skip accounting the context save time for anything but the last request of
the coalesced bunch, and also skip drawing those boxes on the timeline.
Signed-off-by: Tvrtko Ursulin
---
scripts/trace.pl | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --g
From: Tvrtko Ursulin
Few micro-second long boxes cannot be displayed by the visualizer in a
meaningful way so just burden the browser and the human looking at the
noise. Sp skip drawing anything shorter and 10us.
Signed-off-by: Tvrtko Ursulin
---
scripts/trace.pl | 15 ++-
1 file c
From: Tvrtko Ursulin
Just forget about earlier request_in events.
Signed-off-by: Tvrtko Ursulin
---
scripts/trace.pl | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/scripts/trace.pl b/scripts/trace.pl
index c795406ae785..92431974296a 100755
--- a/scripts/trace.pl
+++ b/s
From: Tvrtko Ursulin
Request split mode had several bugs, both in the original version and also
after the recent refactorings.
One big one was that it wasn't considering different submit ports as a
reason to split execution, and also that it was too time based instead of
looking at relevant time
From: Tvrtko Ursulin
Timeline id allocation order is not tied with engine ids any more.
Remove the option which assumed that was the case in attempt to provide
more readable timeline.
Signed-off-by: Tvrtko Ursulin
---
scripts/media-bench.pl | 2 +-
scripts/trace.pl | 18 ---
From: Tvrtko Ursulin
Add the command line switch which uses different colours for different
context execution boxes.
v2:
* Use HSL to simplify color generation. (Lionel)
* Colour other boxes in the same colour but different shade so it is
easier to follow the timeline.
Signed-off-by: Tvrtk
From: Tvrtko Ursulin
In split mode all requests have to be added up since they were previously
re-arranged so there is no overlap.
Signed-off-by: Tvrtko Ursulin
Cc: John Harrison
---
scripts/trace.pl | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/trace.pl b/scri
From: Tvrtko Ursulin
We add stripes for different stages of request execution so it is easier
to follow one context in the multi-colour mode.
Vertical stripe pattern indicates pipeline "blockages" - requests waiting
for dependencies before they are runnable.
Diagonal stripes indicate runnable r
== Series Details ==
Series: RFT gem_mmap_gtt/gdg: 2 tile rows
URL : https://patchwork.freedesktop.org/series/42990/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8971_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8971_
== Series Details ==
Series: RFT gem_mmap_gtt/gdg Throw in a wmb
URL : https://patchwork.freedesktop.org/series/42988/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8970_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_897
== Series Details ==
Series: drm/dp: add module parameter for the dpcd access max retries (rev2)
URL : https://patchwork.freedesktop.org/series/42803/
State : failure
== Summary ==
Applying: drm/dp: add module parameter for the dpcd access max retries
error: corrupt patch at line 9
error: coul
Report and compare stddev instead of variance so that direct submission
passes ;)
---
tests/gem_exec_latency.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/tests/gem_exec_latency.c b/tests/gem_exec_latency.c
index 547d728b3..757b390d0 100644
--- a/tests/
> -Original Message-
> From: Srinivas, Vidya
> Sent: Tuesday, May 8, 2018 5:08 PM
> To: 'Maarten Lankhorst' ; 'intel-
> g...@lists.freedesktop.org'
> Subject: RE: [PATCH v7 3/6] drm/i915: Add skl_check_nv12_surface for NV12
>
>
>
> > -Original Message-
> > From: Srinivas, Vidy
On Wed, May 09, 2018 at 12:28:15PM +0300, Jani Nikula wrote:
> On Wed, 09 May 2018, Feng Tang wrote:
> > On Wed, May 09, 2018 at 10:53:53AM +0300, Jani Nikula wrote:
> >> On Wed, 09 May 2018, Feng Tang wrote:
> >> > On Tue, May 08, 2018 at 10:30:19PM +0300, Jani Nikula wrote:
> >> >> On Wed, 09 M
Quoting Chris Wilson (2018-05-10 09:13:02)
> ---
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 89bf5d67cb74..d92857c879c1 100644
> --- a/drivers/gpu/drm/i915/i915
== Series Details ==
Series: RFT gem_mmap_gtt/gdg: 2 tile rows
URL : https://patchwork.freedesktop.org/series/42990/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8971 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.f
== Series Details ==
Series: RFT gem_mmap_gtt/gdg: 2 tile rows
URL : https://patchwork.freedesktop.org/series/42990/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4c164840dbb9 RFT gem_mmap_gtt/gdg: 2 tile rows
-:19: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total:
Quoting Chris Wilson (2018-05-10 08:47:31)
> ---
> drivers/gpu/drm/i915/i915_gem.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 89bf5d67cb74..4c26e1fed6c6 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/d
== Series Details ==
Series: RFT gem_mmap_gtt/gdg Throw in a wmb
URL : https://patchwork.freedesktop.org/series/42988/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8970 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 89bf5d67cb74..d92857c879c1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1958,7 +
== Series Details ==
Series: RFT gem_mmap_gtt/gdg Throw in a wmb
URL : https://patchwork.freedesktop.org/series/42988/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
36ebf10700bc RFT gem_mmap_gtt/gdg Throw in a wmb
-:15: WARNING:MEMORY_BARRIER: memory barrier without comment
#15
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 89bf5d67cb74..4c26e1fed6c6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2089,6 +2089,7 @@ int i9
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