[Intel-gfx] ✓ Fi.CI.IGT: success for Preparation patches for NV12

2018-04-08 Thread Patchwork
== Series Details == Series: Preparation patches for NV12 URL : https://patchwork.freedesktop.org/series/41340/ State : success == Summary == Possible new issues: Test gem_pwrite: Subgroup big-gtt-backwards: skip -> PASS (shard-apl) Known issues:

[Intel-gfx] ✓ Fi.CI.BAT: success for Preparation patches for NV12

2018-04-08 Thread Patchwork
== Series Details == Series: Preparation patches for NV12 URL : https://patchwork.freedesktop.org/series/41340/ State : success == Summary == Series 41340v1 Preparation patches for NV12 https://patchwork.freedesktop.org/api/1.0/series/41340/revisions/1/mbox/ Known issues: Test debugfs_t

[Intel-gfx] [PATCH v1 09/14] drm/i915/skl: split skl_compute_ddb function

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. v2: Added reviewed by tag from Shashank Sharma v3: Added reviewed by from Juha-Pekka Heikkila v4: Rebas

[Intel-gfx] [PATCH v1 13/14] drm/i915: Update format_is_yuv() to include NV12

2018-04-08 Thread Vidya Srinivas
From: Chandra Konduru This patch adds NV12 to format_is_yuv() function for sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) v3: Rebased (me) v4: Rebased and addressed review comments from Clinton A Taylor. "static function in intel_sprite.c is not available to the primary plane

[Intel-gfx] [PATCH v1 01/14] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl

[Intel-gfx] [PATCH v1 11/14] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

2018-04-08 Thread Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits for the conversion. v2: Addressed review comments from Shashank Sharma Alignment issue fixed in i915_reg.h v3: Adding Reviewed By from Shashank Sharma v4: Rebased the patch. As part of rebasing, re-using the color series defines which are a

[Intel-gfx] [PATCH v1 05/14] drm/i915/skl+: NV12 related changes for WM

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. v2: Addressed review comments from Shashank Sharma. v3: Addressed review comments from Shashank Sharma Changed plane_num to plane_id in skl_compute_plane_wm_par

[Intel-gfx] [PATCH v1 00/14] Preparation patches for NV12

2018-04-08 Thread Vidya Srinivas
Series contain preparation patches for NV12 support Enabling NV12 KMD support will follow the series Chandra Konduru (3): drm/i915: Set scaler mode for NV12 drm/i915: Update format_is_yuv() to include NV12 drm/i915: Upscale scaler max scale for NV12 Mahesh Kumar (9): drm/i915/skl+: rename

[Intel-gfx] [PATCH v1 12/14] drm/i915: Set scaler mode for NV12

2018-04-08 Thread Vidya Srinivas
From: Chandra Konduru This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling v2: Review comments from Ville addressed NV12 case to be checked first for setting the scaler v3: Rebased (me) v

[Intel-gfx] [PATCH v1 14/14] drm/i915: Upscale scaler max scale for NV12

2018-04-08 Thread Vidya Srinivas
From: Chandra Konduru This patch updates scaler max limit support for NV12 v2: Rebased (me) v3: Rebased (me) v4: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v5: Addressed review comments from Ville and rebased - calculation of max

[Intel-gfx] [PATCH v1 04/14] drm/i915/skl+: support verification of DDB HW state for NV12

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in the Plane NV12 Buffer Conf

[Intel-gfx] [PATCH v1 08/14] drm/i915/skl+: nv12 workaround disable WM level 1-7

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C states or do not enable late

[Intel-gfx] [PATCH v1 07/14] drm/i915/skl+: make sure higher latency level has higher wm value

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. v2: Change

[Intel-gfx] [PATCH v1 03/14] drm/i915/skl+: add NV12 in skl_format_to_fourcc

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. v2: Added reviewed by tag from Mika Kahola v3: Added reviewed by from Juha-Pekka Heikkila v4: Rebased the series Reviewed-by: Juha-Pekka Heikkila Reviewed-by: Mika Kahola Signed-off-by: Mahesh Ku

[Intel-gfx] [PATCH v1 06/14] drm/i915/skl+: pass skl_wm_level struct to wm compute func

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank Sharma v3: Adding reviewed by

[Intel-gfx] [PATCH v1 10/14] drm/i915: Display WA 827

2018-04-08 Thread Vidya Srinivas
Display WA 827 applies to GEN9 (excluede GLK) and CNL. Switching the plane format from NV12 to RGB and leaving system idle results in display underrun and corruption. WA: Set the bit 15 & bit 19 to 1b in the CLKGATE_DIS_PSL register for the pipe in which NV12 plane is enabled. v2: Addressed review

[Intel-gfx] [PATCH v1 02/14] drm/i915/skl+: refactor WM calculation for NV12

2018-04-08 Thread Vidya Srinivas
From: Mahesh Kumar Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten v3: Rebased and addressed r

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/audio: Fix audio detection issue on GLK

2018-04-08 Thread Patchwork
== Series Details == Series: drm/i915/audio: Fix audio detection issue on GLK URL : https://patchwork.freedesktop.org/series/41334/ State : failure == Summary == Series 41334v1 drm/i915/audio: Fix audio detection issue on GLK https://patchwork.freedesktop.org/api/1.0/series/41334/revisions/1/m

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/audio: Fix audio detection issue on GLK

2018-04-08 Thread Patchwork
== Series Details == Series: drm/i915/audio: Fix audio detection issue on GLK URL : https://patchwork.freedesktop.org/series/41334/ State : warning == Summary == $ dim checkpatch origin/drm-tip ccec6d316968 drm/i915/audio: Fix audio detection issue on GLK -:26: CHECK:PARENTHESIS_ALIGNMENT: Ali

[Intel-gfx] [PATCH] drm/i915/audio: Fix audio detection issue on GLK

2018-04-08 Thread Gaurav K Singh
On Geminilake, sometimes audio card is not getting detected after reboot. This is a spurious issue happening on Geminilake. HW codec and HD audio controller link was going out of sync for which there was a fix in i915 driver but was not getting invoked for GLK. Extending this fix to GLK as well. T