== Series Details ==
Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
URL : https://patchwork.freedesktop.org/series/41297/
State : success
== Summary ==
Possible new issues:
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
fail
== Series Details ==
Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake
Workarounds
URL : https://patchwork.freedesktop.org/series/41311/
State : failure
== Summary ==
Possible new issues:
Test kms_atomic_transition:
Subgroup plane-all-transition-fencin
== Series Details ==
Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as
guilty until proven innocent
URL : https://patchwork.freedesktop.org/series/41308/
State : failure
== Summary ==
Possible new issues:
Test kms_atomic_transition:
Subgroup plane-all-tra
== Series Details ==
Series: drm/i915: Treat i915_reset_engine() as guilty until proven innocent
URL : https://patchwork.freedesktop.org/series/41305/
State : warning
== Summary ==
Possible new issues:
Test kms_atomic_transition:
Subgroup plane-all-transition-fencing:
== Series Details ==
Series: drm/i915/dp: Send DPCD ON for MST before phy_up (rev2)
URL : https://patchwork.freedesktop.org/series/41297/
State : success
== Summary ==
Series 41297v2 drm/i915/dp: Send DPCD ON for MST before phy_up
https://patchwork.freedesktop.org/api/1.0/series/41297/revision
On Sat, 2018-04-07 at 00:49 +, Souza, Jose wrote:
> On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote:
> > On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote:
> > > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote:
> > > > IGT tests could be improved wit
When doing a modeset where the sink is transitioning from D3 to D0 , it
would sometimes be possible for the initial power_up_phy() to start
timing out. This would only be observed in the last action before the
sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
originally thought t
== Series Details ==
Series: drm/i915/dp: Send DPCD ON for MST before phy_up
URL : https://patchwork.freedesktop.org/series/41297/
State : failure
== Summary ==
Possible new issues:
Test gem_pwrite:
Subgroup big-gtt-backwards:
pass -> SKIP (shard-apl)
On Fri, 2018-04-06 at 16:36 -0700, José Roberto de Souza wrote:
> On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote:
> > On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote:
> > > IGT tests could be improved with sink status, knowing for sure
> > > that
> > > hardware have ac
== Series Details ==
Series: drm/i915/psr: enable psr1 on psr2 panels
URL : https://patchwork.freedesktop.org/series/41294/
State : warning
== Summary ==
Possible new issues:
Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -> PASS (shard-hsw)
On Mon, 2018-04-02 at 15:38 -0700, Pandiyan, Dhinakaran wrote:
> On Mon, 2018-04-02 at 13:51 -0700, José Roberto de Souza wrote:
> > IGT tests could be improved with sink status, knowing for sure that
> > hardware have activate or exit PSR.
> >
> > Reviewed-by: Dhinakaran Pandiyan
>
>
> Please
== Series Details ==
Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake
Workarounds
URL : https://patchwork.freedesktop.org/series/41311/
State : success
== Summary ==
Series 41311v1 series starting with [01/22] drm/i915/icl: Introduce initial
Icelake Workarounds
ht
Quoting Michel Thierry (2018-04-06 23:35:43)
> I would s/BIT()/ENGINE_MASK()/g, but it's not like we enforce it
> (engine_struck has BIT(engine->id)).
Done. ENGINE_MASK looks more semantically consistent with calling it
"stalled_mask, the set of guilty engines".
-Chris
___
== Series Details ==
Series: series starting with [01/22] drm/i915/icl: Introduce initial Icelake
Workarounds
URL : https://patchwork.freedesktop.org/series/41311/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
080bab08b911 drm/i915/icl: Introduce initial Icelake Workarounds
-:
Quoting Michel Thierry (2018-04-06 23:35:43)
> On 4/6/2018 3:03 PM, Chris Wilson wrote:
> > -static u32 fake_hangcheck(struct i915_request *rq)
> > +static u32 fake_hangcheck(struct i915_request *rq, u32 mask)
> > {
> > - u32 reset_count;
> > + struct i915_gpu_error *error = &rq->i915->gp
== Series Details ==
Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as
guilty until proven innocent
URL : https://patchwork.freedesktop.org/series/41308/
State : success
== Summary ==
Series 41308v1 series starting with [1/2] drm/i915: Treat i915_reset_engine()
as gui
On 4/6/2018 3:03 PM, Chris Wilson wrote:
Currently, we rely on inspecting the hangcheck state from within the
i915_reset() routines to determine which engines were guilty of the
hang. This is problematic for cases where we want to run
i915_handle_error() and call i915_reset() independently of han
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_engine_cs.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers
Avoids a hang during soft reset.
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 8
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index af4f
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.
v2: Wrong operation to clear the bit (Praveen)
Cc: Sagar Arun Kamble
Cc: Praveen Paneri
Cc: Mika Kuoppa
Disable blend embellishment in RCC.
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h| 18 +++---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
Required to dinamically set 'Small PL Lossless Fix Enable'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
Cc: Mika Kuoppala
Signed-off
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_pm.c | 7 +++
2 files changed, 11
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/d
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for WaInPlaceDecompressionHang.
- Squashed with this patch:
drm/i915/icl: add ice
Required for Bindless samplers.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h| 2 ++
drivers/gpu
Required to dinamically set 'Trilinear Filter Quality Mode'
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
Cc: Mika Kuoppala
Signed-of
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 9 insertions(+), 2 dele
Disable I2M Write for performance reasons.
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i
Required for TR-TT (Tiled Resource Translation Table) support.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: For whatever reason, this ended up in KBL (??!!)
Cc: Mika Kuoppala
Signed
Disable CGPSF unit clock gating to prevent an issue.
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
Revert to the legacy implementation.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Rebased
- Renamed to Wa_2006611047
- A0 and B0 only
v4:
- Add spaces around '<<' (and fix the surrounding code as well)
- Mark the WA as pre-prod
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/dr
Enables blend optimization for floating point RTs
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i91
Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...
v2: Rebased
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed, 10 insertions(+)
diff --git a/driver
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 9 in
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 9 insertions(+),
== Series Details ==
Series: series starting with [1/2] drm/i915: Treat i915_reset_engine() as
guilty until proven innocent
URL : https://patchwork.freedesktop.org/series/41308/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2957aaafaf83 drm/i915: Treat i915_reset_engine() as g
On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > Inside the psr work function, we want to wait for PSR to idle first
> > and
> > wish to do so without blocking the normal modeset path, so we do so
> > without holding the PSR l
Quoting Michel Thierry (2018-04-06 22:44:34)
> On 4/6/2018 2:30 PM, Chris Wilson wrote:
> > Quoting Michel Thierry (2018-04-06 22:23:21)
> >> And I thought we believed in presumption of innocence...
> >>
> >> On 4/6/2018 2:00 PM, Chris Wilson wrote:
> >>> If we are resetting just one engine, we kno
If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to i915_gem_reset_engine(), which
alleviates the necessity to poke at the generic engine->hangcheck.stalled
magic variable, leaving that under control of hangcheck as its name
implies. Other t
Currently, we rely on inspecting the hangcheck state from within the
i915_reset() routines to determine which engines were guilty of the
hang. This is problematic for cases where we want to run
i915_handle_error() and call i915_reset() independently of hangcheck.
Instead of relying on the indirect
== Series Details ==
Series: drm/i915/psr: vbt change for psr
URL : https://patchwork.freedesktop.org/series/41289/
State : failure
== Summary ==
Possible new issues:
Test drm_read:
Subgroup invalid-buffer:
pass -> FAIL (shard-snb)
Test gem_mmap_gtt:
On 4/6/2018 2:30 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-04-06 22:23:21)
And I thought we believed in presumption of innocence...
On 4/6/2018 2:00 PM, Chris Wilson wrote:
If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to
== Series Details ==
Series: drm/i915: Treat i915_reset_engine() as guilty until proven innocent
URL : https://patchwork.freedesktop.org/series/41305/
State : success
== Summary ==
Series 41305v1 drm/i915: Treat i915_reset_engine() as guilty until proven
innocent
https://patchwork.freedesktop
Quoting Michel Thierry (2018-04-06 22:23:21)
> And I thought we believed in presumption of innocence...
>
> On 4/6/2018 2:00 PM, Chris Wilson wrote:
> > If we are resetting just one engine, we know it has stalled. So we can
> > pass the stalled parameter directly to i915_gem_reset_engine(), which
And I thought we believed in presumption of innocence...
On 4/6/2018 2:00 PM, Chris Wilson wrote:
If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to i915_gem_reset_engine(), which
alleviates the necessity to poke at the generic engine->h
== Series Details ==
Series: Aspect ratio support in DRM layer (rev2)
URL : https://patchwork.freedesktop.org/series/39960/
State : failure
== Summary ==
Possible new issues:
Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -> PASS (shard-hsw)
== Series Details ==
Series: series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware
tracking size
URL : https://patchwork.freedesktop.org/series/41303/
State : warning
== Summary ==
Series 41303v1 series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+
hardware tracking
Quoting José Roberto de Souza (2018-04-06 21:53:49)
> A simple page flip can cause the CFB required size to increase and
> if it is bigger than the currently allocated CFB it needs to be
> resized to activate FBC again.
I would have expected the answer to be to plug into atomic. During the
prepare
If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to i915_gem_reset_engine(), which
alleviates the necessity to poke at the generic engine->hangcheck.stalled
magic variable, leaving that under control of hangcheck as its name
implies. Other t
== Series Details ==
Series: series starting with [1/2] drm/i915/fbc/cnl: Add GLK and CNL+ hardware
tracking size
URL : https://patchwork.freedesktop.org/series/41303/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
51c1ab0d8ad0 drm/i915/fbc/cnl: Add GLK and CNL+ hardware tracki
A simple page flip can cause the CFB required size to increase and
if it is bigger than the currently allocated CFB it needs to be
resized to activate FBC again.
Until now this case was not being handled but CI is starting to
get some of this errors.
So here it will free the old CFB and a try to
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_fbc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 707d49c12638..573b034a02fd 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
== Series Details ==
Series: drm/i915: Split out parking from the idle worker for reuse (rev2)
URL : https://patchwork.freedesktop.org/series/41278/
State : success
== Summary ==
Possible new issues:
Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -
Quoting Lionel Landwerlin (2018-04-05 14:05:52)
> On 05/04/18 13:39, Tvrtko Ursulin wrote:
> > +
> > + /** Number of requests with unresolved fences and dependencies. */
> > + __u32 queued;
> > +
> > + /** Number of ready requests waiting on a slot on GPU. */
> > + __u32 runnable;
>
Quoting Tvrtko Ursulin (2018-04-05 13:39:22)
> From: Tvrtko Ursulin
>
> We add a PMU counter to expose the number of requests currently executing
> on the GPU.
>
> This is useful to analyze the overall load of the system.
>
> v2:
> * Rebase.
> * Drop floating point constant. (Chris Wilson)
>
Quoting Tvrtko Ursulin (2018-04-05 13:39:21)
> From: Tvrtko Ursulin
>
> We add a PMU counter to expose the number of requests with resolved
> dependencies waiting for a slot on the GPU to run.
>
> This is useful to analyze the overall load of the system.
>
> v2: Don't limit to gen8+.
>
> v3:
>
Quoting Tvrtko Ursulin (2018-04-05 13:39:20)
> From: Tvrtko Ursulin
>
> We add a PMU counter to expose the number of requests which have been
> submitted from userspace but are not yet runnable due dependencies and
> unsignaled fences.
>
> This is useful to analyze the overall load of the system
Quoting Tvrtko Ursulin (2018-04-05 13:39:19)
> From: Tvrtko Ursulin
>
> Keep a count of requests submitted from userspace and not yet runnable due
> unresolved dependencies.
>
> v2: Rename and move under the container struct. (Chris Wilson)
> v3: Rebase.
>
> Signed-off-by: Tvrtko Ursulin
> ---
Quoting Tvrtko Ursulin (2018-04-05 13:39:18)
> From: Tvrtko Ursulin
>
> Keep a per-engine number of runnable (waiting for GPU time) requests.
>
> v2:
> * Move queued increment from insert_request to execlist_submit_request to
>avoid bumping when re-ordering for priority.
> * Support the co
== Series Details ==
Series: drm/i915/dp: Send DPCD ON for MST before phy_up
URL : https://patchwork.freedesktop.org/series/41297/
State : success
== Summary ==
Series 41297v1 drm/i915/dp: Send DPCD ON for MST before phy_up
https://patchwork.freedesktop.org/api/1.0/series/41297/revisions/1/mbo
== Series Details ==
Series: drm/i915: Split out parking from the idle worker for reuse (rev2)
URL : https://patchwork.freedesktop.org/series/41278/
State : success
== Summary ==
Possible new issues:
Test gem_mmap_gtt:
Subgroup forked-medium-copy-odd:
dmesg-warn -
On Fri, 2018-04-06 at 12:48 -0700, Laura Abbott wrote:
> On 04/06/2018 11:52 AM, Lyude Paul wrote:
> > When doing a modeset where the sink is transitioning from D3 to D0 , it
> > would sometimes be possible for the initial power_up_phy() to start
> > timing out. This would only be observed in the l
On 04/06/2018 11:52 AM, Lyude Paul wrote:
When doing a modeset where the sink is transitioning from D3 to D0 , it
would sometimes be possible for the initial power_up_phy() to start
timing out. This would only be observed in the last action before the
sink went into D3 mode was intel_dp_sink_dpms
On Fri, Apr 06, 2018 at 07:14:51PM +, Deepak Singh Rawat wrote:
> This makes sense once we got rid of plane->fb
>
> Will this go to drm-next?
The plan is to push to drm-misc-next once we get all
the ducks in a row.
> Could you please CC
> me so that I can do some testing myself. Thanks.
Her
== Series Details ==
Series: drm/i915/psr: enable psr1 on psr2 panels
URL : https://patchwork.freedesktop.org/series/41294/
State : success
== Summary ==
Series 41294v1 drm/i915/psr: enable psr1 on psr2 panels
https://patchwork.freedesktop.org/api/1.0/series/41294/revisions/1/mbox/
Possi
On Fri, Apr 06, 2018 at 12:28:30PM -0700, Dhinakaran Pandiyan wrote:
>
>
>
> On Fri, 2018-04-06 at 14:52 -0400, Lyude Paul wrote:
> > When doing a modeset where the sink is transitioning from D3 to D0 , it
> > would sometimes be possible for the initial power_up_phy() to start
> > timing out. Th
This makes sense once we got rid of plane->fb
Will this go to drm-next? Could you please CC
me so that I can do some testing myself. Thanks.
Reviewed-by: Deepak Rawat
>
> From: Ville Syrjälä
>
> We want to get rid of plane->fb on atomic drivers. Stop setting it.
>
> Cc: Thomas Hellstrom
>
Quoting Michal Wajdeczko (2018-04-06 17:57:20)
> On Fri, 06 Apr 2018 17:51:44 +0200, Chris Wilson
> wrote:
>
> > We will want to park GEM before disengaging the drive^W^W^W unwedging.
> > Since we already do the work for idling, expose the guts as a new
> > function that we can then reuse.
> >
On Fri, Apr 06, 2018 at 12:10:24PM -0700, Dhinakaran Pandiyan wrote:
>
>
>
> On Sat, 2018-04-07 at 00:12 +0530, vathsala nagaraju wrote:
> > From: Vathsala Nagaraju
> >
> > Adds force_psr1 mod parameter to enable psr1 on psr2 panels.
> > useful in cases where psr2 fails and user wants to enabl
== Series Details ==
Series: drm/i915/psr: enable psr1 on psr2 panels
URL : https://patchwork.freedesktop.org/series/41294/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
768ed9ff8e29 drm/i915/psr: enable psr1 on psr2 panels
-:28: CHECK:PARENTHESIS_ALIGNMENT: Alignment should ma
On Fri, 2018-04-06 at 14:52 -0400, Lyude Paul wrote:
> When doing a modeset where the sink is transitioning from D3 to D0 , it
> would sometimes be possible for the initial power_up_phy() to start
> timing out. This would only be observed in the last action before the
> sink went into D3 mode wa
>
> From: Ville Syrjälä
>
> Instead of looking at the (soon to be deprecated) plane->fb we'll
> examing plane->state->fb instead. We can do this because
> vmw_du_crtc_atomic_check() prevents us from enabling a crtc
> without the primary plane also being enabled.
>
> Due to that same reason, I'm
When doing a modeset where the sink is transitioning from D3 to D0 , it
would sometimes be possible for the initial power_up_phy() to start
timing out. This would only be observed in the last action before the
sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
originally thought t
On Sat, 2018-04-07 at 00:12 +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju
>
> Adds force_psr1 mod parameter to enable psr1 on psr2 panels.
> useful in cases where psr2 fails and user wants to enable
> psr1 feature for power saving until a fix
> is provided for psr2.
We should per
From: Vathsala Nagaraju
Adds force_psr1 mod parameter to enable psr1 on psr2 panels.
useful in cases where psr2 fails and user wants to enable
psr1 feature for power saving until a fix
is provided for psr2.
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Cc: José Roberto de Souza
Signed-off-by: Vath
Reviewed-by: Deepak Rawat
>
> From: Ville Syrjälä
>
> The only caller of vmw_kms_update_implicit_fb() is the page_flip
> hook which itself gets called with the plane mutex already held.
> Hence we can look at plane->state safely. Toss in a lockdep assert
> to make the situation more clear.
>
On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> Inside the psr work function, we want to wait for PSR to idle first
> and
> wish to do so without blocking the normal modeset path, so we do so
> without holding the PSR lock. However, we first have to find which
> pipe
> PSR was enabled on,
== Series Details ==
Series: drm/i915/psr: vbt change for psr
URL : https://patchwork.freedesktop.org/series/41289/
State : success
== Summary ==
Series 41289v1 drm/i915/psr: vbt change for psr
https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/1/mbox/
Possible new issues:
On Fri, Apr 06, 2018 at 10:55:14PM +0530, Nautiyal, Ankit K wrote:
> This patch is causing failure of IGT test kms_3d. The kms_3d test
> expects the no. of 3d modes to be 13.
>
> (The test has hard-coded value for expected no. of 3d modes as 13)
>
> But due to the addition of "matching aspect_ra
On Fri, Apr 06, 2018 at 10:58:51PM +0530, vathsala nagaraju wrote:
> From: Vathsala Nagaraju
>
> For psr block #9, the vbt description has moved to options [0-3] for
> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
> structure. Since spec does not mention from which VBT ver
== Series Details ==
Series: Aspect ratio support in DRM layer (rev2)
URL : https://patchwork.freedesktop.org/series/39960/
State : success
== Summary ==
Series 39960v2 Aspect ratio support in DRM layer
https://patchwork.freedesktop.org/api/1.0/series/39960/revisions/2/mbox/
Possible new
== Series Details ==
Series: drm/i915: Split out parking from the idle worker for reuse
URL : https://patchwork.freedesktop.org/series/41278/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race-interruptible:
pass -> FA
From: Vathsala Nagaraju
For psr block #9, the vbt description has moved to options [0-3] for
TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
structure. Since spec does not mention from which VBT version this
change was added to vbt.bsf file, we cannot depend on bdb->version
This patch is causing failure of IGT test kms_3d. The kms_3d test
expects the no. of 3d modes to be 13.
(The test has hard-coded value for expected no. of 3d modes as 13)
But due to the addition of "matching aspect_ratio" in drm_mode_equal in
this patch, the total no. of
modes in the connect
== Series Details ==
Series: Aspect ratio support in DRM layer (rev2)
URL : https://patchwork.freedesktop.org/series/39960/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e9fb8279cbaa drm/modes: Introduce drm_mode_match()
-:39: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match
== Series Details ==
Series: drm/i915: Split out parking from the idle worker for reuse (rev2)
URL : https://patchwork.freedesktop.org/series/41278/
State : success
== Summary ==
Series 41278v2 drm/i915: Split out parking from the idle worker for reuse
https://patchwork.freedesktop.org/api/1.0
From: Ankit Nautiyal
We parse the EDID and add all the modes in the connector's modelist.
This adds CEA modes with aspect ratio information too, regadless of
whether user space requested this information or not.
This patch prunes the modes with aspect-ratio information, from a
connector's modeli
From: "Sharma, Shashank"
Current DRM layer functions don't parse aspect ratio information
while converting a user mode->kernel mode or vice versa. This
causes modeset to pick mode with wrong aspect ratio, eventually
causing failures in HDMI compliance test cases, due to wrong VIC.
This patch add
From: "Sharma, Shashank"
HDMI 2.0/CEA-861-F introduces two new aspect ratios:
- 64:27
- 256:135
This patch:
- Adds new DRM flags for to represent these new aspect ratios.
- Adds new cases to handle these aspect ratios while converting
from user->kernel mode or vise versa.
This patch was once
From: Ville Syrjälä
AVI infoframe can only carry none, 4:3, or 16:9 picture aspect
ratios. Return an error if the user asked for something different.
Cc: Shashank Sharma
Cc: "Lin, Jia"
Cc: Akashdeep Sharma
Cc: Jim Bride
Cc: Jose Abreu
Cc: Daniel Vetter
Cc: Emil Velikov
Cc: Thierry Reding
From: Ankit Nautiyal
This patch adds helper functions for determining if aspect-ratio is
expected in user-mode and for allowing/disallowing the aspect-ratio,
if its not expected.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/drm_modes.c | 47 +
i
From: Ville Syrjälä
commit 6dffd431e229 ("drm: Add aspect ratio parsing in DRM layer")
cause us to not send out any VICs in the AVI infoframes. That commit
was since reverted, but if and when we add aspect ratio handing back
we need to be more careful.
Let's handle this by considering the aspect
From: Ankit Nautiyal
To enable aspect-ratio support in DRM, blindly exposing the aspect
ratio information along with mode, can break things in existing
user-spaces which have no intention or support to use this aspect
ratio information.
To avoid this, a new drm client cap is required to enable a
From: Ville Syrjälä
If the user mode would specify an aspect ratio other than 4:3 or 16:9
we now silently ignore it. Maybe a better apporoach is to return an
error? Let's try that.
Also we must be careful that we don't try to send illegal picture
aspect in the infoframe as it's only capable of s
From: Ankit Nautiyal
If the user-space does not support aspect-ratio, and requests for a
modeset with mode having aspect ratio bits set, then the given
user-mode must be rejected. Secondly, while preparing a user-mode from
kernel mode, the aspect-ratio info must not be given, if aspect-ratio
is n
From: Ville Syrjälä
Make mode matching less confusing by allowing the caller to specify
which parts of the modes should match via some flags.
Signed-off-by: Ville Syrjälä
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_modes.c | 134 ++--
include/d
1 - 100 of 196 matches
Mail list logo
