On Thu, Mar 22, 2018 at 05:59:16PM -0700, Souza, Jose wrote:
> On Thu, 2018-03-22 at 16:23 -0700, Rodrigo Vivi wrote:
> > On Thu, Mar 22, 2018 at 02:48:38PM -0700, José Roberto de Souza
> > wrote:
> > > This is a register to help debug what is in the last SDP VSC
> > > packet revived by sink.
> > >
== Series Details ==
Series: drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams
(rev4)
URL : https://patchwork.freedesktop.org/series/39979/
State : success
== Summary ==
Known issues:
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-atomic:
On 2018.03.22 21:31:33 +, Chris Wilson wrote:
> Quoting Gustavo A. R. Silva (2018-03-22 18:21:54)
> > The checks are misleading and not required [1].
> >
> > [1] https://lkml.org/lkml/2018/3/19/1792
> >
> > Addresses-Coverity-ID: 1466017
> > Cc: Chris Wilson
> > Signed-off-by: Gustavo A. R.
== Series Details ==
Series: ICL PLLs, DP/HDMI and misc display (rev4)
URL : https://patchwork.freedesktop.org/series/38737/
State : failure
== Summary ==
Applying: drm/i915/icl: add basic support for the ICL clocks
Applying: drm/i915/icl: add basic support for the ICL clocks
error: Failed to
On Thu, 2018-03-22 at 16:23 -0700, Rodrigo Vivi wrote:
> On Thu, Mar 22, 2018 at 02:48:38PM -0700, José Roberto de Souza
> wrote:
> > This is a register to help debug what is in the last SDP VSC
> > packet revived by sink.
> >
> > Signed-off-by: José Roberto de Souza
>
>
> Reviewed-by: Rodrigo
== Series Details ==
Series: series starting with [v2,1/4] drm/i915: Always do WOPCM partitioning
based on real firmware sizes
URL : https://patchwork.freedesktop.org/series/40541/
State : success
== Summary ==
Series 40541v1 series starting with [v2,1/4] drm/i915: Always do WOPCM
partitioni
On Thu, 2018-03-22 at 15:57 -0700, Rodrigo Vivi wrote:
> On Thu, Mar 22, 2018 at 02:48:39PM -0700, José Roberto de Souza
> wrote:
> > Without GTC enabled hardware is sending dummy aux frame sync value
> > that is not useful to sink do selective update, that is why it also
> > require that sink supp
On Thu, 2018-03-22 at 16:46 -0700, Rodrigo Vivi wrote:
> On Thu, Mar 22, 2018 at 02:48:48PM -0700, José Roberto de Souza
> wrote:
> > Signed-off-by: José Roberto de Souza
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 40
> > ++
Hi all,
On Thu, 22 Mar 2018 13:21:29 +1100 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm-intel tree got a conflict in:
>
> drivers/gpu/drm/i915/gvt/scheduler.c
>
> between commit:
>
> fa3dd623e559 ("drm/i915/gvt: keep oa config in shadow ctx")
>
> from Linus' tree and c
Hi all,
On Thu, 15 Mar 2018 14:14:25 +1100 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> sound/pci/hda/hda_intel.c
>
> between commits:
>
> 1ba8f9d30817 ("ALSA: hda: Add a power_save blacklist")
> 40088dc4e1ea ("ALSA: hda - Revert power
Hi all,
On Tue, 20 Mar 2018 12:08:41 +1100 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> drivers/gpu/drm/sun4i/sun4i_tcon.h
>
> between commit:
>
> e742a17cd360 ("drm/sun4i: tcon: Reduce the scope of the LVDS error a bit")
>
> from Linus
== Series Details ==
Series: drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams
(rev4)
URL : https://patchwork.freedesktop.org/series/39979/
State : success
== Summary ==
Series 39979v4 drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc
diagrams
https://patch
== Series Details ==
Series: series starting with [1/2] drm/simple-kms-helper: Plumb plane state to
the enable hook
URL : https://patchwork.freedesktop.org/series/40514/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup 2x-wf_vblank-ts-check-interruptible:
On Fri, 2018-03-23 at 00:16 +, Souza, Jose wrote:
> On Thu, 2018-03-22 at 16:43 -0700, Pandiyan, Dhinakaran wrote:
> >
> >
> > On Thu, 2018-03-22 at 16:27 -0700, Rodrigo Vivi wrote:
> > > On Thu, Mar 22, 2018 at 02:48:47PM -0700, José Roberto de Souza
> > > wrote:
> > > > This will be help
On Thu, 2018-03-22 at 16:15 -0700, Rodrigo Vivi wrote:
> On Thu, Mar 22, 2018 at 02:48:44PM -0700, José Roberto de Souza
> wrote:
> > This value do not change overtime so better cache it than
> > fetch it every PSR enable.
> >
> > Signed-off-by: José Roberto de Souza
> > Cc: Dhinakaran Pandiyan
On Thu, 2018-03-22 at 16:43 -0700, Pandiyan, Dhinakaran wrote:
>
>
> On Thu, 2018-03-22 at 16:27 -0700, Rodrigo Vivi wrote:
> > On Thu, Mar 22, 2018 at 02:48:47PM -0700, José Roberto de Souza
> > wrote:
> > > This will be helpful to debug what hardware is actually tracking.
> > >
> > > Signed-of
On Thu, Mar 22, 2018 at 05:06:13PM -0700, Souza, Jose wrote:
> On Thu, 2018-03-22 at 16:31 -0700, Rodrigo Vivi wrote:
> > On Thu, Mar 22, 2018 at 02:48:46PM -0700, José Roberto de Souza
> > wrote:
> >
> > please add some justification on why this is useful
>
> Okay something like this should
From: Manasi Navare
This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.
The Voltage swing seqeuence is similar to Cannonlake.
However it has different register definitions and hence
it makes sense to create a separate vswing se
After enabled the WOPCM write-once registers locking status checking,
reloading of the i915 module will fail with modparam enable_guc set to 3
(enable GuC and HuC firmware loading) if the module was originally loaded
with enable_guc set to 1 (only enable GuC firmware loading). This is
because WOPCM
In current code, we only compare the locked WOPCM register values with the
calculated values. However, we can continue loading GuC/HuC firmware if the
locked (or partially locked) values were valid for current GuC/HuC firmware
sizes.
This patch added a new code path to verify whether the locked re
Signed-off-by: Jackie Li
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm
The enable_guc modparam is used to enable/disable GuC/HuC FW uploading
dynamcially during i915 module loading. If WOPCM offset register was locked
without having HUC_LOADING_AGENT_GUC bit set to 1, the module reloading
with both GuC and HuC FW will fail since we need to set this bit to 1 for
HuC FW
This commit introduces the definitions for the ICL clocks and adds the
basic functions to the shared DPLL framework. It adds code for the
Enable and Disable sequences for some PLLs, but it does not have the
code to compute the actual PLL values, which are marked as TODO
comments and should be intro
There's a lot of code for the PLL enabling, so let's first only
introduce the register definitions in order to make patch reviewing a
little easier.
v2: Coding style (Jani).
v3: Preparation for upstreaming.
v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James).
Signed-off-by: Paulo Zano
On Thu, 2018-03-22 at 16:31 -0700, Rodrigo Vivi wrote:
> On Thu, Mar 22, 2018 at 02:48:46PM -0700, José Roberto de Souza
> wrote:
>
> please add some justification on why this is useful
Okay something like this should be fine?
IGT tests could be improved with sink status, knowing for sure th
Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> Hello
>
> Here are some more ICL patches, now with the Combo & MG PLLs, some
> DP/HDMI
> initialization code and a few misc fixes.
>
> Again, the R-B tags already present in some of the patches (including
> those form
> me) were given a
On Thu, Feb 22, 2018 at 12:55:19AM -0300, Paulo Zanoni wrote:
> From: Manasi Navare
>
> On clock recovery this function is called to find out
> the max voltage swing level that we could go.
>
> However gen 9 functions use the old buffer translation tables
> to figure that out. ICL uses different
On Thu, 2018-03-22 at 13:33 +0200, Ville Syrjälä wrote:
> On Thu, Mar 22, 2018 at 01:19:19AM +, Pandiyan, Dhinakaran wrote:
> >
> >
> >
> > On Wed, 2018-03-21 at 21:29 +0200, Ville Syrjälä wrote:
> > > On Wed, Mar 21, 2018 at 07:19:53PM +, Pandiyan, Dhinakaran wrote:
> > > >
> > > >
GuC Address Space and WOPCM Layout diagrams won't be generated correctly by
sphinx build if not using proper reST syntax.
This patch uses reST literal blocks to make sure GuC Address Space and
WOPCM Layout diagrams to be generated correctly, and it also corrects some
errors in the diagram descript
On Thu, 2018-03-22 at 21:08 +, Chris Wilson wrote:
> Quoting Dhinakaran Pandiyan (2018-03-20 22:41:51)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 64ecea80438d..a83d95b1b587 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/dr
On Thu, Mar 22, 2018 at 02:48:48PM -0700, José Roberto de Souza wrote:
> Signed-off-by: José Roberto de Souza
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 40
> -
> drivers/gpu/drm/i915/i915_reg.h | 17 ++
On Thu, 2018-03-22 at 16:27 -0700, Rodrigo Vivi wrote:
> On Thu, Mar 22, 2018 at 02:48:47PM -0700, José Roberto de Souza wrote:
> > This will be helpful to debug what hardware is actually tracking.
> >
> > Signed-off-by: José Roberto de Souza
> > Cc: Dhinakaran Pandiyan
> > Cc: Rodrigo Vivi
Den 22.03.2018 21.27, skrev Ville Syrjala:
From: Ville Syrjälä
mipi_dbi_enable_flush() wants to call the fb->dirty() hook from the
bowels of the .atomic_enable() hook. That prevents us from taking the
plane mutex in fb->dirty() unless we also plumb down the acquire
context.
Instead it seems
On Thu, Mar 22, 2018 at 02:48:46PM -0700, José Roberto de Souza wrote:
please add some justification on why this is useful
> Signed-off-by: José Roberto de Souza
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 54
> ++
Den 22.03.2018 19.49, skrev Ville Syrjälä:
On Thu, Mar 22, 2018 at 05:51:35PM +0100, Noralf Trønnes wrote:
tinydrm is also using plane->fb:
$ grep -r "plane\.fb" drivers/gpu/drm/tinydrm/
drivers/gpu/drm/tinydrm/repaper.c: if (tdev->pipe.plane.fb != fb)
drivers/gpu/drm/tinydrm/mipi-dbi.c:
On Thu, Mar 22, 2018 at 02:48:47PM -0700, José Roberto de Souza wrote:
> This will be helpful to debug what hardware is actually tracking.
>
> Signed-off-by: José Roberto de Souza
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 47
> +
On Thu, Mar 22, 2018 at 02:48:38PM -0700, José Roberto de Souza wrote:
> This is a register to help debug what is in the last SDP VSC
> packet revived by sink.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Rodrigo Vivi
(just looking to 1.4b one, but the versions on the comments seems
Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> From: Arkadiusz Hiler
>
> Start using the new registers for ICL and on.
This patch doesn't make sense at this point of the series since we
don't run this code on ICL. I'll put it at the correct series.
>
> Cc: Manasi Navare
> Cc: Rod
On Thu, Mar 22, 2018 at 02:48:45PM -0700, José Roberto de Souza wrote:
> In the 2 eDP1.4a pannels tested set or not set bit have no effect
> but is better set it and comply with specification.
>
> Signed-off-by: José Roberto de Souza
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
looking at the
On Thu, Mar 22, 2018 at 02:48:37PM -0700, José Roberto de Souza wrote:
> To comply with eDP1.4a this bit should be set when enabling PSR2.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Rodrigo Vivi
> ---
> include/drm/drm_dp_helper.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff -
On Thu, 2018-03-22 at 16:09 -0700, Rodrigo Vivi wrote:
> On Thu, Mar 22, 2018 at 02:48:40PM -0700, José Roberto de Souza
> wrote:
> > Move to only one place the sink requirements that the actual driver
> > needs to enable PSR2.
> >
> > Also intel_psr2_config_valid() is called every time the crtc c
On Thu, Mar 22, 2018 at 02:48:44PM -0700, José Roberto de Souza wrote:
> This value do not change overtime so better cache it than
> fetch it every PSR enable.
>
> Signed-off-by: José Roberto de Souza
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
On Thu, Mar 22, 2018 at 02:48:43PM -0700, José Roberto de Souza wrote:
> Cosmetic change.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 2 files changed, 3 insertions(+), 2 del
On Thu, Mar 22, 2018 at 02:48:40PM -0700, José Roberto de Souza wrote:
> Move to only one place the sink requirements that the actual driver
> needs to enable PSR2.
>
> Also intel_psr2_config_valid() is called every time the crtc config
> is computed, wasting some time every time it was checking f
Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> From: Manasi Navare
>
> This sequence is used to setup voltage swing before enabling MG PHY
> DDI
> as well as for changing the voltage during DisplayPort Link training.
>
> For ICL, there are two types of DDIs. This sequence needs to b
On Thu, Mar 22, 2018 at 02:48:39PM -0700, José Roberto de Souza wrote:
> Without GTC enabled hardware is sending dummy aux frame sync value
> that is not useful to sink do selective update, that is why it also
> require that sink supports and requires the y-coordinate.
>
> So removing everything r
Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> From: Manasi Navare
>
> This is an important part of the DDI initalization as well as
> for changing the voltage during DisplayPort link training.
>
> The Voltage swing seqeuence is similar to Cannonlake.
> However it has different regi
On 22/03/18 11:14, Chris Wilson wrote:
Quoting Antonio Argenziano (2018-03-22 17:32:46)
On 22/03/18 05:42, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-03-22 12:36:58)
On 22/03/2018 11:39, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-03-22 11:17:11)
trigger_reset(fd)
== Series Details ==
Series: series starting with [01/12] drm: Add DP PSR2 sink enable bit
URL : https://patchwork.freedesktop.org/series/40521/
State : failure
== Summary ==
Series 40521v1 series starting with [01/12] drm: Add DP PSR2 sink enable bit
https://patchwork.freedesktop.org/api/1.0/
On 03/22/2018 11:17 AM, Piotr Piórkowski wrote:
If GuC firmware is not available on the system and we load i915 with enable
GuC, then we hit this null pointer dereference issue:
[ 71.098873] BUG: unable to handle kernel NULL pointer dereference at
0008
[ 71.098938] IP: intel_uc_
From: Anusha Srivatsa
Cleanup the testcases by moving the platform checks to a single function.
The earlier version of the path is posted here [1]
v2: Make use of the property enums to get the supported rotations
v3: Move hardcodings to a single function(Ville)
[1]: https://patchwork.freedeskt
== Series Details ==
Series: series starting with [01/12] drm: Add DP PSR2 sink enable bit
URL : https://patchwork.freedesktop.org/series/40521/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3c6c3ba8cde6 drm: Add DP PSR2 sink enable bit
67ced254aa32 drm: Add DP last received PS
Without GTC enabled hardware is sending dummy aux frame sync value
that is not useful to sink do selective update, that is why it also
require that sink supports and requires the y-coordinate.
So removing everything related to aux frame sync, if GTC is enabled
we can bring this back.
Cc: Dhinakar
From: "Souza, Jose"
For Geminilake and Cannonlake+ the Y-coordinate support must be
enabled in PSR2_CTL too.
Spec: 7713 and 7720
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_p
== Series Details ==
Series: series starting with [v2,3/3] HAX: Enable GuC for CI (rev4)
URL : https://patchwork.freedesktop.org/series/40516/
State : failure
== Summary ==
Applying: HAX: Enable GuC for CI
Applying: drm/i915/uc: Fetch uC firmware in init_early
error: Failed to merge in the cha
Move to only one place the sink requirements that the actual driver
needs to enable PSR2.
Also intel_psr2_config_valid() is called every time the crtc config
is computed, wasting some time every time it was checking for
Y coordinate requirement.
This allow us to nuke y_cord_support and some of VS
This is a register to help debug what is in the last SDP VSC
packet revived by sink.
Signed-off-by: José Roberto de Souza
---
include/drm/drm_dp_helper.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 0bac0c7d0dec..91c
Signed-off-by: José Roberto de Souza
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 54 +
1 file changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 16f99
To comply with eDP1.4a this bit should be set when enabling PSR2.
Signed-off-by: José Roberto de Souza
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 62903bae0221..0bac0c7d0dec 100644
--- a/inclu
This will be helpful to debug what hardware is actually tracking.
Signed-off-by: José Roberto de Souza
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 47 +
drivers/gpu/drm/i915/i915_reg.h | 18 ++
2 files c
Signed-off-by: José Roberto de Souza
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 40 -
drivers/gpu/drm/i915/i915_reg.h | 17
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
Sink can support our PSR2 requirements but userspace can request
a resolution that PSR2 hardware do not support, in this case it
was overwritten the PSR2 sink support.
Adding another flag here, this way if requested resolution changed
to a value that PSR2 hardware can handle, PSR2 can be enabled.
This value do not change overtime so better cache it than
fetch it every PSR enable.
Signed-off-by: José Roberto de Souza
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 28
2 files changed, 1
Cosmetic change.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_psr.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c4be6bcd1ef..e660c8
In the 2 eDP1.4a pannels tested set or not set bit have no effect
but is better set it and comply with specification.
Signed-off-by: José Roberto de Souza
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletio
Quoting Mika Kuoppala (2018-03-20 15:17:33)
> Looping through rps frequencies when both min and max are zero
> ends up into an endless loop. This can happen during hardware
> enablement.
>
> Bail out early if rps frequencies are not correctly set yet.
>
> Cc: Chris Wilson
> Signed-off-by: Mika K
Quoting Gustavo A. R. Silva (2018-03-22 18:21:54)
> The checks are misleading and not required [1].
>
> [1] https://lkml.org/lkml/2018/3/19/1792
>
> Addresses-Coverity-ID: 1466017
> Cc: Chris Wilson
> Signed-off-by: Gustavo A. R. Silva
Reviewed-by: Chris Wilson
Zhenyu?
-Chris
On 03/22/2018 01:38 PM, Michał Winiarski wrote:
On Tue, Mar 20, 2018 at 04:18:46PM -0700, Jackie Li wrote:
In current code, we only compare the locked WOPCM register values with the
calculated values. However, we can continue loading GuC/HuC firmware if the
locked (or partially locked) values we
== Series Details ==
Series: series starting with [1/2] drm/simple-kms-helper: Plumb plane state to
the enable hook
URL : https://patchwork.freedesktop.org/series/40514/
State : success
== Summary ==
Series 40514v1 series starting with [1/2] drm/simple-kms-helper: Plumb plane
state to the en
We were fetching uC firmwares in separate uc_init_fw step, while
there is no reason why we can't fetch them during init_early.
This will also simplify upcoming patches, as size of the firmware
may be used for register initialization.
Signed-off-by: Michal Wajdeczko
Cc: Michal Winiarski
Cc: Sagar
On 19/03/18 18:22, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
...
Signed-off-by: Tvrtko Ursulin
---
tests/i915_query.c | 381 +
1 file changed, 381 insertions(+)
diff --git a/tests/i915_query.c b/tests/i915_query.c
index c7de8cbd8371..94
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/
In upcoming patch, we want to perform more actions in early
initialization of the uC. This reordering will help resolve
new dependencies that will be introduced by future patch.
v2: s/i915_gem_load_init/i915_gem_init_early (Chris)
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Tvrtko Ursu
== Series Details ==
Series: series starting with [1/2] drm/simple-kms-helper: Plumb plane state to
the enable hook
URL : https://patchwork.freedesktop.org/series/40514/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e90adeef964f drm/simple-kms-helper: Plumb plane state to the
Quoting Dhinakaran Pandiyan (2018-03-20 22:41:51)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 64ecea80438d..a83d95b1b587 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -125,28 +125,44 @@ void intel_psr_
On Thu, 2018-03-22 at 11:21 +0200, Ville Syrjälä wrote:
> On Thu, Mar 22, 2018 at 01:05:24AM +, Pandiyan, Dhinakaran wrote:
> > On Wed, 2018-03-21 at 21:48 +0200, Ville Syrjälä wrote:
> > > On Tue, Mar 20, 2018 at 03:41:51PM -0700, Dhinakaran Pandiyan wrote:
> > > > Timestamps are useful for
Quoting Michal Wajdeczko (2018-03-22 20:36:58)
> We were fetching uC firmwares in separate uc_init_fw step, while
> there is no reason why we can't fetch them during init_early.
> This will also simplify upcoming patches, as size of the firmware
> may be used for register initialization.
>
> Signe
Quoting Michal Wajdeczko (2018-03-22 20:36:57)
> In upcoming patch, we want to perform more actions in early
> initialization of the uC. This reordering will help resolve
> new dependencies that will be introduced by future patch.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Tvrt
On Thu, Mar 22, 2018 at 01:33:10PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 22, 2018 at 01:19:19AM +, Pandiyan, Dhinakaran wrote:
> >
> >
> >
> > On Wed, 2018-03-21 at 21:29 +0200, Ville Syrjälä wrote:
> > > On Wed, Mar 21, 2018 at 07:19:53PM +, Pandiyan, Dhinakaran wrote:
> > > >
> >
On Tue, Mar 20, 2018 at 04:18:46PM -0700, Jackie Li wrote:
> In current code, we only compare the locked WOPCM register values with the
> calculated values. However, we can continue loading GuC/HuC firmware if the
> locked (or partially locked) values were valid for current GuC/HuC firmware
> sizes
Quoting Jeff McGee (2018-03-22 19:29:16)
> On Thu, Mar 22, 2018 at 02:30:09PM +, Chris Wilson wrote:
> > Quoting Mika Kuoppala (2018-03-22 14:26:41)
> > > Chris Wilson writes:
> > >
> > > > If we fail to reset the GPU in a timely fashion, dump the GEM trace so
> > > > that we can see what ope
We were fetching uC firmwares in separate uc_init_fw step, while
there is no reason why we can't fetch them during init_early.
This will also simplify upcoming patches, as size of the firmware
may be used for register initialization.
Signed-off-by: Michal Wajdeczko
Cc: Michal Winiarski
Cc: Sagar
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/
In upcoming patch, we want to perform more actions in early
initialization of the uC. This reordering will help resolve
new dependencies that will be introduced by future patch.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i9
== Series Details ==
Series: drm/i915/guc: Fix null pointer dereference when GuC FW is not available
(rev3)
URL : https://patchwork.freedesktop.org/series/40490/
State : success
== Summary ==
Known issues:
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
From: Ville Syrjälä
mipi_dbi_enable_flush() wants to call the fb->dirty() hook from the
bowels of the .atomic_enable() hook. That prevents us from taking the
plane mutex in fb->dirty() unless we also plumb down the acquire
context.
Instead it seems simpler to split the fb->dirty() into a tinydrm
From: Ville Syrjälä
We'll need access to the plane state during .atomic_enable().
Performed with coccinelle:
@r1@
identifier F =~ ".*enable$";
identifier P, CS;
@@
F(
struct drm_simple_display_pipe *P
,struct drm_crtc_state *CS
+ ,struct drm_plane_state *plane_state
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Jeff McGee
> Sent: Thursday, March 22, 2018 12:09 PM
> To: Tvrtko Ursulin
> Cc: Kondapally, Kalyan ; intel-
> g...@lists.freedesktop.org; b...@bwidawsk.net
> Subject: Re: [Intel-gfx] [RFC 0/8] Force preemption
>
> O
== Series Details ==
Series: drm: Eliminate plane->fb/crtc usage for atomic drivers (rev4)
URL : https://patchwork.freedesktop.org/series/40478/
State : failure
== Summary ==
Possible new issues:
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-legacy:
pass -
On Thu, Mar 22, 2018 at 02:30:09PM +, Chris Wilson wrote:
> Quoting Mika Kuoppala (2018-03-22 14:26:41)
> > Chris Wilson writes:
> >
> > > If we fail to reset the GPU in a timely fashion, dump the GEM trace so
> > > that we can see what operations were in flight when the GPU got stuck.
> > >
On Thu, Mar 22, 2018 at 05:41:57PM +, Tvrtko Ursulin wrote:
>
> On 22/03/2018 16:01, Jeff McGee wrote:
> >On Thu, Mar 22, 2018 at 03:57:49PM +, Tvrtko Ursulin wrote:
> >>
> >>On 22/03/2018 14:34, Jeff McGee wrote:
> >>>On Thu, Mar 22, 2018 at 09:28:00AM +, Chris Wilson wrote:
> Quo
Hi Dave,
A few fixes for 4.16. Main thing here is getting getfb to reject
multiplanar fbs. I should have sent some of these before but conference
and traveling got in the way.
Thanks,
Gustavo
drm-misc-fixes-2018-03-22:
Main change is a patch to reject getfb call for multiplanar framebuffers,
th
== Series Details ==
Series: drm/i915/guc: Fix null pointer dereference when GuC FW is not available
(rev3)
URL : https://patchwork.freedesktop.org/series/40490/
State : success
== Summary ==
Series 40490v3 drm/i915/guc: Fix null pointer dereference when GuC FW is not
available
https://patch
On Thu, Mar 22, 2018 at 05:51:35PM +0100, Noralf Trønnes wrote:
> tinydrm is also using plane->fb:
>
> $ grep -r "plane\.fb" drivers/gpu/drm/tinydrm/
> drivers/gpu/drm/tinydrm/repaper.c: if (tdev->pipe.plane.fb != fb)
> drivers/gpu/drm/tinydrm/mipi-dbi.c: if (tdev->pipe.plane.fb != fb)
>
== Series Details ==
Series: drm/i915: Don't spew errors when resetting HDMI scrambling/bit clock
ratio fails (rev4)
URL : https://patchwork.freedesktop.org/series/40461/
State : warning
== Summary ==
Possible new issues:
Test kms_flip:
Subgroup 2x-flip-vs-dpms:
The checks are misleading and not required [1].
[1] https://lkml.org/lkml/2018/3/19/1792
Addresses-Coverity-ID: 1466017
Cc: Chris Wilson
Signed-off-by: Gustavo A. R. Silva
---
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/d
== Series Details ==
Series: drm/i915/guc: Fix null pointer dereference when GuC FW is not available
(rev3)
URL : https://patchwork.freedesktop.org/series/40490/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d735ca60e03f drm/i915/guc: Fix null pointer dereference when GuC FW i
On 22 March 2018 at 18:03, Harry Wentland wrote:
> On 2018-03-22 01:54 PM, Emil Velikov wrote:
>> Hi Ville,
>>
>> On 22 March 2018 at 15:22, Ville Syrjala
>> wrote:
>>> From: Ville Syrjälä
>>>
>>> I really just wanted to fix i915 to re-enable its planes afer load
>>> detection (a two line patch
== Series Details ==
Series: series starting with [1/2] drm/i915/cnl: Implement
WaProgramMgsrForCorrectSliceSpecificMmioReads
URL : https://patchwork.freedesktop.org/series/40503/
State : warning
== Summary ==
Series 40503v1 series starting with [1/2] drm/i915/cnl: Implement
WaProgramMgsrFor
On Thu, 22 Mar 2018 19:17:28 +0100, Piotr Piórkowski
wrote:
If GuC firmware is not available on the system and we load i915 with
enable
GuC, then we hit this null pointer dereference issue:
[ 71.098873] BUG: unable to handle kernel NULL pointer dereference at
0008
[ 71.0
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