On 2/24/2018 4:23 AM, Manasi Navare wrote:
Thanks for the patches. I am working on the DSC support on i915 for eDP/DP
as well. Looking at the patches below, this is specific to VDSC enabling for eDP
panels and not for the external DP.
So please mention that specifically in the cover letter as w
== Series Details ==
Series: drm/i915: add schedule out notification of preempted but completed
request
URL : https://patchwork.freedesktop.org/series/38903/
State : success
== Summary ==
Test kms_sysfs_edid_timing:
pass -> WARN (shard-apl) fdo#100047
Test kms_curs
== Series Details ==
Series: drm/i915: add schedule out notification of preempted but completed
request
URL : https://patchwork.freedesktop.org/series/38903/
State : success
== Summary ==
Series 38903v1 drm/i915: add schedule out notification of preempted but
completed request
https://patchw
On Mon, 2018-02-19 at 10:07 +0100, Maarten Lankhorst wrote:
> Op 16-02-18 om 20:27 schreef Pandiyan, Dhinakaran:
> > On Fri, 2018-02-16 at 08:55 +, Chris Wilson wrote:
> >> Quoting Dhinakaran Pandiyan (2018-02-16 04:33:21)
> >>> Preparing a framebuffer should not require a flush. _post_plane
On Fri, 2018-02-23 at 17:51 -0800, José Roberto de Souza wrote:
> When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> self, so lets use the mutex register that is available in gen9+ to
> avoid concurrent access by hardware and driver.
> Older gen handling will be done separated.
>
== Series Details ==
Series: drm/i915: Add and enable DP AUX CH mutex (rev2)
URL : https://patchwork.freedesktop.org/series/38655/
State : success
== Summary ==
Test kms_flip:
Subgroup modeset-vs-vblank-race:
pass -> FAIL (shard-hsw) fdo#103060
Subgr
There is one corner case missing schedule out notification of the preempted
request. The preempted request is just completed when preemption happen,
then it will be canceled and won't be resubmitted later, GVT-g will lost
the schedule out notification.
Here add schedule out notification if found t
== Series Details ==
Series: series starting with [1/6] drm/i915/skl+: Add and enable DP AUX CH mutex
URL : https://patchwork.freedesktop.org/series/38902/
State : failure
== Summary ==
Series 38902v1 series starting with [1/6] drm/i915/skl+: Add and enable DP AUX
CH mutex
https://patchwork.f
== Series Details ==
Series: drm/i915: Add and enable DP AUX CH mutex (rev2)
URL : https://patchwork.freedesktop.org/series/38655/
State : success
== Summary ==
Series 38655v2 drm/i915: Add and enable DP AUX CH mutex
https://patchwork.freedesktop.org/api/1.0/series/38655/revisions/2/mbox/
Tes
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 199 +++
2 files changed, 96 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
in
Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS.
Signed-off-by: José Roberto de Souza
---
d
Sink device will do a short pulse in HPD line when there is some
PSR/PSR2 error that needs to be handled by source, this is handling
the first and most simples error: DP_PSR_SINK_INTERNAL_ERROR.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 2 ++
drivers/gpu/drm/i9
Sink will interrupt source when it have any problem saving or reading
the remote frame buffer.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_p
As gen < 9 hardware don't have the aux ch mutex, we need to exit PSR
and wait until it is back to inactive state before do any aux ch
transaction.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_dp.c | 8 +++-
drivers/gpu/drm/i915/intel_drv.h | 9 +
drivers/gpu
***
Please do not send review to this patch here, it was sent separated
https://lists.freedesktop.org/archives/intel-gfx/2018-February/156921.html
it is only included here to avoid concurrency access when reading
sink PSR status and errors registers
***
When PSR/PSR2/GTC is enabled hardware can do
When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
self, so lets use the mutex register that is available in gen9+ to
avoid concurrent access by hardware and driver.
Older gen handling will be done separated.
Reference:
https://01.org/sites/default/files/documentation/intel-gfx-p
On Tue, 2018-02-20 at 18:18 -0800, José Roberto de Souza wrote:
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index
v2
- removed the PSR dependency, now getting lock all the times when available
- renamed functions to avoid nested calls
- moved register bits right after the DP_AUX_CH_MUTEX()
- removed 'drm/i915: keep AUX powered while PSR is enabled' Dhinakaran Pandiyan
will sent a better and final version
v3
-
On Tue, 2018-02-20 at 18:18 -0800, José Roberto de Souza wrote:
> Just share the common code in PSR and PSR2.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_psr.c | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i9
On Tue, 2018-02-20 at 18:18 -0800, José Roberto de Souza wrote:
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index f5d7bfb4300
On Fri, 2018-02-23 at 16:59 -0800, Dhinakaran Pandiyan wrote:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> > Missing flips when FBC is enabled with PSR
> > link off/PSR2 deep sleep scenarios.
> >
>
> I am wary of this. Is there a test to compare flip misses before/after
> this wo
On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> Host/Render modifications do not trigger PSR exit
> or Wireless quick capture exit correctly.
>
I don't get this workaround either. The wording indicates frontbuffer
modifications are expected to trigger PSR exit in HW. But we rely on the
d
On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> Missing flips when FBC is enabled with PSR
> link off/PSR2 deep sleep scenarios.
>
I am wary of this. Is there a test to compare flip misses before/after
this workaround? We also have to confirm disabling FBC has the same
effect of not havi
On Fri, Feb 23, 2018 at 09:25:45PM +0530, Gaurav K Singh wrote:
> Get decompression capabilities from DP sink by doing
> DPCD reads of different offsets as per eDP/DP specs.
>
> Signed-off-by: Gaurav K Singh
> ---
> drivers/gpu/drm/i915/intel_dp.c | 167
> +++
On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> WA 0884:bxt:all,cnl:*:A - "When FBC is enabled with eDP PSR,
> the CPU host modify writes may not get updated on the Display
> as expected.
> WA: Write 0x to CUR_SURFLIVE_A with every CPU
> host modify write to trigger PSR exit."
>
>
On Tue, Feb 13, 2018 at 11:26 PM, Rodrigo Vivi wrote:
> From: Andy Lutomirski
>
> +
> + dev_priv->psr.activate_timer.expires = jiffies - 1;
That can't possibly be okay.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.free
On Fri, Feb 23, 2018 at 09:25:44PM +0530, Gaurav K Singh wrote:
> For Vesa Display Stream compression, defining structures for
> compression capabilities to be stored in encoder.
>
> Signed-off-by: Gaurav K Singh
> ---
> drivers/gpu/drm/i915/i915_drv.h | 125
> +
On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> It is a fact that scheduled work is now improved.
>
> But it is also a fact that on core platforms that shouldn't
> be needed. We only need to actually wait on VLV/CHV.
>
> The immediate enabling is actually not an issue for the
> HW perspe
According to Spec "Requirement before plane enabling or
configuration change: Disable SAGV if any enabled plane will not
be able to enable watermarks for memory latency >= SAGV block
time, or any transcoder is interlaced. Else, enable SAGV."
Currently we are only enabling and disabling SAGV on ful
"Pandiyan, Dhinakaran" writes:
> On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
>> From: Andy Lutomirski
>>
>> The current PSR code has a two call sites that each schedule delayed
>> work to activate PSR. As far as I can tell, each call site intends
>> to keep PSR inactive for the give
== Series Details ==
Series: drm/i915: Disable SAGV on pre plane update. (rev2)
URL : https://patchwork.freedesktop.org/series/38806/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
According to Spec "Requirement before plane enabling or
configuration change: Disable SAGV if any enabled plane will not
be able to enable watermarks for memory latency >= SAGV block
time, or any transcoder is interlaced. Else, enable SAGV."
Currently we are only enabling and disabling SAGV on ful
Thanks for the patches. I am working on the DSC support on i915 for eDP/DP
as well. Looking at the patches below, this is specific to VDSC enabling for eDP
panels and not for the external DP.
So please mention that specifically in the cover letter as well.
On Fri, Feb 23, 2018 at 09:25:43PM +0530,
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/psr: New power domain for AUX IO.
URL : https://patchwork.freedesktop.org/series/38892/
State : warning
== Summary ==
Series 38892v1 series starting with [CI,1/6] drm/i915/psr: New power domain for
AUX IO.
https://patchwork.f
== Series Details ==
Series: series starting with [v5,1/2] drm/i915: Move a bunch of
workaround-related code to its own file
URL : https://patchwork.freedesktop.org/series/38891/
State : warning
== Summary ==
Series 38891v1 series starting with [v5,1/2] drm/i915: Move a bunch of
workaround-r
From: "Dhinakaran Pandiyan"
Frontbuffer flush and invalidate call psr, fbc and drrs functions that use
mutexes but they can be called in atomic contexts in the fbdev path. The
point where the spinlocks are acquired is up in the call stack that is not
entirely easy to spot, so annotate with might_
From: "Dhinakaran Pandiyan"
The core already takes care of the delay before retrying. The delay now
changes to (500, 600)us instead of (500 + 1000, 600 + 1500)us.
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: David Weinehall
---
drivers/gpu/drm/i915/intel_dp.c | 8
From: "Dhinakaran Pandiyan"
intel_edp_init_dpcd() is cluttered with PSR specific DPCD checks and
intel_dp.c is huge.
No functional change intended.
v2: Rebased.
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: David Weinehall
Acked-by: Rodrigo Vivi
---
drivers/gpu/drm/i915
From: "Dhinakaran Pandiyan"
PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain
for AUX-A enables DC_OFF well too. This is not required, so add a new
AUX_IO_A domain for AUX-A to allow DC states to remain enabled. Other AUX
channels re-use the existing AUX domains.
v4: Rew
From: "Dhinakaran Pandiyan"
No functional change.
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: David Weinehall
---
drivers/gpu/drm/i915/intel_dp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
ind
From: "Dhinakaran Pandiyan"
The cap check should be specifically for bit 0 instead of any bit.
Cc: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Fixes: 474d1ec4a3d7 ("drm/i915/skl: Enabling PSR2 SU with frame sync")
---
drivers/gpu/drm/i915/intel_psr.c | 2 +-
1 f
== Series Details ==
Series: series starting with [v5,1/2] drm/i915: Move a bunch of
workaround-related code to its own file
URL : https://patchwork.freedesktop.org/series/38891/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Move a bunch of workaround-related cod
This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.
v2: Use intel_ prefix for code that de
There are different kind of workarounds (those that modify registers that
live in the context image, those that modify global registers, those that
whitelist registers, etc...) and they have different requirements in terms
of where they are applied and how. Also, by splitting them apart, it should
== Series Details ==
Series: series starting with [1/6] Revert "drm: Use a flexible array member for
blob property data"
URL : https://patchwork.freedesktop.org/series/38886/
State : success
== Summary ==
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-b-planes:
== Series Details ==
Series: series starting with [1/6] Revert "drm: Use a flexible array member for
blob property data"
URL : https://patchwork.freedesktop.org/series/38886/
State : success
== Summary ==
Series 38886v1 series starting with [1/6] Revert "drm: Use a flexible array
member for
From: Ville Syrjälä
Now that blob->data is void* again we don't need the casts anymore.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c| 3 +--
drivers/gpu/drm/drm_atomic_helper.c | 2 +-
drivers/gpu/drm/drm_edid.c | 3 +--
drivers/gpu/drm/drm_fb_helper.c | 2
From: Ville Syrjälä
Avoid all the sizeof(drm_color_lut) business by using
drm_color_lut_size() to convert the blob length into
number of LUT entries.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff -
From: Ville Syrjälä
Provide a small helper to convert the blob length in bytes
to the number of LUT entries.
Signed-off-by: Ville Syrjälä
---
include/drm/drm_color_mgmt.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index
From: Ville Syrjälä
Now that blob->data is void* again we don't need to cast it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i91
From: Ville Syrjälä
While we want to potentially support multiple different gamma/degamma
LUT sizes we can (and should) at least check that the blob length
is a multiple of the LUT entry size.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c | 15 +++
1 file changed, 1
From: Ville Syrjälä
Using a flexible array for the blob data was a mistake by me. It
forces all users of the blob data to cast blob->data to something
else. void* is clearly superior so let's go back to the original
scheme.
Not a clean revert as the code has moved.
This reverts commit d63f5e6bf
We current have a single for_each_engine() iterator which we use to
generate both a set of uABI engines and a set of physical engines.
Determining what uABI ring-id corresponds to an actual HW engine is
tricky, so pull that out to a library function and introduce
for_each_physical_engine() for case
== Series Details ==
Series: drm/i915/perf: fix b counter register whitelist on haswell
URL : https://patchwork.freedesktop.org/series/38875/
State : warning
== Summary ==
Test drv_suspend:
Subgroup fence-restore-tiled2untiled:
pass -> SKIP (shard-snb)
Test
On 23/02/18 06:04, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix that by sanitizing firmware status as we will use it shortly.
v2: s/reset_prepare/prepare_to_reset (M
== Series Details ==
Series: drm/i915/perf: fix b counter register whitelist on haswell
URL : https://patchwork.freedesktop.org/series/38875/
State : success
== Summary ==
Series 38875v1 drm/i915/perf: fix b counter register whitelist on haswell
https://patchwork.freedesktop.org/api/1.0/series
On Fri, Feb 23, 2018 at 11:26:41AM -0500, Harry Wentland wrote:
> On 2018-02-22 04:42 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The documentation for the ctm matrix suggests a two's complement
> > format, but at least the i915 implementation is using sign-magnitude
> > instead. And
Quoting Mika Kuoppala (2018-02-23 15:18:17)
> Chris Wilson writes:
>
> > Sometimes we need to boost the priority of an in-flight request, which
> > may lead to the situation where the second submission port then contains
> > a higher priority context than the first and so we need to inject a
> >
On 2018-02-22 04:42 PM, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The documentation for the ctm matrix suggests a two's complement
> format, but at least the i915 implementation is using sign-magnitude
> instead. And looks like malidp is doing the same. Change the docs
> to match the current
This register is incorrectly listed as SNB/IVB only in the documentation. It
turns out it's useful for one configuration on HSW (Compute Metrics Basic).
Fixes: f89823c2122 "drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG
interface"
Cc: Stable
Signed-off-by: Lionel Landwerlin
---
drivers/g
== Series Details ==
Series: Enabling VDSC in i915 driver for GLK
URL : https://patchwork.freedesktop.org/series/38874/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK incl
== Series Details ==
Series: series starting with [1/2] drm/i915/uc: Introduce
intel_uc_suspend|resume
URL : https://patchwork.freedesktop.org/series/38867/
State : failure
== Summary ==
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
incomplete -> PASS (shar
Hi,
On 19/01/2018 17:10, Tvrtko Ursulin wrote:
Hi,
On 19/01/2018 16:45, Peter Zijlstra wrote:
On Thu, Jan 18, 2018 at 06:40:07PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
For situations where sysadmins might want to allow different level of
of access control for different PMUs, we
1. Send PPS and enable DSC after decompression is enabled in DP sink
2. Enable DSC in Source before enabling pipe
3. Disabling compression after disabling pipe, but before disabling port
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_vdsc.c | 51 +++
2 f
Below are the things being taken care as part of this patch:
1. Program Picture Parameter Set(PPS) MMIO regs and Rate Control
params regs in DSC Controller.
Depending on the no of VDSC engines, program the above regs.
2. Populate PPS Secondary Data Packet for Sink device
3. Data is send only to Si
For Vesa Display Stream compression, defining structures for
compression capabilities to be stored in encoder.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 125 +++
drivers/gpu/drm/i915/intel_drv.h | 62 +++
include/drm
Below changes are being taken care in this patch:
1. If there is no DSC support from DPCD offset 0x60, just return
2. If DSC support is there, disable decompression in DPCD offset
0x160 during DP encoder disable sequence.
3. If DSC support is there, enable decompression in DPCD offset
0x160 during
Defining all mmio regs from Gen9 onwards to be used
for VDSC programming.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/i915_drv.h | 58 ++
drivers/gpu/drm/i915/i915_reg.h | 448
2 files changed, 506 insertions(+)
diff --git a/drivers/gpu/d
Vesa Display Stream Compression defines Picture Parameter Set(PPS),
which encoders must communicate to decoders. PPS is encapsulated
in 128 bytes(PS0 through PS127). The PPS contains parameters that
the decoder needs to correctly decode pictures. Correct decoding
requires that an identical PPS be u
Get decompression capabilities from DP sink by doing
DPCD reads of different offsets as per eDP/DP specs.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dp.c | 167
1 file changed, 167 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_d
Display manufacturers are turning to higher-resolution displays
to differentiate their products. The increased pixel counts have
required increased bandwidth over the links that drive these displays.
However, advances in physical layer technology have not kept up
with the increases in pixel count
Vesa Display Stream Compression defines Picture Parameter Set(PPS),
which encoders must communicate to decoders. PPS is encapsulated
in 128 bytes(PS0 through PS127). PPS specifies the syntax for DSC
bitstreams.Correct decoding also requires that an identical PPS be
used at the encoder and decoder.
Below changes are there as part of this patch:
1. Adding Rate Control parameters for DSC
2. Compute Rate Control parameters
3. Compute DSC parameters for Picture Parameter Set
4. Adding a new .c file for VDSC operations
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/Makefile | 1 +
== Series Details ==
Series: drm/i915/uc: Start preparing GuC/HuC for reset (rev2)
URL : https://patchwork.freedesktop.org/series/38805/
State : warning
== Summary ==
Test kms_flip:
Subgroup dpms-vs-vblank-race-interruptible:
fail -> PASS (shard-hsw) fdo#103
On Thu, Feb 22, 2018 at 08:10:32PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Collect all the aux ch vfunc assignments into intel_dp_aux_init()
> instead of having it spread around.
>
> Reviewed-by: Chris Wilson
> Reviewed-by: Rodrigo Vivi
> Signed-off-by: Ville Syrjälä
Pushed 1-4
Chris Wilson writes:
> Sometimes we need to boost the priority of an in-flight request, which
> may lead to the situation where the second submission port then contains
> a higher priority context than the first and so we need to inject a
> preemption event. To do so we must always check inside
>
== Series Details ==
Series: series starting with [1/2] drm/i915/uc: Introduce
intel_uc_suspend|resume
URL : https://patchwork.freedesktop.org/series/38867/
State : success
== Summary ==
Series 38867v1 series starting with [1/2] drm/i915/uc: Introduce
intel_uc_suspend|resume
https://patchwor
On Friday 23 February 2018 07:16 PM, Ville Syrjälä wrote:
On Fri, Feb 23, 2018 at 04:40:42PM +0530, Ramalingam C wrote:
This is really making it cleaner.
Reviewed-by: Ramalingam C
On Friday 23 February 2018 02:57 AM, Ville Syrjala wrote:
From: Ville Syrjälä
Let's try to keep the detail
== Series Details ==
Series: drm/i915/uc: Start preparing GuC/HuC for reset (rev2)
URL : https://patchwork.freedesktop.org/series/38805/
State : success
== Summary ==
Series 38805v2 drm/i915/uc: Start preparing GuC/HuC for reset
https://patchwork.freedesktop.org/api/1.0/series/38805/revisions/
Quoting Mika Kuoppala (2018-02-23 14:06:06)
> Chris Wilson writes:
> > static inline bool is_high_priority(struct intel_guc_client *client)
> > {
> > return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
> > @@ -682,15 +687,12 @@ static void guc_dequeue(struct intel_engine_cs
> > *e
On 23/02/2018 11:58, Petri Latvala wrote:
On Fri, Feb 23, 2018 at 11:34:53AM +, Tvrtko Ursulin wrote:
From: Chris Wilson
CPU hotplug, especially CPU0, can be flaky on commodity hardware.
To improve test reliability and reponse times when testing larger runs we
need to handle those cases
We want to use higher level 'uc' functions as the main entry points to
the GuC/HuC code to hide some details and keep code layered.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 6 +++---
drivers/gpu/drm/i915/i915_gem.c | 4 ++-
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
inde
On Fri, Feb 23, 2018 at 09:04:08AM +, Chris Wilson wrote:
> Sometimes we need to boost the priority of an in-flight request, which
> may lead to the situation where the second submission port then contains
> a higher priority context than the first and so we need to inject a
> preemption event.
Chris Wilson writes:
> Sometimes we need to boost the priority of an in-flight request, which
> may lead to the situation where the second submission port then contains
> a higher priority context than the first and so we need to inject a
> preemption event. To do so we must always check inside
>
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix that by sanitizing firmware status as we will use it shortly.
v2: s/reset_prepare/prepare_to_reset (Michel)
don't forget about gem_sanitize path
On Fri, Feb 23, 2018 at 01:52:22PM +, Brian Starkey wrote:
> Hi Ville,
>
> On Thu, Feb 22, 2018 at 11:42:29PM +0200, Ville Syrjala wrote:
> >From: Ville Syrjälä
> >
> >The documentation for the ctm matrix suggests a two's complement
> >format, but at least the i915 implementation is using sig
On Fri, Feb 23, 2018 at 05:19:19AM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/8] drm/i915: Use the correct power domain for
> aux ch (rev3)
> URL : https://patchwork.freedesktop.org/series/38802/
> State : warning
>
> == Summary ==
>
> Test kms_flip_til
Hi Ville,
On Thu, Feb 22, 2018 at 11:42:29PM +0200, Ville Syrjala wrote:
From: Ville Syrjälä
The documentation for the ctm matrix suggests a two's complement
format, but at least the i915 implementation is using sign-magnitude
instead. And looks like malidp is doing the same. Change the docs
t
On Fri, Feb 23, 2018 at 01:33:42PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, February 23, 2018 3:13 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Lin, Johnson ; Shankar, Uma
> >; Sharma, Shashank
On 22/02/18 17:53, Lionel Landwerlin wrote:
+static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_
On Fri, Feb 23, 2018 at 04:40:42PM +0530, Ramalingam C wrote:
> This is really making it cleaner.
>
> Reviewed-by: Ramalingam C
>
>
>
> On Friday 23 February 2018 02:57 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Let's try to keep the details on the AKSV stuff concentrated
> > in
Quoting Chris Wilson (2018-02-22 14:11:54)
> Sometimes we need to boost the priority of an in-flight request, which
> may lead to the situation where the second submission port then contains
> a higher priority context than the first and so we need to inject a
> preemption event. To do so we must a
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 3:13 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Lin, Johnson ; Shankar, Uma
>; Sharma, Shashank
>Subject: [PATCH 4/4] drm/i915: Don't mangle the CTM on pre-HSW
>
>From: Vill
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 3:13 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Lin, Johnson ; Shankar, Uma
>; Sharma, Shashank
>Subject: [PATCH 3/4] drm/i915: Rename pipe CSC to use ilk_ prefix
>
>From: V
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 3:13 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Lin, Johnson ; Shankar, Uma
>; Sharma, Shashank
>Subject: [PATCH 2/4] drm/i915: Remove the pointless 1:1 matrix copy
>
>From:
>-Original Message-
>From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, February 23, 2018 3:12 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: dri-de...@lists.freedesktop.org; Mihail Atanassov
>; Liviu Dudau ; Brian
>Starkey ; Mali DP Maintainers
>; Lin, Johnson ; Shan
On Fri, Feb 23, 2018 at 11:34:53AM +, Tvrtko Ursulin wrote:
> From: Chris Wilson
>
> CPU hotplug, especially CPU0, can be flaky on commodity hardware.
>
> To improve test reliability and reponse times when testing larger runs we
> need to handle those cases better.
>
> Handle failures to of
From: Chris Wilson
CPU hotplug, especially CPU0, can be flaky on commodity hardware.
To improve test reliability and reponse times when testing larger runs we
need to handle those cases better.
Handle failures to off-line a CPU by immediately skipping the test, and
failures to on-line a CPU by
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