== Series Details ==
Series: series starting with [1/2] drm/i915: Add enum aux_ch and clean up the
aux init to use it
URL : https://patchwork.freedesktop.org/series/38744/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b28837aa5cbe drm/i915: Add enum aux_ch and clean up the aux
We current have a single for_each_engine() iterator which we use to
generate both a set of uABI engines and a set of physical engines.
Determining what uABI ring-id corresponds to an actual HW engine is
tricky, so pull that out to a library function and introduce
for_each_physical_engine() for case
Quoting Tvrtko Ursulin (2018-02-22 06:07:32)
> From: Tvrtko Ursulin
>
> Place context in/out hooks into the GuC backend, when contexts are
> assigned to ports, and removed from them, in order to be able to
> provide engine busy stats in GuC mode.
>
> Signed-off-by: Tvrtko Ursulin
> Testcase: ig
== Series Details ==
Series: drm/i915: GuC test run (rev4)
URL : https://patchwork.freedesktop.org/series/38615/
State : failure
== Summary ==
Test kms_flip:
Subgroup modeset-vs-vblank-race:
fail -> PASS (shard-hsw) fdo#103060 +1
Test perf:
Subgroup
On Wed, 2018-02-21 at 23:28 -0800, Dhinakaran Pandiyan wrote:
> From: Ville Syrjälä
>
> Since we no longer have a 1:1 correspondence between ports and AUX
> channels, let's give AUX channels their own enum. Makes it easier
> to tell the apples from the oranges, and we get rid of the
> port E AUX
PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain
for AUX-A enables DC_OFF well too. This is not required, so add a new
AUX_IO_A domain for AUX-A to allow DC states to remain enabled. Other AUX
channels re-use the existing AUX domains as they do need power well 2.
v2: Add
From: Ville Syrjälä
Since we no longer have a 1:1 correspondence between ports and AUX
channels, let's give AUX channels their own enum. Makes it easier
to tell the apples from the oranges, and we get rid of the
port E AUX power domain FIXME since we now derive the power domain
from the actual AU
On Tue, 2018-02-20 at 11:31 -0800, Rodrigo Vivi wrote:
> On Tue, Feb 20, 2018 at 07:05:22PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Since we no longer have a 1:1 correspondence between ports and AUX
> > channels, let's give AUX channels their own enum. Makes it easier
> > t
Quoting Zhenyu Wang (2018-02-22 03:13:19)
> On 2018.02.20 20:15:22 +, Chris Wilson wrote:
> > Quoting Zhenyu Wang (2018-02-14 05:28:27)
> > >
> > > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for
> > > chinese new year, team would take one week off at least, so like to
> > >
On Tue, 2018-02-20 at 21:00 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Just store function pointers that give us the correct register offsets
> instead of storing the register offsets themselves. Slightly less
> efficient perhaps but saves a few bytes and better matches how we do
> th
Quoting Rodrigo Vivi (2018-02-22 04:26:29)
> Hi guys,
>
> looking at gem_eio&in_flight* for gen9 on:
> https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html
>
> run 246 x 247
> pure v4.16-rc2 x our fixes
>
> would any of 2 patches explain:
>
> drm/i915: Clear the in-use marker on execbu
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
(rev2)
URL : https://patchwork.freedesktop.org/series/38717/
State : success
== Summary ==
Series 38717v2 series starting with [1/2] drm/i915/guc: Support engine busy
stats
https://patchwork.freed
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
(rev2)
URL : https://patchwork.freedesktop.org/series/38717/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
690dfe054013 drm/i915/guc: Support engine busy stats
-:33: WARNING: line o
Looks good to me. Few cosmetic changes suggested below. With those
addressed:
Reviewed-by: Sagar Arun Kamble
On 2/22/2018 5:05 AM, Oscar Mateo wrote:
In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Als
On Tue, 2018-02-20 at 19:05 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Since we no longer have a 1:1 correspondence between ports and AUX
> channels, let's give AUX channels their own enum. Makes it easier
> to tell the apples from the oranges, and we get rid of the
> port E AUX pow
== Series Details ==
Series: drm/i915: GuC test run (rev4)
URL : https://patchwork.freedesktop.org/series/38615/
State : success
== Summary ==
Series 38615v4 drm/i915: GuC test run
https://patchwork.freedesktop.org/api/1.0/series/38615/revisions/4/mbox/
Test kms_pipe_crc_basic:
Subgro
From: Tvrtko Ursulin
Place context in/out hooks into the GuC backend, when contexts are
assigned to ports, and removed from them, in order to be able to
provide engine busy stats in GuC mode.
Signed-off-by: Tvrtko Ursulin
Testcase: igt/perf_pmu/busy-accuracy-*-*
---
drivers/gpu/drm/i915/intel_
On Wednesday 14 February 2018 08:45 PM, Winkler, Tomas wrote:
This patch defines the hdcp2.2 protocol messages for the
HDCP2.2 authentication.
Signed-off-by: Ramalingam C
---
include/drm/drm_hdcp.h | 226
+
1 file changed, 226 insertions(+)
On Thursday 15 February 2018 01:10 AM, Jani Nikula wrote:
On Wed, 14 Feb 2018, "Winkler, Tomas" wrote:
This patch defines the hdcp2.2 protocol messages for the
HDCP2.2 authentication.
Signed-off-by: Ramalingam C
---
include/drm/drm_hdcp.h | 226
On Wednesday 14 February 2018 08:15 PM, Winkler, Tomas wrote:
This one is already upstream
Thanks for pointing that out. I will drop this patch.
--Ram
Thanks
Tomas
From: Tomas Winkler
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/hw-me-regs.h | 2 ++
drivers/misc/mei/pci-me.c
Hi guys,
looking at gem_eio&in_flight* for gen9 on:
https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html
run 246 x 247
pure v4.16-rc2 x our fixes
would any of 2 patches explain:
drm/i915: Clear the in-use marker on execbuf failure
drm/i915: Fix rsvd2 mask when out-fence is returned
An
== Series Details ==
Series: ICL PLLs, DP/HDMI and misc display
URL : https://patchwork.freedesktop.org/series/38737/
State : warning
== Summary ==
Series 38737v1 ICL PLLs, DP/HDMI and misc display
https://patchwork.freedesktop.org/api/1.0/series/38737/revisions/1/mbox/
Test gem_exec_suspend:
== Series Details ==
Series: ICL PLLs, DP/HDMI and misc display
URL : https://patchwork.freedesktop.org/series/38737/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
176365bcdda2 drm/i915/icl: add definitions for the ICL PLL registers
-:87: CHECK: Prefer using the BIT macro
#87:
And the DDI_A_4_LANES bit from DDI_BUF_CTL doesn't even exist anymore.
This commit prevents us from auto picking a maximum of 2 lanes, which
makes some panels useless by rejecting their only native mode.
Thanks to Manasi for the help debugging this one.
v2: Typo fix (Rodrigo).
Cc: Manasi Navare
From: Manasi Navare
On clock recovery this function is called to find out
the max voltage swing level that we could go.
However gen 9 functions use the old buffer translation tables
to figure that out. ICL uses different set of tables for eDP
and DP for both Combo and MG PHY ports. This patch ad
From: James Ausmus
These fields have been deprecated and moved in ICL+. Stop setting the
bits.
They have moved to GAMMA_MODE and CSC_MODE, respectively. This patch
is just to stop incorrectly setting bits in PLANE_COLOR_CTL while
we're waiting for the new replacement functionality to be done.
v
This implements the "MG PLL Programming" sequence from our spec. The
biggest problem was that the spec assumes real numbers, so we had to
adjust some numbers and alculations due to the fact that the Kernel
prefers to deal with integers.
I recommend grabbing some coffee, a pen and paper before revi
Hello
Here are some more ICL patches, now with the Combo & MG PLLs, some DP/HDMI
initialization code and a few misc fixes.
Again, the R-B tags already present in some of the patches (including those form
me) were given a long time ago, so they need to be re-issued due to the
rebasing.
Thanks,
Pa
From: Dhinakaran Pandiyan
Extend enum hpd_pin to port F so that we can start using this for ICL.
v2: Rebase.
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_hotplug.c | 3 +++
2 files changed, 4
From: Manasi Navare
This sequence is used to setup voltage swing before enabling MG PHY DDI
as well as for changing the voltage during DisplayPort Link training.
For ICL, there are two types of DDIs. This sequence needs to be used
for MG PHY DDI which is ports C-F.
v5 (from Paulo):
* Checkpatch
From: Arkadiusz Hiler
Start using the new registers for ICL and on.
Cc: Manasi Navare
Cc: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
Signed-off-by: Arkadiusz Hiler
---
drivers/gpu/drm/i915/intel_ddi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i
From: Nabendu Maiti
Gen11 supports upto 5k source scaling
v2: Re-factoring of code as per review
v3: Corrected max Vertical size and indentation
v4: Added max Vertical dst size in same patch
Signed-off-by: Nabendu Maiti
---
drivers/gpu/drm/i915/intel_display.c | 11 +++
drivers/gpu/dr
This commit introduces the definitions for the ICL clocks and adds the
basic functions to the shared DPLL framework. It adds code for the
Enable and Disable sequences for some PLLs, but it does not have the
code to compute the actual PLL values, which are marked as TODO
comments and should be intro
HDMI mode DPLL programming on ICL is the same as CNL, so just reuse
the CNL code.
v2:
- Properly detect HDMI crtcs.
- Rebase after changes to the cnl function (clock * 1000).
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 34 +++---
1 file
From: Manasi Navare
This is an important part of the DDI initalization as well as
for changing the voltage during DisplayPort link training.
The Voltage swing seqeuence is similar to Cannonlake.
However it has different register definitions and hence
it makes sense to create a separate vswing se
There's a lot of code for the PLL enabling, so let's first only
introduce the register definitions in order to make patch reviewing a
little easier.
v2: Coding style (Jani).
v3: Preparation for upstreaming.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 149 ++
From: Manasi Navare
This table is used for voltage swing programming sequence during DDI
Buffer initialization for MG PHY DDI Buffers on Icelake.
v2 (from Paulo):
* Fix white space issues.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Reviewed-by: Paulo Zanoni
Signed-off-by: Manasi Navare
Signed-off-by:
Just use the hardcoded tables provided by our spec.
v2: Rebase.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 86 ++-
1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/
From: Manasi Navare
These tables are used on voltage vswing sequence initialization on
Icelake.
The swing_sel on the spec's table is defined in a 4 bits binary like
1010. However the register bits are split in upper 1 bit swing_sel
and lower 3 bits swing sel.
In this table here we store this v
From: Manasi Navare
On Icelake platform, MG PHY is used when operating in DP alternate
mode or the legacy HDMI or DP modes. DDI Ports C, D, E, F are MG PHY
DDI ports on ICL.
This patch adds the necessary voltage swing programming related
register definitions and macros for MG PHY DDI ports.
v4
From: Manasi Navare
This patch defines register definitions required for ICL voltage
vswing programming for Combo PHY DDI Ports. It uses the same bit
definitions and macros as the CNL voltage swing sequences.
v7:
* Kill _MMIIO_PORT2_LN (Paulo)
v6:
* Replace some spaces with TAB (Paulo)
v5:
* Use
On 2018.02.20 20:15:22 +, Chris Wilson wrote:
> Quoting Zhenyu Wang (2018-02-14 05:28:27)
> >
> > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for
> > chinese new year, team would take one week off at least, so like to
> > send this out before vacation. This has one to fix GT
> -Original Message-
> From: Juha-Pekka Heikkila [mailto:juhapekka.heikk...@gmail.com]
> Sent: Wednesday, February 21, 2018 7:52 PM
> To: Srinivas, Vidya ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
> format for primary pla
== Series Details ==
Series: drm/i915/hsw: add missing disabled EUs registers reads (rev4)
URL : https://patchwork.freedesktop.org/series/38441/
State : success
== Summary ==
Test kms_flip:
Subgroup 2x-dpms-vs-vblank-race:
pass -> FAIL (shard-hsw) fdo#103060
Hi Ville,
I already resubmit the patch https://patchwork.freedesktop.org/patch/205823/
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73f730c..b9068bd1943f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -655,18 +6
On 20/02/18 07:37, Mika Kuoppala wrote:
From: Tvrtko Ursulin
Show GEN11 specific interrupt registers in debugfs
v2: Update for POR changes. (Daniele Ceraolo Spurio)
v3: get runtime pm ref. unify common parts with gen8 (Daniele)
Cc: Ceraolo Spurio, Daniele
Signed-off-by: Tvrtko Ursulin
Sig
== Series Details ==
Series: drm/i915: Scanout fence fixes/cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/38714/
State : success
== Summary ==
Test drv_suspend:
Subgroup fence-restore-untiled:
skip -> PASS (shard-snb)
Test kms_flip:
S
== Series Details ==
Series: ICL GEM enabling (v2) (rev6)
URL : https://patchwork.freedesktop.org/series/38174/
State : failure
== Summary ==
Applying: drm/i915/icl: Add the ICL PCI IDs
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_pci.c
M include/drm/i
On Wed, Feb 21, 2018 at 09:43:55PM +, Chris Wilson wrote:
> Quoting James Xiong (2018-02-20 17:48:03)
> > From: "Xiong, James"
> >
> > With gem_reuse enabled, when a buffer size is different than
> > the sizes of buckets, it is aligned to the next bucket's size,
> > which means about 25% more
In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
each VDBOX and VEBOX has its own power well, which only exist if the related
engine exists in the HW.
Unfortunately, we have a Catch-22 situation going
Nice, this is a no-brainer
Reviewed-by: Lyude Paul
On Wed, 2018-02-21 at 10:28 +0100, Maarten Lankhorst wrote:
> Moving the check upwards will mean we we no longer have to add planes
> and connectors manually, because everything is handled correctly by
> drm_atomic_helper_check_modeset() as inte
On Wed, Feb 21, 2018 at 01:12:08PM -0800, Souza, Jose wrote:
> On Wed, 2018-02-21 at 12:45 -0800, Rodrigo Vivi wrote:
> > On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza
> > wrote:
> > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > > self, so lets use the
Quoting Ville Syrjala (2018-02-21 16:02:35)
> From: Ville Syrjälä
>
> Currently the FBC code doesn't handle the 90/270 degree rotated case
> correctly. We would need the GTT tracking to monitor the fence on the
> normal GTT view (the rotated view doesn't even have a fence). Not quite
> sure how w
Quoting Ville Syrjala (2018-02-21 16:02:34)
> From: Ville Syrjälä
>
> We've replicated the fb pin/unpin code in a few places. Pull it into
> convenint helpers.
>
> Slight change in locking behaviour as intel_cleanup_plane_fb() now
> grab struct_mutex unconditionally.
>
> v2: Change the locking
Quoting Ville Syrjala (2018-02-21 16:02:33)
> From: Ville Syrjälä
>
> As only a subset of primary planes are FBC capable there's no need
> to waste fences on all of them. So let's skip the fence if the plane
> isn't even fbc capable.
>
> In the future we might extend this to skip the fence even
Quoting Ville Syrjala (2018-02-21 17:31:01)
> From: Ville Syrjälä
>
> Let's record the information whether a plane can do fbc or not under
> struct inte_plane.
>
> v2: Rebase due to i9xx_plane_id
> Handle BDW/HSW correctly
> v3: Move inte_fbc_init() back since we depend on it happening
>
From: Ville Syrjälä
Currently we pin a fence on every plane doing tiled scanout. The
number of planes we have available is fast apporaching the number
of fences so we really should stop wasting them. Only FBC needs
the fence on gen4+, so let's use fences only for the primary planes
on those platf
Quoting Ville Syrjala (2018-02-21 18:48:07)
> From: Ville Syrjälä
>
> Currently we pin a fence on every plane doing tiled scanout. The
> number of planes we have available is fast apporaching the number
> of fences so we really should stop wasting them. Only FBC needs
> the fence on gen4+, so let
Quoting Ville Syrjala (2018-02-21 16:02:30)
> From: Ville Syrjälä
>
> Gen2/3 display engine depends on the fence for tiled scanout. So if we
> fail to get a fence fail the entire operation.
>
> Cc: Chris Wilson
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 +
Quoting James Xiong (2018-02-20 17:48:03)
> From: "Xiong, James"
>
> With gem_reuse enabled, when a buffer size is different than
> the sizes of buckets, it is aligned to the next bucket's size,
> which means about 25% more memory than the requested is allocated
> in the worst senario. For exampl
Quoting Michel Thierry (2018-02-21 17:25:54)
> On 21/02/18 05:32, Chris Wilson wrote:
> > Load an empty ringbuffer for preemption, ignoring the lite-restore
> > workaround as we know the preempt context is always idle before preemption.
> >
>
> True, injecting the preempt context shouldn't cause
Quoting Joonas Lahtinen (2018-02-21 18:40:51)
> Quoting Chris Wilson (2018-02-21 11:56:36)
> > We want to de-emphasize the link between the request (dependency,
> > execution and fence tracking) from GEM and so rename the struct from
> > drm_i915_gem_request to i915_request. That is we may implemen
== Series Details ==
Series: drm/i915/hsw: add missing disabled EUs registers reads (rev4)
URL : https://patchwork.freedesktop.org/series/38441/
State : success
== Summary ==
Series 38441v4 drm/i915/hsw: add missing disabled EUs registers reads
https://patchwork.freedesktop.org/api/1.0/series/
== Series Details ==
Series: drm/i915/execlists: Move the GEM_BUG_ON context matches CSB later
URL : https://patchwork.freedesktop.org/series/38709/
State : failure
== Summary ==
Test kms_plane_multiple:
Subgroup legacy-pipe-b-tiling-none:
skip -> PASS (shar
On Wed, 2018-02-21 at 12:45 -0800, Rodrigo Vivi wrote:
> On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza
> wrote:
> > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > self, so lets use the mutex register that is available in gen9+ to
> > avoid concurrent acces
== Series Details ==
Series: drm/atomic: Call ww_acquire_done after drm_modeset_lock_all
URL : https://patchwork.freedesktop.org/series/38711/
State : warning
== Summary ==
Test kms_flip:
Subgroup 2x-plain-flip-ts-check:
pass -> FAIL (shard-hsw) fdo#100368 +
Quoting Tvrtko Ursulin (2018-02-21 16:25:34)
>
> On 21/02/2018 14:45, Chris Wilson wrote:
> > We current have a single for_each_engine() iterator which we use to
> > generate both a set of uABI engines and a set of physical engines.
> > Determining what uABI ring-id corresponds to an actual HW eng
On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza wrote:
> When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> self, so lets use the mutex register that is available in gen9+ to
> avoid concurrent access by hardware and driver.
>
> Reference:
> https://01.org/sites
It turns out that HSW has a register that tells us how many EUs are
disabled per half-slice (roughly a similar notion to subslice). We
didn't read those registers so far as most userspace drivers didn't
need those values prior to Gen8, but an internal library would like to
have access to this.
Sin
We current have a single for_each_engine() iterator which we use to
generate both a set of uABI engines and a set of physical engines.
Determining what uABI ring-id corresponds to an actual HW engine is
tricky, so pull that out to a library function and introduce
for_each_physical_engine() for case
It turns out that HSW has a register that tells us how many EUs are
disabled per half-slice (roughly a similar notion to subslice). We
didn't read those registers so far as most userspace drivers didn't
need those values prior to Gen8, but an internal library would like to
have access to this.
Sin
== Series Details ==
Series: drm/i915: Scanout fence fixes/cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/38714/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ec43511e598e drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout
a686f373992f drm/i915: Onl
On Wed, 21 Feb 2018 20:48:07 +0200
Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we pin a fence on every plane doing tiled scanout. The
> number of planes we have available is fast apporaching the number
> of fences so we really should stop wasting them. Only FBC needs
> the fence on
Hi Dave,
A delicious collection of fixes and features for you this week. The backlight
helpers have been picked up by Lee Jones in the backlight tree, so hopefully
no fireworks there. Everything else is business as usual.
drm-misc-next-2018-02-21:
drm-misc-next for 4.17:
Cross-subsystem Changes:
Quoting Chris Wilson (2018-02-21 14:45:21)
> diff --git a/tests/gem_sync.c b/tests/gem_sync.c
> index d70515ea..788fafc3 100644
> --- a/tests/gem_sync.c
> +++ b/tests/gem_sync.c
> @@ -86,23 +86,9 @@ sync_ring(int fd, unsigned ring, int num_children, int
> timeout)
> int num_engines = 0;
>
== Series Details ==
Series: drm/i915/execlists: Add a GEM_TRACE to show when the context is
completed
URL : https://patchwork.freedesktop.org/series/38707/
State : success
== Summary ==
Test kms_atomic_transition:
Subgroup 1x-modeset-transitions-nonblocking-fencing:
f
On Wed, Feb 21, 2018 at 04:23:31PM +0100, Maarten Lankhorst wrote:
> After we acquired all generic modeset locks in drm_modeset_lock_all, it's
> unsafe acquire any other so just mark acquisition as done.
>
> Atomic drivers shouldn't use drm_modeset_lock_all.
>
> Signed-off-by: Maarten Lankhorst
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
URL : https://patchwork.freedesktop.org/series/38717/
State : failure
== Summary ==
Series 38717v1 series starting with [1/2] drm/i915/guc: Support engine busy
stats
https://patchwork.freedesktop.o
== Series Details ==
Series: drm/i915: Scanout fence fixes/cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/38714/
State : success
== Summary ==
Series 38714v3 drm/i915: Scanout fence fixes/cleanups
https://patchwork.freedesktop.org/api/1.0/series/38714/revisions/3/mbox/
Test ge
On 2018-02-21 01:36 PM, Daniel Vetter wrote:
> On Wed, Feb 21, 2018 at 04:23:31PM +0100, Maarten Lankhorst wrote:
>> After we acquired all generic modeset locks in drm_modeset_lock_all, it's
>> unsafe acquire any other so just mark acquisition as done.
>>
>> Atomic drivers shouldn't use drm_modeset
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
URL : https://patchwork.freedesktop.org/series/38717/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dc87ce86e08d drm/i915/guc: Support engine busy stats
-:33: WARNING: line over 80 c
Quoting Chris Wilson (2018-02-21 11:56:36)
> We want to de-emphasize the link between the request (dependency,
> execution and fence tracking) from GEM and so rename the struct from
> drm_i915_gem_request to i915_request. That is we may implement the GEM
> user interface on top of requests, but the
Quoting Lionel Landwerlin (2018-02-16 17:31:01)
> +static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> + struct intel_device_info *info = mkwrite_device_info(dev_priv);
> + struct sseu_dev_info *sseu = &info->sseu;
> + u32 fuse1;
> +
> + /*
> +
On Tue, Feb 20, 2018 at 11:39:08PM -0800, Dhinakaran Pandiyan wrote:
> No code changes, fixes doc build warnings and polish some doc text.
>
> Reported-by: Daniel Vetter
> Cc: Rodrigo Vivi
> Cc: Daniel Vetter
> Signed-off-by: Dhinakaran Pandiyan
Thanks for the quick follow-up. Patch applied.
== Series Details ==
Series: lib: Skip aliased bsd ABI ring if bsd2 is available (rev2)
URL : https://patchwork.freedesktop.org/series/38690/
State : warning
== Summary ==
IGT patchset tested on top of latest successful build
960e55a87d7b7d7385063e37cc9f281df2be8037 igt/gem_ctx_isolation: Chec
== Series Details ==
Series: drm/i915: Scanout fence fixes/cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/38714/
State : failure
== Summary ==
Series 38714v2 drm/i915: Scanout fence fixes/cleanups
https://patchwork.freedesktop.org/api/1.0/series/38714/revisions/2/mbox/
Test co
Op 21-02-18 om 11:20 schreef Vidya Srinivas:
> This patch series is adding NV12 support for Broxton display after rebasing on
> latest drm-tip.
> Initial series of the patches can be found here:
> https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
>
> Previous revision history:
>
== Series Details ==
Series: drm/i915/execlists: Remove the ring advancement under preemption
URL : https://patchwork.freedesktop.org/series/38698/
State : success
== Summary ==
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-c-frame-sequence:
fail -> PASS (
Hi all,
Mostly fixes in this tag. QA/testing could emphasis on CNL hardware as we're
removing the alpha_support flag for it.
Regards, Joonas
---
The following changes tagged drm-intel-testing-2018-02-21:
drm-intel-next-2018-02-21:
Driver Changes:
- Lift alpha_support protection from Cannonlake
== Series Details ==
Series: drm/i915: Scanout fence fixes/cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/38714/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c4c108df218b drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout
b5042b8f97b3 drm/i915: Onl
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
URL : https://patchwork.freedesktop.org/series/38717/
State : failure
== Summary ==
Series 38717v1 series starting with [1/2] drm/i915/guc: Support engine busy
stats
https://patchwork.freedesktop.o
== Series Details ==
Series: series starting with [1/2] drm/i915/guc: Support engine busy stats
URL : https://patchwork.freedesktop.org/series/38717/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
661f5ef77993 drm/i915/guc: Support engine busy stats
-:33: WARNING: line over 80 c
From: Ville Syrjälä
Let's record the information whether a plane can do fbc or not under
struct inte_plane.
v2: Rebase due to i9xx_plane_id
Handle BDW/HSW correctly
v3: Move inte_fbc_init() back since we depend on it happening
even with i915.disable_display, and populate
fbc->possibl
On 21/02/18 05:32, Chris Wilson wrote:
Load an empty ringbuffer for preemption, ignoring the lite-restore
workaround as we know the preempt context is always idle before preemption.
True, injecting the preempt context shouldn't cause a lite-restore.
And the restriction was to always have Head!
From: Tvrtko Ursulin
With disabled aggressive idling from IGT. To see how shard run fares.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 ++
3 files changed, 3 insertions(+), 4
From: Tvrtko Ursulin
Place context in/out hooks into the GuC backend, when contexts are
assigned to ports, and removed from them, in order to be able to
provide engine busy stats in GuC mode.
Signed-off-by: Tvrtko Ursulin
Testcase: igt/perf_pmu/busy-accuracy-*-*
---
drivers/gpu/drm/i915/intel_
On Wed, 2018-02-21 at 00:59 -0800, Dhinakaran Pandiyan wrote:
> On Tuesday, February 20, 2018 6:23:47 PM PST José Roberto de Souza
> wrote:
> > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it
> > self, so lets use the mutex register that is available in gen9+ to
> > avoid concur
On 2/21/2018 5:50 PM, Michal Wajdeczko wrote:
On Wed, 21 Feb 2018 09:08:08 +0100, Sagar Arun Kamble
wrote:
On 2/21/2018 4:27 AM, Michal Wajdeczko wrote:
Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure")
we believed that we correctly handle all errors encountered duri
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..0e3b237 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,11 @@ static inline bool intel_uc_fw_is_selected(struct
intel_uc_fw *uc_fw)
== Series Details ==
Series: drm/i915/hsw: add missing disabled EUs registers reads (rev2)
URL : https://patchwork.freedesktop.org/series/38441/
State : success
== Summary ==
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank-interruptible:
fail -> PASS (shar
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