So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
index = 3, one of which has been kindly provided to me by Jan Brummer,
where not working with the i915 driver, giving a black screen on the
first modeset.
The problem with at least these Dells is that their VBT defines a MIPI
ASSE
Hi,
On 25-01-18 15:10, Ville Syrjälä wrote:
On Thu, Jan 25, 2018 at 02:37:26PM +0100, Hans de Goede wrote:
So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
index = 3, one of which has been kindly provided to me by Jan Brummer,
where not working with the i915 driver, giving a
== Series Details ==
Series: drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern
URL : https://patchwork.freedesktop.org/series/37148/
State : failure
== Summary ==
Test gem_softpin:
Subgroup noreloc-s4:
fail -> SKIP (shard-snb) fdo#103375
Test kms_flip:
== Series Details ==
Series: drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern
URL : https://patchwork.freedesktop.org/series/37148/
State : success
== Summary ==
Series 37148v1 drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern
https://patchwork.freedesktop.org/api/1.0/series/37148/rev
Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
indirect context wa bb.
References: HSD#1939868
Signed-off-by: Rafael Antognolli
---
drivers/gpu/drm/i915/intel_lrc.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
== Series Details ==
Series: drm/i915/cnp: Properly handle VBT ddc pin out of bounds. (rev5)
URL : https://patchwork.freedesktop.org/series/37060/
State : success
== Summary ==
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
pass -> FAIL (shard
On 24/01/18 09:46, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2018-01-24 17:30:07)
From: Thomas Daniel
Enhanced Execlists is an upgraded version of execlists which supports
up to 8 ports. The lrcs to be submitted are written to a submit queue
(the ExecLists Submission Queue - ELSQ),
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU.
URL : https://patchwork.freedesktop.org/series/37134/
State : failure
== Summary ==
Test kms_flip:
Subgroup dpms-vs-vblank-race:
pass -> FAIL (sh
== Series Details ==
Series: drm/i915: Always update the no_fbc_reason when disabling
URL : https://patchwork.freedesktop.org/series/37139/
State : failure
== Summary ==
Series 37139v1 drm/i915: Always update the no_fbc_reason when disabling
https://patchwork.freedesktop.org/api/1.0/series/371
On Tue, Jan 23, 2018 at 05:05:35PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> Enable SAGV for ICL platform.
>
> Signed-off-by: Mahesh Kumar
Reviewed-by: James Ausmus
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/dr
On Tue, Jan 23, 2018 at 05:05:34PM -0200, Paulo Zanoni wrote:
> It's 10us for gen 11.
>
> Reviewed-by: Mahesh Kumar
> Signed-off-by: Paulo Zanoni
Reviewed-by: James Ausmus
> ---
> drivers/gpu/drm/i915/intel_pm.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git
On Tue, Jan 23, 2018 at 05:05:31PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> This patch adds support to start tracking status of DBUF slices.
> This is foundation to introduce support for enabling/disabling second
> DBUF slice dynamically for ICL.
>
> Signed-off-by: Mahesh Kumar
Revi
On Tue, Jan 23, 2018 at 05:05:33PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
> 11 bits. This patch make changes to use proper mask for ICL+ during
> hardware ddb value readout.
>
> Signed-off-by: Mahesh Kumar
> ---
On Tue, Jan 23, 2018 at 05:05:32PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> ICL has two slices of DBuf, each slice of size 1024 blocks.
> We should not always enable slice-2. It should be enabled only if
> display total required BW is > 12GBps OR more than 1 pipes are enabled.
>
> Cha
On Thu, Jan 25, 2018 at 02:25:24PM -0800, Rodrigo Vivi wrote:
> If the table result is out of bounds on the array map
> there is something really wrong with VBT pin so we don't
> return that vbt_pin, but only return 0 instead.
>
> This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
> Ignor
== Series Details ==
Series: drm/i915/cnp: Properly handle VBT ddc pin out of bounds. (rev5)
URL : https://patchwork.freedesktop.org/series/37060/
State : success
== Summary ==
Series 37060v5 drm/i915/cnp: Properly handle VBT ddc pin out of bounds.
https://patchwork.freedesktop.org/api/1.0/ser
== Series Details ==
Series: series starting with [1/2] lib: Refactor igt_wait() to use library
timers
URL : https://patchwork.freedesktop.org/series/37132/
State : failure
== Summary ==
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> SKIP
Provide the reason why we call intel_fbc_deactivate() so that debugging
issues with FBC being delayed is clearer.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_fbc.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc
On Tue, Jan 23, 2018 at 05:05:30PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> This patch program default values of MBus credit during pipe enable.
>
> Changes since V2:
> - We don't need to do anything when disabling the pipe
> Changes Since V1:
> - Add WARN_ON (Paulo)
> - Remove TOD
On Tue, Jan 23, 2018 at 05:05:29PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> This patch initializes MBus during display initialization.
>
> Changes since V2 (from Paulo):
> - Don't forget to remove the WARN_ON(1) call.
> Changes since V1:
> - Rebase to use function like Macros
>
> R
On Tue, Jan 23, 2018 at 05:05:28PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> This patch introduce MBus control registers and their bit-fields
> MBUS_ABOX_CTL
> MBUS_BBOX_CTL
> MBUS_DBOX_CTL
> MBUS_UBOX_CTL
>
> Changes Since V1:
> - Use function like macros (Paulo)
> - fix copy-paste
On Tue, Jan 23, 2018 at 05:05:27PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar
>
> We don't have planar pixel format support implemented for ICL yet.
> ICL require 2 display planes to be allocated for Planar formats unlike
> previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU.
URL : https://patchwork.freedesktop.org/series/37134/
State : success
== Summary ==
Series 37134v1 series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI
IDs for another SKU
If the table result is out of bounds on the array map
there is something really wrong with VBT pin so we don't
return that vbt_pin, but only return 0 instead.
This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
Ignore VBT request for know invalid DDC pin.")'
Also this properly fixes commi
On Thu, Jan 25, 2018 at 06:25:06PM +, Rodrigo Vivi wrote:
> On Thu, Jan 25, 2018 at 06:07:19PM +, Lucas De Marchi wrote:
> > On Thu, Jan 25, 2018 at 05:52:26PM +0200, Jani Nikula wrote:
> > > On Thu, 25 Jan 2018, Rodrigo Vivi wrote:
> > > > If the table result is out of bounds on the array
On CNP Pin 3 is for misc of Port F usage depending on the
configuration. For CNL that uses Port F, pin 3 is the one.
v2: Make it more generic and update commit message.
Cc: Anusha Srivatsa
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
---
driver
Let's try to simplify this mapping to hpd_pin -> bit
instead using port.
So for CNL with port F where we have this port using
hdp_pin and bits of other ports we don't need to duplicated
the mapping.
But for now this is only a re-org with no functional change
expected.
v2: Add missing lines and nu
We also need to extend this WA to Aux F.
Cc: Dhinakaran Pandiyan
Cc: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
Now let's finish the Port-F support by adding the
proper port F detection, irq and power well support.
v2: Rebase
v3: Use BIT_ULL
v4: Cover missed case on ddi init.
v5: Update commit message.
v6: Rebase on top of display headers rework.
v7: Squash power-well handling related to DDI F to this
p
This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'
But since no Port F was needed so far we don't need to
propagate fixes back there.
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
Reviewed-by: D
On CNP boards that are using DDI F,
bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
the Digital Port F hotplug line when the Digital
Port F hotplug detect input is enabled.
v2: Reuse all existent structure instead of adding a
new HPD_PORT_F pointing to pin of port E.
v3: Use IS_CNL_WITH_PORT_F so w
On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.
There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.
v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Reb
Since when it got introduced with commit '555e38d27317
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.
Since Port F is not used so far we don't need to propagate
Fixes back there.
v2: Reuse _SHIFT definition to avoid co
On CNL SKUs that uses port F, max DP rate is 8.1G for all
ports when we have the elevated voltage (higher than 0.85V).
v2: Make commit message more generic.
v3: Move conditions to a helper to get easier to read. (Ville).
v4: Add a mention to the numerical voltage on commit
message per Manasi
The only difference is that this SKUs has the full
Port A/E split named as Port F.
But since SKUs differences don't matter on the platform
definition group and ids, let's merge all off them together.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v
On Thu, Jan 25, 2018 at 09:37:56PM +, Rodrigo Vivi wrote:
please ignore this one...
now I guess I will have to resend the entire series to avoid
CI confusion... :/
> If the table result is out of bounds on the array map
> there is something really wrong with VBT pin so we don't
> return that
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU. (rev2)
URL : https://patchwork.freedesktop.org/series/37129/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
== Series Details ==
Series: series starting with [1/2] lib: Refactor igt_wait() to use library
timers
URL : https://patchwork.freedesktop.org/series/37132/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
872fd8f21e22a3ca49739b67c47c6665da450dbf tests/kms_c
If the table result is out of bounds on the array map
there is something really wrong with VBT pin so we don't
return that vbt_pin, but only return 0 instead.
This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
Ignore VBT request for know invalid DDC pin.")'
Also this properly fixes commi
Use the timer routines for computing elapsed time from igt_core for
smaller code.
Signed-off-by: Chris Wilson
---
lib/igt_aux.h | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/lib/igt_aux.h b/lib/igt_aux.h
index 02e70126c..48ba7970f 100644
--- a/li
It is taking longer than a couple of seconds for the FBC worker to be
executed after scheduling; and then will take a minimum of a vblank
interval for it activate. So wait longer to reduce the flip flops.
Signed-off-by: Chris Wilson
---
tests/kms_frontbuffer_tracking.c | 2 +-
1 file changed, 1
== Series Details ==
Series: series starting with [01/10] drm/i915/cnl: Add Cannonlake PCI IDs for
another SKU.
URL : https://patchwork.freedesktop.org/series/37129/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK
Since when it got introduced with commit '555e38d27317
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.
Since Port F is not used so far we don't need to propagate
Fixes back there.
v2: Reuse _SHIFT definition to avoid co
Let's try to simplify this mapping to hpd_pin -> bit
instead using port.
So for CNL with port F where we have this port using
hdp_pin and bits of other ports we don't need to duplicated
the mapping.
But for now this is only a re-org with no functional change
expected.
v2: Add missing lines and nu
On CNL SKUs that uses port F, max DP rate is 8.1G for all
ports when we have the elevated voltage (higher than 0.85V).
v2: Make commit message more generic.
v3: Move conditions to a helper to get easier to read. (Ville).
v4: Add a mention to the numerical voltage on commit
message per Manasi
On CNP boards that are using DDI F,
bit 25 (SDE_PORTE_HOTPLUG_SPT) is representing
the Digital Port F hotplug line when the Digital
Port F hotplug detect input is enabled.
v2: Reuse all existent structure instead of adding a
new HPD_PORT_F pointing to pin of port E.
v3: Use IS_CNL_WITH_PORT_F so w
Now let's finish the Port-F support by adding the
proper port F detection, irq and power well support.
v2: Rebase
v3: Use BIT_ULL
v4: Cover missed case on ddi init.
v5: Update commit message.
v6: Rebase on top of display headers rework.
v7: Squash power-well handling related to DDI F to this
p
This was wrong since its introduction on commit '04416108ccea
("drm/i915/cnl: Add registers related to voltage swing sequences.")'
But since no Port F was needed so far we don't need to
propagate fixes back there.
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
Reviewed-by: D
On CNP Pin 3 is for misc of Port F usage depending on the
configuration. For CNL that uses Port F, pin 3 is the one.
v2: Make it more generic and update commit message.
Cc: Anusha Srivatsa
Cc: Lucas De Marchi
Cc: Manasi Navare
Signed-off-by: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
---
driver
We also need to extend this WA to Aux F.
Cc: Dhinakaran Pandiyan
Cc: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
On some Cannonlake SKUs we have a dedicated Aux for port F,
that is only the full split between port A and port E.
There is still no Aux E for Port E, as in previous platforms,
because port_E still means shared lanes with port A.
v2: Rebase.
v3: Add couple missed PORT_F cases on intel_dp.
v4: Reb
The only difference is that this SKUs has the full
Port A/E split named as Port F.
But since SKUs differences don't matter on the platform
definition group and ids, let's merge all off them together.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v
On 1/25/2018 3:24 AM, Chris Wilson wrote:
Load an empty ringbuffer for preemption, ignoring the lite-restore
workaround as we now the preempt context is always idle before preemption.
s/we now/we know/?
Looks ok to me; the restriction is to avoid a lite-restore with
HEAD==TAIL, and as you sai
On Thu, Jan 25, 2018 at 06:07:19PM +, Lucas De Marchi wrote:
> On Thu, Jan 25, 2018 at 05:52:26PM +0200, Jani Nikula wrote:
> > On Thu, 25 Jan 2018, Rodrigo Vivi wrote:
> > > If the table result is out of bounds on the array map
> > > there is something really wrong with VBT pin so we don't
>
Quoting Michel Thierry (2018-01-25 17:49:49)
> On 1/25/2018 3:24 AM, Chris Wilson wrote:
> > CTX_CONTEXT_CONTROL (CTX_SR_CTL) operates as a masked register and so
> > will only apply the bits that are selected by the upper half. In the
> > case of selectively enabling sr inhibit, this may mean the
On Thu, Jan 25, 2018 at 03:52:26PM +, Jani Nikula wrote:
> On Thu, 25 Jan 2018, Rodrigo Vivi wrote:
> > If the table result is out of bounds on the array map
> > there is something really wrong with VBT pin so we don't
> > return that vbt_pin, but only return 0 instead.
> >
> > This basically
On Thu, Jan 25, 2018 at 05:52:26PM +0200, Jani Nikula wrote:
> On Thu, 25 Jan 2018, Rodrigo Vivi wrote:
> > If the table result is out of bounds on the array map
> > there is something really wrong with VBT pin so we don't
> > return that vbt_pin, but only return 0 instead.
> >
> > This basically
Quoting Michel Thierry (2018-01-25 17:49:49)
> On 1/25/2018 3:24 AM, Chris Wilson wrote:
> > CTX_CONTEXT_CONTROL (CTX_SR_CTL) operates as a masked register and so
> > will only apply the bits that are selected by the upper half. In the
> > case of selectively enabling sr inhibit, this may mean the
Quoting Michel Thierry (2018-01-25 17:49:49)
> On 1/25/2018 3:24 AM, Chris Wilson wrote:
> > CTX_CONTEXT_CONTROL (CTX_SR_CTL) operates as a masked register and so
> > will only apply the bits that are selected by the upper half. In the
> > case of selectively enabling sr inhibit, this may mean the
On 1/25/2018 3:24 AM, Chris Wilson wrote:
CTX_CONTEXT_CONTROL (CTX_SR_CTL) operates as a masked register and so
will only apply the bits that are selected by the upper half. In the
case of selectively enabling sr inhibit, this may mean the context keeps
the current setting (so forgetting to save
Em Sex, 2018-01-19 às 16:05 -0800, Rodrigo Vivi escreveu:
> The only difference is that this SKUs has the full
> Port A/E split named as Port F.
>
> But since SKUs differences don't matter on the platform
> definition group and ids, let's merge all off them together.
>
> v2: Really include the PC
== Series Details ==
Series: drm/i915/cnp: Properly handle VBT ddc pin out of bounds. (rev3)
URL : https://patchwork.freedesktop.org/series/37060/
State : failure
== Summary ==
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl) fdo#102254
Test kms_fr
== Series Details ==
Series: drm/i915/cnp: Properly handle VBT ddc pin out of bounds. (rev3)
URL : https://patchwork.freedesktop.org/series/37060/
State : success
== Summary ==
Series 37060v3 drm/i915/cnp: Properly handle VBT ddc pin out of bounds.
https://patchwork.freedesktop.org/api/1.0/ser
== Series Details ==
Series: drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT
sequence
URL : https://patchwork.freedesktop.org/series/37105/
State : failure
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
On Thu, 25 Jan 2018, Rodrigo Vivi wrote:
> If the table result is out of bounds on the array map
> there is something really wrong with VBT pin so we don't
> return that vbt_pin, but only return 0 instead.
>
> This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
> Ignore VBT request for kno
If the table result is out of bounds on the array map
there is something really wrong with VBT pin so we don't
return that vbt_pin, but only return 0 instead.
This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
Ignore VBT request for know invalid DDC pin.")'
Also this properly fixes commi
== Series Details ==
Series: drm/i915/cnp: Properly handle VBT ddc pin out of bounds. (rev2)
URL : https://patchwork.freedesktop.org/series/37060/
State : success
== Summary ==
Series 37060v2 drm/i915/cnp: Properly handle VBT ddc pin out of bounds.
https://patchwork.freedesktop.org/api/1.0/ser
On Thu, 25 Jan 2018, Rodrigo Vivi wrote:
> If the table result is out of bounds on the array map
> there is something really wrong with VBT pin so we don't
> return that vbt_pin, but only return 0 instead.
>
> This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
> Ignore VBT request for kno
If the table result is out of bounds on the array map
there is something really wrong with VBT pin so we don't
return that vbt_pin, but only return 0 instead.
This basically reverts commit 'a8e6f3888b05 ("drm/i915/cnp:
Ignore VBT request for know invalid DDC pin.")'
Also this properly fixes commi
== Series Details ==
Series: drm: Warn if plane/crtc/encoder/connector index exceeds our 32bit
bitmasks (rev3)
URL : https://patchwork.freedesktop.org/series/37058/
State : failure
== Summary ==
Test drv_suspend:
Subgroup fence-restore-untiled-hibernate:
fail ->
On 2018-01-25 08:30 AM, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We use 32bit bitmasks to track planes/crtcs/encoders/connectors.
> Naturally we can only do that if the index of those objects stays
> below 32. Issue a warning whenever we exceed that limit, hopefully
> prompting someone to f
On 25/01/2018 14:32, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-01-25 14:26:53)
On 25/01/2018 13:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-01-25 13:33:32)
- if (engine && ((caps & engine->caps) != caps))
- return -EINVAL;
+ do {
+
== Series Details ==
Series: drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT
sequence
URL : https://patchwork.freedesktop.org/series/37105/
State : success
== Summary ==
Series 37105v1 drm/i915: Fix DSI panels with v1 MIPI sequences without a
DEASSERT sequence
https://patc
Quoting Tvrtko Ursulin (2018-01-25 14:26:53)
>
> On 25/01/2018 13:57, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-01-25 13:33:32)
> >> - if (engine && ((caps & engine->caps) != caps))
> >> - return -EINVAL;
> >> + do {
> >> + engine
On 25/01/2018 13:57, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-01-25 13:33:32)
- if (engine && ((caps & engine->caps) != caps))
- return -EINVAL;
+ do {
+ engine = i915->engine[_VCS(instance)];
+ instance ^= 1;
== Series Details ==
Series: Virtual queue/engine uAPI prototype
URL : https://patchwork.freedesktop.org/series/37103/
State : failure
== Summary ==
Series 37103v1 Virtual queue/engine uAPI prototype
https://patchwork.freedesktop.org/api/1.0/series/37103/revisions/1/mbox/
Test core_auth:
On Thu, Jan 25, 2018 at 02:37:26PM +0100, Hans de Goede wrote:
> So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
> index = 3, one of which has been kindly provided to me by Jan Brummer,
> where not working with the i915 driver, giving a black screen on the
> first modeset.
>
>
Quoting Tvrtko Ursulin (2018-01-25 13:33:32)
> - if (engine && ((caps & engine->caps) != caps))
> - return -EINVAL;
> + do {
> + engine = i915->engine[_VCS(instance)];
> + instance ^= 1;
> + vcs_inst
== Series Details ==
Series: series starting with [1/2] drm/i915/lrc: Clear context restore/save
inhibit flags for new contexts
URL : https://patchwork.freedesktop.org/series/37099/
State : failure
== Summary ==
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
== Series Details ==
Series: drm: Warn if plane/crtc/encoder/connector index exceeds our 32bit
bitmasks (rev3)
URL : https://patchwork.freedesktop.org/series/37058/
State : success
== Summary ==
Series 37058v3 drm: Warn if plane/crtc/encoder/connector index exceeds our
32bit bitmasks
https:/
On 25/01/2018 11:32, Jani Nikula wrote:
On Wed, 24 Jan 2018, Tvrtko Ursulin wrote:
On 24/01/2018 16:23, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-01-24 16:18:15)
From: Tvrtko Ursulin
This series tries to solve a few issues in the current DRM logging code to
primarily make it clearer
So far models of the Dell Venue 8 Pro, with a panel with MIPI panel
index = 3, one of which has been kindly provided to me by Jan Brummer,
where not working with the i915 driver, giving a black screen on the
first modeset.
The problem with at least these Dells is that their VBT defines a MIPI
ASSE
From: Tvrtko Ursulin
Refactoring to enable future patches.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 49 --
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu
From: Tvrtko Ursulin
At execbuf time engine busyness since the last submission is used as basis
for determining where to submit. In case both engines are equally busy,
request is submitted to the same engine as the previous one.
Virtual engine contexts enable engine busy stats on first submissio
From: Tvrtko Ursulin
Virtual context imply the target engine will be picked by the driver.
v2: Disallow legacy execbuf API.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c| 15 ++-
drivers/gpu/drm/i915/i915_gem_context.h| 2 ++
drivers/gpu/drm/i9
From: Chris Wilson
A context encompasses the driver's view of process related state, and
encapsulates the logical GPU state where available. Each context is
currently equivalent to a process in CPU terms. Like with processes,
sometimes the user wants a lighter encapsulation that shares some state
From: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 13 +-
drivers/gpu/drm/i915/i915_gem.c | 9 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 15 ++-
drivers/gpu/drm/i915/i915_gem_context.h | 2 +
drivers/gpu/drm/i915/i915_gem_e
From: Tvrtko Ursulin
Contexts marked as virtual can be load balanced between available engine
instaces. In this trivial implementation there are two important points to
kepp in mind:
1. Best engine is chosen by round-robin on every submission.
Every time context is transferred between engines a
From: Tvrtko Ursulin
We add a per-context, per-engine-class timeline so we are later able to
implement a virtual engine by creating implicit dependencies between
requests submitted to the same engine class.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h
From: Tvrtko Ursulin
To add the knowledge that VCS1 engine does not support HEVC,
we introduce the concept of engine capabilities. These are
flags defined in per-engine class space which can be passed
in during execbuf time. The driver is then able to fail the
execbuf in case of mismatch between
From: Tvrtko Ursulin
Introduce a new way of selecting engines using the engine class
and instance concept.
This is primarily interesting for the VCS engine selection which
is a) currently done via disjoint set of flags, and b) the
current I915_EXEC_BSD flags has different semantics depending on
From: Tvrtko Ursulin
Needed for a following patch.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 38 --
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i91
From: Tvrtko Ursulin
The latest idea on how to load-balance VCS submissions in i915.
This time round we have a concept of submission queues implemented as contexts
which share PPGTT.
Userspace is supposed to create a queue with the virtual flag set to one.
Subsequent submissions to this queue w
From: Ville Syrjälä
We use 32bit bitmasks to track planes/crtcs/encoders/connectors.
Naturally we can only do that if the index of those objects stays
below 32. Issue a warning whenever we exceed that limit, hopefully
prompting someone to fix the problem.
For connectors the issue is a bit more c
On Thu, Jan 25, 2018 at 01:27:27PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 25, 2018 at 10:17:21AM +0100, Maarten Lankhorst wrote:
> > Op 24-01-18 om 22:47 schreef Ville Syrjala:
> > > From: Ville Syrjälä
> > >
> > > We use 32bit bitmasks to track planes/crtcs/encoders/connectors.
> > > Naturally
Quoting Jeff McGee (2018-01-24 23:01:37)
> On Fri, Nov 10, 2017 at 06:14:17PM +, Chris Wilson wrote:
> > Quoting Patchwork (2017-11-10 16:46:14)
> > > == Series Details ==
> > >
> > > Series: series starting with [CI,1/8] drm/i915: Define an engine class
> > > enum for the uABI
> > > URL :
On Wed, Jan 24, 2018 at 06:50:45PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-01-24 18:36:42)
> > From: Ville Syrjälä
> >
> > Add some compile time assrts to the frontbuffer tracking to make sure
> > that we have enough bits per pipe to cover all the planes, and that we
> > have eno
== Series Details ==
Series: series starting with [1/2] drm/i915/lrc: Clear context restore/save
inhibit flags for new contexts
URL : https://patchwork.freedesktop.org/series/37099/
State : success
== Summary ==
Series 37099v1 series starting with [1/2] drm/i915/lrc: Clear context
restore/sa
On Wed, 24 Jan 2018, Tvrtko Ursulin wrote:
> On 24/01/2018 16:23, Chris Wilson wrote:
>> Quoting Tvrtko Ursulin (2018-01-24 16:18:15)
>>> From: Tvrtko Ursulin
>>>
>>> This series tries to solve a few issues in the current DRM logging code to
>>> primarily make it clearer which messages belong to
On Thu, Jan 25, 2018 at 10:17:21AM +0100, Maarten Lankhorst wrote:
> Op 24-01-18 om 22:47 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > We use 32bit bitmasks to track planes/crtcs/encoders/connectors.
> > Naturally we can only do that if the index of those objects stays
> > below 32. Issu
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