On Sun, Dec 24, 2017 at 6:49 AM, Rhys Kidd wrote:
> warning() needs that, which was introduced in a 865a47ca failure path.
>
> Otherwise we get error messages on that failure path like:
> ...
> Program leg found: NO
>
> Meson encountered an error in file overlay/meson.build, line 62, column
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> Since when it got introduced with commit '555e38d27317
> ("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
> was wrong, because Port F bits are far from bits used
> for A to E.
>
> Since Port F is not used so far we don't need t
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> On some Cannonlake SKUs we have a dedicated Aux for port F,
> that is only the full split between port A and port E.
>
> There is still no Aux E for Port E, as in previous platforms,
> because port_E still means shared lanes with port A.
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> SKUs that lacks on the full port F split will just time out
> when touching this power well bits, causing a noisy warn.
Shouldn't be this be squashed with [PATCH 09/11] in that case? Why
introduce a WARN and then fix it.
>
> This macr
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> This was wrong since its introduction on commit '04416108ccea
> ("drm/i915/cnl: Add registers related to voltage swing sequences.")'
>
> But since no Port F was needed so far we don't need to
> propagate fixes back there.
>
Checked agains
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> Some Cannonlake SKUs will come with a full split between
> port A and port E. This will be called port F although it
> is not a 6th port, but only a split.
I am not sure if this is said in this spec.
From to what I can read and understand
On Wed, Dec 20, 2017 at 10:59:57AM +0100, Daniel Vetter wrote:
> On Tue, Dec 19, 2017 at 03:27:31PM -0800, Dongwon Kim wrote:
> > I forgot to include this brief information about this patch series.
> >
> > This patch series contains the implementation of a new device driver,
> > hyper_dmabuf, whic
>> To clarify, the HW will flip between the two GT/IA requests rather than
>> stick to the highest?
Yes, it will flip on Gen9. On Gen8 there was some mechanism (HW) which
flattened that. But it was removed/substituted in Gen9. In Gen10 it was tuned
to close the mentioned issue.
>> Do you know
Quoting Rogozhkin, Dmitry V (2017-12-26 16:39:23)
> Clarification on the issue. Consider that you have a massive load on GT and
> just tiny one on IA. If GT will program the RING frequency to be lower than
> IA frequency, then you will fall into the situation when RING frequency
> constantly tra
Clarification on the issue. Consider that you have a massive load on GT and
just tiny one on IA. If GT will program the RING frequency to be lower than IA
frequency, then you will fall into the situation when RING frequency constantly
transits from GT to IA level and back. Each transition of a R
Quoting Chris Wilson (2017-12-18 21:47:25)
> Quoting Jackie Li (2017-12-18 21:22:08)
> > From: Zhipeng Gong
> >
> > SKL platforms requires a higher ring multiplier when there's massive
> > GPU load. Current driver doesn't provide a way to override the ring
> > multiplier.
> >
> > This patch adds
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