Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
the host support this feature, need to check the BIT(3) of caps in PVINFO.
v3 : Remove unnecessary comments.
v4 : Separate VM enable patch with GVT-g implementation patch due to code
dependency
Signed-off-by: Weinan Li
Cc
On Thu, 12 Oct 2017, Mika Kahola wrote:
> CI system spotted an error on CFL system when running IGT tests with
> display disabled. In this case, the 'INTEL_INFO(dev_priv)->num_pipes'
> is set to 0. This will cause that we prematurely return from
> 'get_saved_enc()'.
>
> To fix this issue, the patc
On 10/11/2017 10:49 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:09 +0200, Sagar Arun Kamble
wrote:
On resume from drm sleep/suspend, we have gem_init_hw path to reload
the GuC/HuC firmware. However, on resume from runtime suspend we needed
to add support to reload the GuC/HuC firm
On 10/11/2017 10:36 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:08 +0200, Sagar Arun Kamble
wrote:
GuC/HuC resume operation depends on whether firmwares are available
in the WOPCM region. This is known through register WOPCM_SIZE BIT(0).
If it indicates WOPCM is locked (bit is se
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Mika Kahola
> Sent: torstai 12. lokakuuta 2017 9.30
> To: intel-gfx@lists.freedesktop.org
> Cc: ville.syrj...@intel.linux.com; Vivi, Rodrigo
> Subject: [Intel-gfx] [PATCH] drm/i915:
On 10/11/2017 9:49 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:05 +0200, Sagar Arun Kamble
wrote:
Suspending GuC involves bunch of tasks controlled by GuC OS and some
controlled by Host OS.
Host needs to disable submission to GuC and any other GuC functions.
Then,
GuC's task is
CI system spotted an error on CFL system when running IGT tests with
display disabled. In this case, the 'INTEL_INFO(dev_priv)->num_pipes'
is set to 0. This will cause that we prematurely return from
'get_saved_enc()'.
To fix this issue, the patch introduces a 'max_pipes' variable which caches
the
On 10/11/2017 9:27 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:04 +0200, Sagar Arun Kamble
wrote:
Prepared generic helpers intel_uc_suspend, intel_uc_resume. These are
called from respective GEM functions. Only exception is intel_uc_resume
that needs to be called w/ or w/o GuC loa
On 10/11/2017 9:20 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:01 +0200, Sagar Arun Kamble
wrote:
intel_guc_suspend and intel_guc_resume are GuC specific functions hence
update the parameter from dev_priv to intel_guc struct. While at it do
s/dev_priv/i915 in suspend/resume functi
On 10/12/2017 11:20 AM, Sagar Arun Kamble wrote:
On 10/11/2017 8:50 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:53:58 +0200, Sagar Arun Kamble
wrote:
GuC interrupts are currently enabled by Logging and disabled in
different
scenarios. Make disabling check whether interrupts were a
== Series Details ==
Series: lib/igt_gt: Allow non-default contexts to hang non-render rings (rev4)
URL : https://patchwork.freedesktop.org/series/31693/
State : success
== Summary ==
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (shard-hsw) fd
Hi Dave,
Here goes
drm-intel-fixes-2017-10-11:
Three fixes for stable:
- Use crtc_state_is_legacy_gamma in intel_color_check (Maarten)
- Read timings from the correct transcoder (Ville).
- Fix HDMI on BSW (Jani).
Other fixes:
- eDP fixes (Manasi)
- Silence compiler warnings (Chris)
- Order two
== Series Details ==
Series: drm/i915/edp: Do not do link training fallback or prune modes on EDP
URL : https://patchwork.freedesktop.org/series/31776/
State : failure
== Summary ==
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test km
== Series Details ==
Series: Lib: Move __gem_context_create to common ioctl wrapper library.
URL : https://patchwork.freedesktop.org/series/31775/
State : success
== Summary ==
Test kms_flip:
Subgroup flip-vs-rmfb:
dmesg-warn -> PASS (shard-hsw) fdo#102614
On 10/11/2017 9:10 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:53:59 +0200, Sagar Arun Kamble
wrote:
With guc_log_level parameter sanitized and GuC interrupts control
functions made self sufficient w.r.t interrupts state, we can remove
the enable_guc_submission checks from flush_guc_
On 10/11/2017 8:50 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:53:58 +0200, Sagar Arun Kamble
wrote:
GuC interrupts are currently enabled by Logging and disabled in
different
scenarios. Make disabling check whether interrupts were already disabled
and similar for enable path. This w
On 10/11/2017 8:21 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:53:57 +0200, Sagar Arun Kamble
wrote:
Parameter guc_log_level needs to be sanitized based on GuC support and
enable_guc_loading parameter since it depends on them like
enable_guc_submission. This will make GuC logging pat
== Series Details ==
Series: enable virtual HWSP in GVT-g (rev2)
URL : https://patchwork.freedesktop.org/series/31217/
State : failure
== Summary ==
Series 31217 revision 2 was fully merged or fully failed: no git log
___
Intel-gfx mailing list
Inte
v2 : clean merge confict
v3 :
remove unnecessary comments
add address audit in HWSP address update
Weinan Li (2):
drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP
drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g
VM
drivers/gpu/drm/i915/gvt/ex
The engine provides a mirror of the CSB and CSB write pointer in the HWSP.
Read these status from virtual HWSP in VM can reduce CPU utilization while
applications have much more short GPU workloads. Here we update the
corresponding data in virtual HWSP as it in virtual MMIO.
Before read these stat
Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
the host support this feature, need to check the BIT(3) of caps in PVINFO.
v3 : Remove unnecessary comments.
Signed-off-by: Weinan Li
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_vgpu.c | 5
== Series Details ==
Series: drm/vblank: Fix flip event vblank count
URL : https://patchwork.freedesktop.org/series/31761/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
fdo#99912 https://bugs.freedesktop.
Hi,
Please consider pulling i915 updates to linux-firmware.git
The following changes since commit bf04291309d3169c0ad3b8db52564235bbd08e30:
WHENCE: Add new qed firmware (2017-10-09 18:03:26 +0100)
are available in the git repository at:
https://github.com/anushasr/linux-firmware.git master
Hi,
Please consider pulling i915 updates o linux-firmware.git.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
== Series Details ==
Series: lib/igt_gt: Allow non-default contexts to hang non-render rings (rev4)
URL : https://patchwork.freedesktop.org/series/31693/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wai
This limitation does not exist in latest kernel. It was removed by this patch-
commit f7978a0c581a8a840a28306f8da43e06e7fef3bf
v2: Added commit id that removes the limitation(Chris Wilson)
V3: Generic way to find if kernel supports this instead of hardcoding
gens(Chris Wilson)
v4: Optimize the i
On 10/11/2017 4:23 PM, Daniele Ceraolo Spurio wrote:
On 11/10/17 14:31, Vinay Belgaumkar wrote:
This limitation does not exist in latest kernel. It was removed by
this patch-
commit f7978a0c581a8a840a28306f8da43e06e7fef3bf
v2: Added commit id that removes the limitation(Chris Wilson)
V3: G
== Series Details ==
Series: drm/i915/edp: Do not do link training fallback or prune modes on EDP
URL : https://patchwork.freedesktop.org/series/31776/
State : success
== Summary ==
Series 31776v1 drm/i915/edp: Do not do link training fallback or prune modes on
EDP
https://patchwork.freedeskt
== Series Details ==
Series: drm/i915: Plane assert/readout cleanups etc.
URL : https://patchwork.freedesktop.org/series/31758/
State : success
== Summary ==
Test kms_flip:
Subgroup plain-flip-ts-check:
pass -> FAIL (shard-hsw) fdo#100368
fdo#100368 https:/
== Series Details ==
Series: Lib: Move __gem_context_create to common ioctl wrapper library.
URL : https://patchwork.freedesktop.org/series/31775/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wait: Don'
On 11/10/17 14:31, Vinay Belgaumkar wrote:
This limitation does not exist in latest kernel. It was removed by this patch-
commit f7978a0c581a8a840a28306f8da43e06e7fef3bf
v2: Added commit id that removes the limitation(Chris Wilson)
V3: Generic way to find if kernel supports this instead of ha
In case of eDP because the panel has a fixed mode, the link rate
and lane count at which it is trained corresponds to the link BW
required to support the native resolution of the panel. In case of
panles with lower resolutions where fewer lanes are hooked up internally,
that number is reflected in
This patch adds a context creation ioctl wrapper that returns the error
for the caller to consume. Multiple tests that implemented this already,
have been changed to use the new library function.
Signed-off-by: Antonio Argenziano
---
benchmarks/gem_exec_ctx.c | 16
benchmarks/
On 10/10/17 07:51, Michal Wajdeczko wrote:
We want to keep ucode xfer functions separate from other
initialization. Once separated, add explicit forcewake.
Suggested-by: Joonas Lahtinen
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/int
== Series Details ==
Series: lib/igt_gt: Allow non-default contexts to hang non-render rings (rev3)
URL : https://patchwork.freedesktop.org/series/31693/
State : warning
== Summary ==
IGT patchset tested on top of latest successful build
136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wai
This limitation does not exist in latest kernel. It was removed by this patch-
commit f7978a0c581a8a840a28306f8da43e06e7fef3bf
v2: Added commit id that removes the limitation(Chris Wilson)
V3: Generic way to find if kernel supports this instead of hardcoding
gens(Chris Wilson)
Cc: Michel Thierr
== Series Details ==
Series: drm/i915/userptr: Drop struct_mutex before cleanup
URL : https://patchwork.freedesktop.org/series/31748/
State : warning
== Summary ==
Test pm_rpm:
Subgroup basic-rte:
pass -> SKIP (shard-hsw)
Subgroup universal-planes:
== Series Details ==
Series: IGT PMU support (rev12)
URL : https://patchwork.freedesktop.org/series/28253/
State : failure
== Summary ==
Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS (shard-hsw) fdo#102886 +1
Test gem_tiled_swapping:
Subgroup non-th
== Series Details ==
Series: lib/igt_gt: Allow non-default contexts to hang non-render rings (rev2)
URL : https://patchwork.freedesktop.org/series/31693/
State : failure
== Summary ==
IGT patchset tested on top of latest successful build
136100c2f00b590bc9485100cce012282c1217cf igt/syncobj_wai
== Series Details ==
Series: igt/prime_mmap_coherency: Only assert correct usage of sync API
URL : https://patchwork.freedesktop.org/series/31729/
State : success
== Summary ==
Test gem_flink_race:
Subgroup flink_close:
pass -> FAIL (shard-hsw) fdo#102655
f
== Series Details ==
Series: drm/i915: Use a cached mapping for the physical HWS (rev3)
URL : https://patchwork.freedesktop.org/series/24562/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test kms_cursor_l
On Tue, 10 Oct 2017, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Untangle intel_enable_ddi() by splitting it into DP and HDMI specific
> variants.
>
> v2: Keep using intel_ddi_get_encoder_port() for now
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 86
> +++
On Tue, 10 Oct 2017, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Untangle intel_disable_ddi() by splitting it into DP and HDMI specific
> variants.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 51
>
> 1 file changed, 31
== Series Details ==
Series: Refactor HW workaround code (rev2)
URL : https://patchwork.freedesktop.org/series/31611/
State : warning
== Summary ==
Series 31611v2 Refactor HW workaround code
https://patchwork.freedesktop.org/api/1.0/series/31611/revisions/2/mbox/
Test gem_close_race:
Hi Dave,
Here's the latest from -misc-fixes. We have fixes for a reference leak, and a
race.
Following Jani's lead, I've setup dim to sign my pull requests. You can find my
public key at https://pgp.key-server.io/0x732C002572DCAF79
drm-misc-fixes-2017-10-11:
Core Changes:
- sync_file: Fix race i
On Tue, 10 Oct 2017, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract the code to disable the DDI_BUF_CTL into small helper. This
> will allows us to detangle the encoder type mess in
> intel_ddi_post_disable().
>
> v2: Keep using intel_ddi_get_encoder_port() for now
>
> Reviewed-by: Jani N
On Tue, 10 Oct 2017, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Pull the code to disable the port clock into a function. We already have
> the intel_ddi_clk_select() counterpart.
>
> v2: Keep using intel_ddi_get_encoder_port() for now (Chris)
>
> Cc: Chris Wilson
> Signed-off-by: Ville Syrjä
On Tue, 10 Oct 2017, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> To make it easier to debug things let's dump the output types bitmask in
> the crtc state dump. And to make life that much better, let's pretty
> print it as a a human reaadable string as well.
>
> v2: Have the caller pass in the
On Mon, 09 Oct 2017, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/dp: WARN about invalid/unknown link
> rates and bw codes
> URL : https://patchwork.freedesktop.org/series/31579/
> State : failure
>
> == Summary ==
>
> Test kms_atomic_transition:
>
== Series Details ==
Series: drm/vblank: Fix flip event vblank count
URL : https://patchwork.freedesktop.org/series/31761/
State : success
== Summary ==
Series 31761v1 drm/vblank: Fix flip event vblank count
https://patchwork.freedesktop.org/api/1.0/series/31761/revisions/1/mbox/
Test drv_mod
On Wed, Oct 11, 2017 at 07:06:45PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2017-10-09 17:19:51)
> > From: Ville Syrjälä
> >
> > With intel_encoder_current_mode() using the normal state readout code it
> > actually works on PCH platforms as well. So let's nuke the PCH check from
> > in
Quoting Oscar Mateo (2017-10-11 19:15:18)
> Let's try to make sure that all WAs are applied correctly and survive
> resumes, resets, etc... (with some help from a companion i-g-t patch).
>
> Signed-off-by: Oscar Mateo
> Cc: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_deb
Quoting Oscar Mateo (2017-10-11 19:15:40)
> Apart from context based workarounds, we can now also test for global
> MMIO and whitelisting ones.
>
> Do take into account that this test does not guarantee that all known
> WAs for a given platform are applied. It only checks that the WAs the
> kernel
On Wed, Oct 11, 2017 at 11:15:14AM -0700, Oscar Mateo wrote:
> I'm not sure why some WAs have historically been applied in init_clock_gating
> and some others in the engine setup (GT vs. display? context vs. global
> registers?) but it does not look like the best place to apply workarounds:
> the n
Quoting Oscar Mateo (2017-10-11 19:15:14)
> I'm not sure why some WAs have historically been applied in init_clock_gating
> and some others in the engine setup (GT vs. display? context vs. global
> registers?) but it does not look like the best place to apply workarounds:
> the name is confusing, i
Quoting Oscar Mateo (2017-10-11 19:15:14)
> I'm not sure why some WAs have historically been applied in init_clock_gating
> and some others in the engine setup (GT vs. display? context vs. global
> registers?) but it does not look like the best place to apply workarounds:
> the name is confusing, i
Quoting Oscar Mateo (2017-10-11 19:15:13)
> There are different kind of workarounds (those that modify registers that
> live in the context image, those that modify global registers, those that
> whitelist registers, etc...) and they have different requirements in terms
> of where they are applied
On Wed, 11 Oct 2017 20:09:10 +0200, Sagar Arun Kamble
wrote:
On 10/11/2017 11:28 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 19:44:31 +0200, Sagar Arun Kamble
wrote:
On 10/11/2017 11:05 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble
wrote:
Quoting Oscar Mateo (2017-10-11 19:15:40)
> @@ -241,39 +350,34 @@ igt_main
> }, *m;
>
> igt_fixture {
> + struct pci_device *pci_dev;
> FILE *file;
> - char *line = NULL;
> - size_t line_size;
> - int i, fd;
>
Apart from context based workarounds, we can now also test for global
MMIO and whitelisting ones.
Do take into account that this test does not guarantee that all known
WAs for a given platform are applied. It only checks that the WAs the
kernel does know about are correctly applied (e.g. they didn
Let's try to make sure that all WAs are applied correctly and survive
resumes, resets, etc... (with some help from a companion i-g-t patch).
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 48 ++---
1 file
Some WAs touch registers that get saved/restored together with the logical
context.
Make this very explicit by renaming a few things in the code.
v2:
- Improved naming
- Rebased
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c |
Does what it says on the tin (plus a few fixes in some old comments).
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_workarounds.c | 45 +++-
1 file changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
By doing this, we can dump these workarounds in debugfs for validation (which,
at the moment, we are only able to do for the contexts WAs).
v2:
- Wrong macro used for MMIO set bit masked
- Improved naming
- Rebased
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
driver
Same as we have been doing for other types, this allow us to dump
the whole list of workarounds to debugs, for validation purposes.
v2:
- Improved naming
- Rebased
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/
Now that we write RING_FORCE_TO_NONPRIV registers directly to hardware,
[commit 32ced39 ("drm/i915: Transform whitelisting WAs into a simple reg
write")] there is no need to save space for them in the list of context
workarounds.
v2: Refer to previous commit in commit message (Michel)
Signed-off-
I'm not sure why some WAs have historically been applied in init_clock_gating
and some others in the engine setup (GT vs. display? context vs. global
registers?) but it does not look like the best place to apply workarounds:
the name is confusing, it's a display function (even though some GT WAs
al
Since we are trying to put all WA stuff together, do not forget about the BB
WAs.
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 253 +-
drivers/gpu/drm/i915/intel_workarounds.c | 254 +++
I didn't receive any major opposition to the RFC, so I am sending the patches
again with some review comments from Chris, a typo fix and some aesthetic
improvements.
Currently, deciding how/where to apply new workarounds is challenging. Often,
workarounds end up applied incorrectly and get lost un
GEN8_CONFIG0 (0xD00) is a protected by a lock (bit 31) which is set by
the BIOS, so there is no way we can enable the three chicken bits
mandated by the WA (the BIOS should be doing it instead).
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h
There are different kind of workarounds (those that modify registers that
live in the context image, those that modify global registers, those that
whitelist registers, etc...) and they have different requirements in terms
of where they are applied and how. Also, by splitting them apart, it should
This has grown to be a sizable amount of code, so move it to
its own file before we try to refactor anything. For the moment,
we are leaving behind the WA BB code and the WAs that get applied
(incorrectly) in init_clock_gating, but we will deal with it later.
v2: Use intel_ prefix for code that de
On 10/11/2017 11:28 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 19:44:31 +0200, Sagar Arun Kamble
wrote:
On 10/11/2017 11:05 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble
wrote:
i915_ggtt_enable_guc has to happen first during i915_gem_resume
if
Quoting Ville Syrjala (2017-10-09 17:19:51)
> From: Ville Syrjälä
>
> With intel_encoder_current_mode() using the normal state readout code it
> actually works on PCH platforms as well. So let's nuke the PCH check from
> intel_lvds_init(). I suppose there aren't any machines that actually
> need
Hi Dave, more v4.15 features.
Our tooling now supports signed tags, this one is probably the
first. Maybe we can make them mandatory in the long run.
drm-intel-next-2017-09-29:
2nd batch of v4.15 features:
- lib/scatterlist updates, use for userptr allocations (Tvrtko)
- Fixed point wrapper cle
On Wed, 11 Oct 2017 19:44:31 +0200, Sagar Arun Kamble
wrote:
On 10/11/2017 11:05 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble
wrote:
i915_ggtt_enable_guc has to happen first during i915_gem_resume
if GuC loading is enabled before GTT restore. In ca
On 10/11/2017 11:00 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:13 +0200, Sagar Arun Kamble
wrote:
In i915_reset/gem_sanitize, GPU will be reset and driver state about
GuC/HuC load status will be invalid. Hence, we mark both GuC/HuC as not
loaded/NONE.
Signed-off-by: Sagar Arun K
On 10/11/2017 11:05 PM, Michal Wajdeczko wrote:
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble
wrote:
i915_ggtt_enable_guc has to happen first during i915_gem_resume
if GuC loading is enabled before GTT restore. In case GuC is not
loaded this enabling happening during intel_uc_init_h
On Wed, Oct 11, 2017 at 08:51:06AM +, Mark Brown wrote:
> On Tue, Oct 10, 2017 at 08:03:00AM +0100, Mark Brown wrote:
> > Hi all,
> >
> > After merging the drm-misc-fixes tree, today's linux-next build
> > (x86_allmodconfig) failed like this:
> >
> > CC [M] drivers/gpu/drm/i915/i915_gem_ev
On Wed, 11 Oct 2017 10:54:14 +0200, Sagar Arun Kamble
wrote:
i915_ggtt_enable_guc has to happen first during i915_gem_resume
if GuC loading is enabled before GTT restore. In case GuC is not
loaded this enabling happening during intel_uc_init_hw need to
skipped. (avoid the GEM_BUG_ON)
i915_ggt
On Wed, 11 Oct 2017 10:54:13 +0200, Sagar Arun Kamble
wrote:
In i915_reset/gem_sanitize, GPU will be reset and driver state about
GuC/HuC load status will be invalid. Hence, we mark both GuC/HuC as not
loaded/NONE.
Signed-off-by: Sagar Arun Kamble
Cc: Michal Wajdeczko
Cc: Michał Winiarski
Quoting Vinay Belgaumkar (2017-10-11 18:16:23)
> This limitation does not exist for gen8+. It was removed by this patch-
>
> commit f7978a0c581a8a840a28306f8da43e06e7fef3bf
So where is the mention of gen8 there? And where is the compatibility
test to determine the age of the kernel?
As a hint,
== Series Details ==
Series: drm/i915: Plane assert/readout cleanups etc.
URL : https://patchwork.freedesktop.org/series/31758/
State : success
== Summary ==
Series 31758v1 drm/i915: Plane assert/readout cleanups etc.
https://patchwork.freedesktop.org/api/1.0/series/31758/revisions/1/mbox/
fi
On Wed, 11 Oct 2017 10:54:09 +0200, Sagar Arun Kamble
wrote:
On resume from drm sleep/suspend, we have gem_init_hw path to reload
the GuC/HuC firmware. However, on resume from runtime suspend we needed
to add support to reload the GuC/HuC firmware and resume.
We can leverage intel_uc_init_hw
On Wed, Oct 11, 2017 at 05:21:56PM +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2017-10-10 15:33:33)
> > Quoting Ville Syrjala (2017-10-09 17:19:50)
> > > From: Ville Syrjälä
> > >
> > > Reuse the normal state readout code to get the fixed mode for LVDS/DVO
> > > encoders. This removes some
This limitation does not exist for gen8+. It was removed by this patch-
commit f7978a0c581a8a840a28306f8da43e06e7fef3bf
v2: Added commit id that removes the limitation(Chris Wilson)
Cc: Michel Thierry
Cc: Arkadiusz Hiler
Cc: Petri Latvala
Signed-off-by: Vinay Belgaumkar
---
lib/igt_gt.c | 8
On Wed, 11 Oct 2017 10:54:08 +0200, Sagar Arun Kamble
wrote:
GuC/HuC resume operation depends on whether firmwares are available
in the WOPCM region. This is known through register WOPCM_SIZE BIT(0).
If it indicates WOPCM is locked (bit is set) we just need to send action
to GuC to resume an
== Series Details ==
Series: softdog: Obey hardlockup_all_cpu_backtrace sysctl (rev2)
URL : https://patchwork.freedesktop.org/series/31751/
State : warning
== Summary ==
Series 31751v2 softdog: Obey hardlockup_all_cpu_backtrace sysctl
https://patchwork.freedesktop.org/api/1.0/series/31751/revi
From: Ville Syrjälä
On machines where the vblank interrupt fires some time after the start
of vblank (or we just manage to race with the vblank interrupt handler)
we will currently stuff a stale vblank counter value into the flip event,
and thus we'll prematurely complete the flip.
Switch over t
On Wed, Oct 11, 2017 at 04:21:58PM +, Alex Villacis Lasso wrote:
> El 11/10/17 a las 11:04, Ville Syrjala escribió:
> > From: Ville Syrjälä
> >
> > This series aims to clean up some of the plane state readout and
> > sanitation, and clean up the enum plane mess a bit by renaming it
> > to enum
== Series Details ==
Series: series starting with [1/2] drm/i915: Parse DSI backlight/cabc ports.
URL : https://patchwork.freedesktop.org/series/31737/
State : warning
== Summary ==
Test prime_self_import:
Subgroup reimport-vs-gem_close-race:
pass -> FAIL (s
Quoting Chris Wilson (2017-10-10 15:33:33)
> Quoting Ville Syrjala (2017-10-09 17:19:50)
> > From: Ville Syrjälä
> >
> > Reuse the normal state readout code to get the fixed mode for LVDS/DVO
> > encoders. This removes some partially duplicated state readout code
> > from LVDS/DVO encoders. The d
On Wed, 11 Oct 2017 10:54:05 +0200, Sagar Arun Kamble
wrote:
Suspending GuC involves bunch of tasks controlled by GuC OS and some
controlled by Host OS.
Host needs to disable submission to GuC and any other GuC functions.
Then,
GuC's task is initiated by Host sending action to GuC to ente
From: Ville Syrjälä
Use enum pipe, enum plane_id, and enum old_plane_id consistently in the
initial framebuffe readout.
v2: Use old_plane_id in the ilk code
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 58
1 file changed, 32 inse
From: Ville Syrjälä
Eliminate crtc->plane since it's pretty much a layering violation.
We can always get the plane via crtc->primary if we actually need it.
The only ugly thing left is plane_to_crtc_mapping[], but that's
still needed by the pre-g4x watermark code.
Also revise the comment about
From: Ville Syrjälä
Stop using the old for_each_intel_plane_in_state() type iteration
macro and replace it with for_each_new_intel_plane_in_state().
And similarly replace drm_atomic_get_existing_crtc_state() with
intel_atomic_get_new_crtc_state(). Switch over to intel_ types
as well to make the c
From: Ville Syrjälä
Plane B and C (note that we don't actually expose plane C currently)
on gen2/3 have a window generator, as does the primary plane on CHV
pipe B. So let's allow positioning of these planes freely within the
pipe source area.
Plane A on gen2/3 seems to have some kind of partial
From: Ville Syrjälä
Replace the 0 and 1 with PLANE_A and PLANE_B in the pre-g4x wm code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_pm.c | 36 +++-
2 files changed, 21 insertions(+), 18 deletions(-)
dif
From: Ville Syrjälä
The only relevant difference between i9xx_get_initial_plane_config() and
ironlake_get_initial_plane_config() is the HSW/BDW TILEOFF handling.
Add that to i9xx_get_initial_plane_config() and nuke
ironlake_get_initial_plane_config().
Signed-off-by: Ville Syrjälä
---
drivers/g
From: Ville Syrjälä
Rename enum plane to enum old_plane_id to make it clear that it only
applies to pre-SKL platforms.
v2: Reorder patches
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/intel_display.c | 84 ++---
1 - 100 of 224 matches
Mail list logo
