== Series Details ==
Series: igt/kms_rotation_crc: Add horizontal flip subtest.
URL : https://patchwork.freedesktop.org/series/31407/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
7f93a2632aae7c5865823b4a2fa4cd8c2a1c0977 Update NEWS, bump version to 1.20.
On Wed, 04 Oct 2017, Manasi Navare wrote:
> Kernel stores the time in jiffies at which the eDP panel is turned
> off. This should be obtained after the panel is off (after the
> wait_panel_off). When we next attempt to turn the panel on, we
> use the difference between the timestamp at which we wa
On Thu, Oct 05, 2017 at 01:08:56AM +, Patchwork wrote:
> == Series Details ==
>
> Series: igt/kms_rotation_crc: Add horizontal flip subtest.
> URL : https://patchwork.freedesktop.org/series/31407/
> State : success
>
> == Summary ==
>
> IGT patchset tested on top of latest successful build
On Wed, 04 Oct 2017, Lyude Paul wrote:
> On Wed, 2017-10-04 at 11:47 +0300, Jani Nikula wrote:
>> On Tue, 03 Oct 2017, Jani Nikula wrote:
>> > From: Dhinakaran Pandiyan
>> >
>> > Use the POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions to
>> > set power states for downstream sinks.
Hi Dave,
Firs of all thanks for pulling previous request.
Here goes another round of drm/i915 fixes.
This is on top of previous one. If this gets to
Linus by 4.14-rc4 the next one will be fully on
right bases. All my local dim scripts already
ajusted for that and a global "dim" solution is being
Hi Dave,
drm-misc-next-2017-10-05:
More drm-misc for 4.15:
Cross-subsystem Changes:
- bunch more simple outreachy patches (Meghana Madhyastha, Aishwarya
Pant, Haneen Mohammed)
- Quite a pile of static checker/cocci/spelling fixups all over.
- Final driver patches+core cleanup of Noralf's new d
On Thu, Aug 24, 2017 at 11:00:27PM +, Rodrigo Vivi wrote:
> On Thu, Aug 24, 2017 at 3:39 PM, Oscar Mateo wrote:
> >
> >
> > On 08/23/2017 05:01 PM, Rodrigo Vivi wrote:
> >>
> >> On Tue, Jul 18, 2017 at 8:15 AM, Oscar Mateo
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 07/14/2017 08:08 AM, Chris Wils
== Series Details ==
Series: igt/kms_rotation_crc: Add horizontal flip subtest.
URL : https://patchwork.freedesktop.org/series/31407/
State : success
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_299/shards.html
___
== Series Details ==
Series: igt/kms_rotation_crc: Add horizontal flip subtest.
URL : https://patchwork.freedesktop.org/series/31407/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
7f93a2632aae7c5865823b4a2fa4cd8c2a1c0977 Update NEWS, bump version to 1.20.
In preparation for unconditionally passing the struct timer_list pointer to
all timer callbacks, switch to using the new timer_setup() and from_timer()
to pass the timer pointer explicitly.
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: David Airlie
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursu
From: Joseph Garvey
Test that horizontal flip works with supported rotations. Includes
a fix for the unrotated fb which was not being positioned correctly
with portrait and landscape rectangles.
v2:(from Anusha)
- Change 180 degree rotation to follow the rest, use
igt_swap(), make flip variable
On 10/03/2017 11:45 PM, Sagar Arun Kamble wrote:
Subject is missing "parameter" in the end. Either keep module
parameter or i915_modparams.
Will fix the subject line.
On 10/4/2017 4:26 AM, Sujaritha Sundaresan wrote:
We currently have two module parameters that control GuC:
"enable_guc_l
Em Ter, 2017-10-03 às 15:31 -0700, Rodrigo Vivi escreveu:
> This is heavily based on a initial patch provided by Ville
> plus all changes provided later by Ander.
>
> As Geminilake, Cannonlake also supports 2 pixels per clock.
>
> Different from Geminilake we are not implementing the 99% Wa.
> Bu
On Wed, Oct 04, 2017 at 03:40:11PM -0700, Manasi Navare wrote:
> On Wed, Oct 04, 2017 at 12:36:42PM -0700, Rodrigo Vivi wrote:
> > On Wed, Oct 04, 2017 at 09:46:41AM +, Mika Kahola wrote:
> > > On Tue, 2017-10-03 at 00:06 -0700, Rodrigo Vivi wrote:
> > > > According to spec "If voltage is set t
I think the failure was with one particularly slow eDP panel, but it is safer
to apply this to all ports.
-Original Message-
From: Vivi, Rodrigo
Sent: Wednesday, 4 October, 2017 1:25 PM
To: Ausmus, James
Cc: intel-gfx@lists.freedesktop.org; ville.syrj...@linux.intel.com;
jani.nik...@l
== Series Details ==
Series: drm/i915: Guc code reorg cont'd
URL : https://patchwork.freedesktop.org/series/31401/
State : success
== Summary ==
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
fdo#102252 https://bugs.freedesktop.org/show_b
On Wed, Oct 04, 2017 at 12:36:42PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 04, 2017 at 09:46:41AM +, Mika Kahola wrote:
> > On Tue, 2017-10-03 at 00:06 -0700, Rodrigo Vivi wrote:
> > > According to spec "If voltage is set too low,
> > > it will break functionality. If voltage is set too high,
On Tue, Oct 03, 2017 at 12:06:09AM -0700, Rodrigo Vivi wrote:
> From: "Kahola, Mika"
>
> Display Voltage and Frequency Switching (DVFS) is used to adjust the
> display voltage to match the display clock frequencies. To save power the
> voltage is set to minimum when disabling PLL.
>
> The sequen
On Tue, Oct 03, 2017 at 12:06:08AM -0700, Rodrigo Vivi wrote:
> From: "Kahola, Mika"
>
> Display Voltage and Frequency Switching (DVFS) is used to adjust the
> display voltage to match the display clock frequencies. If voltage is
> set too low, it will break functionality. If voltage is set too h
== Series Details ==
Series: lib/igt_kms: Convert properties to be more atomic-like. (rev11)
URL : https://patchwork.freedesktop.org/series/30903/
State : warning
== Summary ==
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
pass -> FAIL (shard
On Tue, Oct 03, 2017 at 12:06:07AM -0700, Rodrigo Vivi wrote:
> From: "Kahola, Mika"
>
> DVFS computation needs cnl_dvfs_{pre,post}_change() functions to be exposed.
> These functions will be used when computing DVFS levels in intel_dpll_mgr.c
>
> Cc: Ville Syrjälä
> Signed-off-by: Kahola, Mika
Looks good and this refactoring makes since.
Reviewed-by: Manasi Navare
On Tue, Oct 03, 2017 at 12:06:06AM -0700, Rodrigo Vivi wrote:
> From: Paulo Zanoni
>
> These functions even have their own page in our spec,
> so extract them from cnl_set_cdclk().
>
> v2: (By Rodrigo) Fixed inverted logi
On Tue, Oct 3, 2017 at 12:06 AM, Rodrigo Vivi wrote:
> From: Paulo Zanoni
>
> These functions even have their own page in our spec,
> so extract them from cnl_set_cdclk().
>
> v2: (By Rodrigo) Fixed inverted logic on error return of
> cnl_dvfs_pre_change.
>
> Cc: Ville Syrjälä
> Signed-off-b
Good catch. Looks good to me as per the Bspec.
Reviewed-by: Manasi Navare
Manasi
On Tue, Oct 03, 2017 at 03:08:59PM -0700, Rodrigo Vivi wrote:
> HDMI Mode selection on CNL is on CFGCR0 for that PLL, not
> on in a global CTRL1 as it was on SKL.
>
> The original patch addressed this difference,
On Wed, Oct 04, 2017 at 07:38:16PM +, Rodrigo Vivi wrote:
> On Wed, Oct 04, 2017 at 06:39:19AM +, Mika Kahola wrote:
> > On Tue, 2017-10-03 at 00:06 -0700, Rodrigo Vivi wrote:
> > > On Cannonlake the DVFS level selection depends on the
> > > port clock.
> > >
> > > So let's re-org in a way
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/edp: Get the Panel Power Off
timestamp after panel is off (rev2)
URL : https://patchwork.freedesktop.org/series/31361/
State : failure
== Summary ==
Test gem_flink_race:
Subgroup flink_close:
fail
On 10/04/2017 06:17 AM, Chris Wilson wrote:
Quoting Mika Kuoppala (2017-10-04 13:39:13)
Oscar Mateo writes:
RING_FORCE_TO_NONPRIV registers do not live in the logical context. They are
simply
global privileged MMIO registers that happen to be powercontext saved and
restored
(meaning only
On Wed, Oct 04, 2017 at 08:09:21PM +, James Ausmus wrote:
> Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
> the meaning of the (3 << 26) value varies per platform, but it's always the
> maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
> it means 3
== Series Details ==
Series: Fix HDMI as dual display on CNL.
URL : https://patchwork.freedesktop.org/series/31352/
State : success
== Summary ==
Series 31352v1 Fix HDMI as dual display on CNL.
https://patchwork.freedesktop.org/api/1.0/series/31352/revisions/1/mbox/
fi-bdw-5557u total:289
On Wed, Oct 04, 2017 at 08:09:22PM +, James Ausmus wrote:
> Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
> Set BDW to 600us unconditionally.
Besides that statement I also found on BSpec:
"
Workaround
Project
BDW, EXCLUDE(CHV)
Set the Timeout timer value to at least 6
Rename DP_AUX_CH_CTL_TIME_OUT_1600us to DP_AUX_CH_CTL_TIME_OUT_MAX, as
the meaning of the (3 << 26) value varies per platform, but it's always the
maximum timeout for that platform. Pre-CNL it means 1600us, and for CNL
it means 3200us.
v2:
-Split in to two patches (Rodrigo)
Cc: Rodrigo Vivi
Sign
Per BSpec, 400us is "BDW+ Do not use this setting." - not just PORT_A.
Set BDW to 600us unconditionally.
v2:
-Split in to two patches (Rodrigo)
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: James Ausmus
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/preempt: Fix
WaEnablePreemptionGranularityControlByUMD
URL : https://patchwork.freedesktop.org/series/31394/
State : failure
== Summary ==
Test gem_ctx_param:
Subgroup invalid-param-get:
pass ->
On Wed, Oct 04, 2017 at 06:39:19AM +, Mika Kahola wrote:
> On Tue, 2017-10-03 at 00:06 -0700, Rodrigo Vivi wrote:
> > On Cannonlake the DVFS level selection depends on the
> > port clock.
> >
> > So let's re-org in a way that we can easily export without
> > duplicating any code.
> >
> > v2:
On Wed, Oct 04, 2017 at 09:46:41AM +, Mika Kahola wrote:
> On Tue, 2017-10-03 at 00:06 -0700, Rodrigo Vivi wrote:
> > According to spec "If voltage is set too low,
> > it will break functionality. If voltage is set too high,
> > it will waste power."
> >
> > So, let's prefer the waste of powe
On Tue, Oct 3, 2017 at 3:08 PM, Rodrigo Vivi wrote:
> HDMI Mode selection on CNL is on CFGCR0 for that PLL, not
> on in a global CTRL1 as it was on SKL.
>
> The original patch addressed this difference, but leaving behind
> this single entry here. So we were checking the wrong bits during
> the PL
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/edp: Get the Panel Power Off
timestamp after panel is off (rev2)
URL : https://patchwork.freedesktop.org/series/31361/
State : success
== Summary ==
Series 31361v2 series starting with [v2,1/2] drm/i915/edp: Get the Panel Pow
On Tue, Oct 3, 2017 at 3:08 PM, Rodrigo Vivi wrote:
> On PLL Enable sequence we need to "Configure DPCLKA_CFGCR0 to turn on
> the clock for the DDI and map the DPLL to the DDI"
>
> So we first do the map and then we unset DDI_CLK_OFF to turn the clock
> on. We do this in 2 separated steps.
>
> How
== Series Details ==
Series: drm/i915: Guc code reorg cont'd
URL : https://patchwork.freedesktop.org/series/31401/
State : success
== Summary ==
Series 31401v1 drm/i915: Guc code reorg cont'd
https://patchwork.freedesktop.org/api/1.0/series/31401/revisions/1/mbox/
Test kms_pipe_crc_basic:
On Wed, 2017-10-04 at 11:47 +0300, Jani Nikula wrote:
> On Tue, 03 Oct 2017, Jani Nikula wrote:
> > From: Dhinakaran Pandiyan
> >
> > Use the POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions to
> > set power states for downstream sinks. Apart from giving us the ability
> > to set po
== Series Details ==
Series: drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC
size (rev3)
URL : https://patchwork.freedesktop.org/series/31284/
State : success
== Summary ==
Test gem_flink_race:
Subgroup flink_close:
fail -> PASS (shar
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/edp: Get the Panel Power Off
timestamp after panel is off (rev2)
URL : https://patchwork.freedesktop.org/series/31361/
State : failure
== Summary ==
Series 31361v2 series starting with [v2,1/2] drm/i915/edp: Get the Panel Pow
On 10/4/2017 10:36 PM, Chris Wilson wrote:
Quoting Sagar Arun Kamble (2017-10-04 15:07:25)
Defined new struct intel_rc6 to hold RC6 specific state and
intel_ring_pstate to hold ring specific state.
What do you mean by ring? Probably not struct intel_ring.
For us it would be closer to intel_e
== Series Details ==
Series: series starting with [v2,1/5] igt/gem_workarounds: Read the workaround
registers from the active context
URL : https://patchwork.freedesktop.org/series/31388/
State : warning
== Summary ==
IGT patchset tested on top of latest successful build
7f93a2632aae7c5865823
Move GuC log declarations into dedicated header as we want to
keep component specific code in separate files.
v2: fix includes (Chris)
update commit message (Joonas)
Suggested-by: Joonas Lahtinen
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
R
Unify initialization of the uC firmware helper as we want to
maximize code reuse.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc_loader.c | 5 +
drivers/gpu/drm/i915/intel_huc.c| 5 +
drivers/gpu/drm/i915/intel_uc_fw.h
Move GuC core definitions into dedicated files as we want to
keep GuC specific code in separated files.
v2: move all functions in single patch (Joonas)
fix old checkpatch issues (Sagar)
v3: rebased
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Leftover from https://patchwork.freedesktop.org/series/31340/
plus next round of minor improvements
Michal Wajdeczko (5):
drm/i915/guc: Move GuC log declarations into dedicated header
drm/i915/guc: Move GuC submission declarations into dedicated header
drm/i915/guc: Move GuC core definitions
Move GuC submission declarations into dedicated header as we want to
keep uC specific code in separate files.
v2: fix include (Chris)
update commit message (Joonas)
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Cc: MichaĹ Winiarski
Reviewed-by
Fix includes order and make sure we only include required headers.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_uc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
== Series Details ==
Series: drm/i915: Guc code reorg
URL : https://patchwork.freedesktop.org/series/31391/
State : warning
== Summary ==
Test kms_flip:
Subgroup blt-wf_vblank-vs-modeset:
pass -> DMESG-WARN (shard-hsw)
Subgroup flip-vs-rmfb-interruptible:
== Series Details ==
Series: lib/igt_kms: Convert properties to be more atomic-like. (rev11)
URL : https://patchwork.freedesktop.org/series/30903/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
7f93a2632aae7c5865823b4a2fa4cd8c2a1c0977 Update NEWS, bump vers
Nice data, thank you!
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Wednesday, October 4, 2017 10:35 AM
To: Tvrtko Ursulin ; Intel-gfx@lists.freedesktop.org
Cc: Chris Wilson ; Rogozhkin, Dmitry V
Subject: Re: [Intel-gfx] [PATCH 06/10] drm/i915/pmu
Quoting Tvrtko Ursulin (2017-10-04 18:38:09)
>
> On 03/10/2017 11:17, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-09-29 13:34:57)
> >> From: Tvrtko Ursulin
> >>
> >> This reduces the cost of the software engine busyness tracking
> >> to a single no-op instruction when there are no listen
On 10/4/2017 10:34 PM, Chris Wilson wrote:
Quoting Sagar Arun Kamble (2017-10-04 15:07:23)
Prepared intel_update_ring_freq function to setup ring frequency
for applicable platforms determined by macro - NEEDS_RING_FREQ_UPDATE
Signed-off-by: Sagar Arun Kamble
Cc: Imre Deak
Cc: Chris Wilson
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/edp: Get the Panel Power Off
timestamp after panel is off (rev2)
URL : https://patchwork.freedesktop.org/series/31361/
State : warning
== Summary ==
Series 31361v2 series starting with [v2,1/2] drm/i915/edp: Get the Panel Pow
On 03/10/2017 11:17, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2017-09-29 13:34:57)
From: Tvrtko Ursulin
This reduces the cost of the software engine busyness tracking
to a single no-op instruction when there are no listeners.
We add a new i915 ordered workqueue to be used only for tasks
n
On 29/09/2017 13:34, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We can use engine busy stats instead of the sampling timer for
better accuracy.
By doing this we replace the stohastic sampling with busyness
metric derived directly from engine activity. This is context
switch interrupt driven,
On 10/04/2017 04:39 AM, Michal Wajdeczko wrote:
On Wed, 04 Oct 2017 08:13:12 +0200, Sagar Arun Kamble
wrote:
On 10/4/2017 4:25 AM, Sujaritha Sundaresan wrote:
Unifying the various seq_puts messages to the simplest one
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messag
On 10/04/2017 12:06 AM, Sagar Arun Kamble wrote:
Hi Sujaritha,
I am Unable to locate single series on patchwork for these changes.
Please send all patches together in single series with cover letter.
It will also enable CI BAT/IGT testing for the series.
Thanks
Sagar
Sorry, I was not aware
On 10/03/2017 11:13 PM, Sagar Arun Kamble wrote:
On 10/4/2017 4:25 AM, Sujaritha Sundaresan wrote:
Unifying the various seq_puts messages to the simplest one
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5: Se
Quoting Michal Wajdeczko (2017-10-03 17:36:07)
> We want to keep GuC specific code in separated files.
>
> v2: move all functions in single patch (Joonas)
> fix old checkpatch issues (Sagar)
>
> v3: rebased
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc:
== Series Details ==
Series: drm/i915: Separate RC6, RPS, Ring Frequency management
URL : https://patchwork.freedesktop.org/series/31387/
State : success
== Summary ==
Test gem_flink_race:
Subgroup flink_close:
fail -> PASS (shard-hsw) fdo#102655
fdo#102655
Quoting Michal Wajdeczko (2017-10-03 17:36:06)
> We want to keep uC specific code in separate files.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Sagar Arun Kamble
> Cc: MichaĹ Winiarski
> ---
> drivers/gpu/drm/i915/i915_debugfs.c| 1 +
> driver
Quoting Michal Wajdeczko (2017-10-03 19:28:02)
> On Tue, 03 Oct 2017 19:03:58 +0200, Chris Wilson
> wrote:
>
> > Quoting Michal Wajdeczko (2017-10-03 17:36:05)
> >> We want to keep component specific code in separate files.
> >>
> >> Suggested-by: Joonas Lahtinen
> >> Signed-off-by: Michal Waj
Quoting Sagar Arun Kamble (2017-10-04 15:07:15)
> With GuC based SLPC, frequency control will be moved to GuC and Host will
> continue to control RC6 and Ring frequency setup. This needs separate
> handling of RPS, RC6 and ring frequencies in i915 flows. We still
> continue use the *gt_powersave ro
Quoting Sagar Arun Kamble (2017-10-04 15:07:25)
> Defined new struct intel_rc6 to hold RC6 specific state and
> intel_ring_pstate to hold ring specific state.
What do you mean by ring? Probably not struct intel_ring.
For us it would be closer to intel_engine_cs_pstate, which is a bit
unwieldy but
Quoting Sagar Arun Kamble (2017-10-04 15:07:23)
> Prepared intel_update_ring_freq function to setup ring frequency
> for applicable platforms determined by macro - NEEDS_RING_FREQ_UPDATE
>
> Signed-off-by: Sagar Arun Kamble
> Cc: Imre Deak
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Radosla
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/preempt: Fix
WaEnablePreemptionGranularityControlByUMD
URL : https://patchwork.freedesktop.org/series/31394/
State : success
== Summary ==
Series 31394v1 series starting with [CI,1/9] drm/i915/preempt: Fix
WaEnablePreemption
On Tue, 2017-10-03 at 18:33 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Guc code reorg
> URL : https://patchwork.freedesktop.org/series/31340/
> State : success
I've merged the series, thanks for the patches and review.
Regards, Joonas
--
Joonas Lahtinen
Open Source T
Kernel stores the time in jiffies at which the eDP panel is turned
off. This should be obtained after the panel is off (after the
wait_panel_off). When we next attempt to turn the panel on, we
use the difference between the timestamp at which we want to turn the
panel on and timestamp at which pane
== Series Details ==
Series: drm/i915/cnl: Do not add an extra page for precaution in the Gen10 LRC
size (rev3)
URL : https://patchwork.freedesktop.org/series/31284/
State : success
== Summary ==
Series 31284v3 drm/i915/cnl: Do not add an extra page for precaution in the
Gen10 LRC size
https
== Series Details ==
Series: drm/i915: Guc code reorg
URL : https://patchwork.freedesktop.org/series/31391/
State : success
== Summary ==
Series 31391v1 drm/i915: Guc code reorg
https://patchwork.freedesktop.org/api/1.0/series/31391/revisions/1/mbox/
Test chamelium:
Subgroup dp-hpd-fa
Use a priority stored in the context as the initial value when
submitting a request. This allows us to change the default priority on a
per-context basis, allowing different contexts to be favoured with GPU
time at the expense of lower importance work. The user can adjust the
context's priority via
When we write to ELSP, it triggers a context preemption at the earliest
arbitration point (3DPRIMITIVE, some PIPECONTROLs, a few other
operations and the explicit MI_ARB_CHECK). If this is to the same
context, it triggers a LITE_RESTORE where the RING_TAIL is merely
updated (used currently to chain
Add another perma-pinned context for using for preemption at any time.
We cannot just reuse the existing kernel context, as first and foremost
we need to ensure that we can preempt the kernel context itself, so
require a distinct context id. Similar to the kernel context, we may
want to interrupt e
Move the re-enabling of MI arbitration from a per-bb w/a buffer to the
emission of the batch buffer itself.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_lrc.c | 24
1 file changed, 4 insertions(+), 20 deletions(-)
diff --git a
With preemption, we will want to "unsubmit" a request, taking it back
from the hw and returning it to the priority sorted execution list. In
order to know where to insert it into that list, we need to remember
its adjust priority (which may change even as it was being executed).
This also affects
In the next few patches, we wish to enable different features for the
scheduler, some which may subtlety change ABI (e.g. allow requests to be
reordered under different circumstances). So we need to make sure
userspace is cognizant of the changes (if they care), by which we employ
the usual method
Let the listener know that the context we just scheduled out was not
complete, and will be scheduled back in at a later point.
v2: Handle CONTEXT_STATUS_PREEMPTED in gvt by aliasing it to
CONTEXT_STATUS_OUT for the moment, gvt can expand upon the difference
later.
Signed-off-by: Chris Wilson
Cc:
From: Jeff McGee
The WA applies to all production Gen9 and requires both enabling and
whitelisting of the per-context preemption control register.
v2: Extend to Cannonlake.
Signed-off-by: Jeff McGee
Signed-off-by: Michał Winiarski
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
From: Michał Winiarski
Supporting fine-granularity preemption levels may require changes in
userspace batch buffer programming. Therefore, we need to fallback to
safe default values, rather that use hardware defaults. Userspace is
still able to enable fine-granularity, since we're whitelisting th
Quoting Patchwork (2017-10-04 16:48:31)
> == Series Details ==
>
> Series: series starting with [CI,1/9] drm/i915/preempt: Fix
> WaEnablePreemptionGranularityControlByUMD
> URL : https://patchwork.freedesktop.org/series/31389/
> State : failure
>
> == Summary ==
>
> Series 31389v1 series star
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/preempt: Fix
WaEnablePreemptionGranularityControlByUMD
URL : https://patchwork.freedesktop.org/series/31389/
State : failure
== Summary ==
Series 31389v1 series starting with [CI,1/9] drm/i915/preempt: Fix
WaEnablePreemption
BSpec indicates exactly 16752 DWORDs (17 pages), plus one page for PPHWSP.
Please
notice that, when looking at the BSpec context image table, the right filter has
to be applied (e.g. "CNL") as some rows are excluded for specific GENs.
BSpec: 1383
v2: Update count and add BSpec tag (Joonas)
v3: W
We don't want to make aggregate uc functions to be too detailed.
This will also make future patch easier.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Joonas Lahtinen
Reviewed-by: Sagar Arun Kamble
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_uc.c | 9 ++---
1
We want to keep each uC specific code in separate files.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Reviewed-by: Sagar Arun Kamble
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_huc.h | 39 +++
From: Sagar Arun Kamble
This patch adds new function intel_uc_init_mmio which will initialize
MMIO access related variables prior to uc load/init.
v2: Removed unnecessary export of guc_send_init_regs. Created
intel_uc_init_mmio that currently wraps guc_init_send_regs. (Michal)
v3 (Michal): add
This is a prerequisite to unblock next steps.
v2: correct include order (Joonas)
v3: use common function prefix (Joonas)
add kerneldoc (Michal)
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamble
Reviewed-by: Sagar Arun Kamble
Reviewed-by: Joonas La
Reviewed patches 1-6 from https://patchwork.freedesktop.org/series/31340/
Michal Wajdeczko (5):
drm/i915: Make intel_uncore.h header self-contained
drm/i915/uc: Drop unnecessary forward declaration
drm/i915/uc: Move uC fw helper code into dedicated files
drm/i915/huc: Move HuC declaration
On 10/04/2017 05:55 AM, Mika Kuoppala wrote:
Chris Wilson writes:
Looking at gem_workarounds shows us that MMCD_MISC_CTRL is not restored
following a suspend-resume cycle. This implies that MMCD_MISC_CTRL is
not stored in the context, but is an ordinary register w/a that we need to
restore d
We're trying to resolve inter-header dependencies.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_uncore.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.h
b/drivers/gp
We don't need it here.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Joonas Lahtinen
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 6966
== Series Details ==
Series: drm/i915: Separate RC6, RPS, Ring Frequency management
URL : https://patchwork.freedesktop.org/series/31387/
State : success
== Summary ==
Series 31387v1 drm/i915: Separate RC6, RPS, Ring Frequency management
https://patchwork.freedesktop.org/api/1.0/series/31387/r
On Tue, Oct 03, 2017 at 04:37:25PM -0700, Manasi Navare wrote:
> For this specific PCI device, the eDP panel requires a higher
> panel power cycle delay of 1300ms where the minimum spec
> requirement of panel power cycle delay is 500ms.
> This fix in combination with correct timestamp at which we g
On Tue, Oct 03, 2017 at 04:37:24PM -0700, Manasi Navare wrote:
> Kernel stores the time in jiffies at which the eDP panel is turned
> off. This should be obtained after the panel is off (after the
> wait_panel_off). When we next attempt to turn the panel on, we
> use the difference between the time
On Wed, 04 Oct 2017 16:23:50 +0200, Joonas Lahtinen
wrote:
On Tue, 2017-10-03 at 16:36 +, Michal Wajdeczko wrote:
This is a prerequisite to unblock next steps.
v2: correct include order (Joonas)
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Sagar Arun Kamb
Quoting Tvrtko Ursulin (2017-10-04 10:39:08)
>
> On 03/10/2017 13:50, Chris Wilson wrote:
> > trace_i915_gem_evict_everything and trace_i915_gem_ring_flush stopped
> > being used when their parent functions were removed.
> >
> > Signed-off-by: Chris Wilson
> > Reviewed-by: Tvrtko Ursulin
> Revi
With preemption, we will want to "unsubmit" a request, taking it back
from the hw and returning it to the priority sorted execution list. In
order to know where to insert it into that list, we need to remember
its adjust priority (which may change even as it was being executed).
This also affects
Use a priority stored in the context as the initial value when
submitting a request. This allows us to change the default priority on a
per-context basis, allowing different contexts to be favoured with GPU
time at the expense of lower importance work. The user can adjust the
context's priority via
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