Looks ok. I won't get around to testing this until maybe mid next week though.
On Wed, May 24, 2017 at 04:52:10PM +0200, Daniel Vetter wrote:
> Again stopping the vblank before uninstalling the irq handler is kinda
> the wrong way round, but the fb_off stuff should take care of
> disabling the ds
Hi Anusha,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc3 next-20170602]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Anusha-Srivatsa/drm-i915-cfl-Add
Patches merged to dinq.
Thanks for the reviews!
On Jun 2, 2017, 1:07 PM -0700, Rodrigo Vivi , wrote:
> Panel Power sequences for CNP is similar to Broxton,
> but with only one sequencer.
>
> Main difference from SPT is that PP_DIVISOR was removed
> and power cycle delay has been moved to PP_CONTRO
== Series Details ==
Series: Enhancement to intel_dp_aux_backlight driver (rev10)
URL : https://patchwork.freedesktop.org/series/21086/
State : success
== Summary ==
Series 21086v10 Enhancement to intel_dp_aux_backlight driver
https://patchwork.freedesktop.org/api/1.0/series/21086/revisions/10
Add heuristic to decide that AUX or PWM pin should use for
backlight brightness adjustment and modify i915 param description
to have auto, force disable, and force enable.
The heuristic to determine that using AUX pin is better than using
PWM pin is that the panel support any of the feature list h
This patch adds option to enable dynamic backlight for eDP
panel that supports this feature via DPCD register and
set minimum / maximum brightness to 0% and 100% of the
normal brightness.
Change-Id: I52f04b814bb4cd9df570ab59094ae974b9baec5b
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/d
This patch set contain 3 patches. Another 6 patches in previous version
was already merged in v7 and v9.
- First patch sets the PWM freqency to match data in panel vbt.
- Next patch adds heuristic to determine whether we should use AUX
or PWM pin to adjust panel backlight brightness.
- Last patch
Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to have
as many bits as possible for PWM duty cyle for granularity of
brightness adjustment while the frequency divisor is still
within 25% of the desired value.
Change-Id: I96221608e1288f
On Fri, Jun 2, 2017 at 11:25 AM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> > This patch adds option to enable dynamic backlight for eDP
> > panel that supports this feature via DPCD register and
> > set minimum
On Fri, Jun 2, 2017 at 10:56 AM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Fri, 2017-06-02 at 17:42 +, Pandiyan, Dhinakaran wrote:
>
> Somehow the CC's got removed in my previous reply, adding them back. See
> one additional comment below.
>
>
> > On Fri, 2017-05-26 at
== Series Details ==
Series: drm/i915/guc: Clear enable_guc_loading in case of init failure
URL : https://patchwork.freedesktop.org/series/25228/
State : success
== Summary ==
Series 25228v1 drm/i915/guc: Clear enable_guc_loading in case of init failure
https://patchwork.freedesktop.org/api/1.
And prevent calling i915_ggtt_disable_guc twice (the first when GuC init
failed, and the second time during driver unload / intel_uc_fini_hw),
and hitting the GEM_BUG_ON.
Fixes: 04f7b24eccdf ("drm/i915/guc: Assert that we switch between known
ggtt->invalidate functions")
Cc: Chris Wilson
Cc: Mich
Coffee Lake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen9 graphics based platform on top of CNP PCH.
Let's start by adding the platform definition based on previous
platforms but yet as preliminary_hw_support.
On following patches we will start adding PCI IDs
On Tue, 2017-05-30 at 15:43 -0700, Rodrigo Vivi wrote:
> From the DMC perspective the same firmware is used on
> both platforms. We haven't recieved any separated release
> specifically for Coffee Lake so let's just re-use what
> is already there for Kabylake.
>
> Signed-off-by: Rodrigo Vivi
Typ
On Fri, 2017-06-02 at 21:25 +, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> > All here is pretty much like Kabylake, expect the PCH.
> >
> > This patch exclude the addition of DMC, GuC and most workardounds since
> > they might have changes/updates.
>
Quoting Michel Thierry (2017-06-02 21:38:56)
> One thing I forgot to ask, what should I do with the error/reset
> uevents? As it is, we will only tell userspace in case of global reset.
My first thought is that we don't care to send the uevent for anything
less than a global reset. The original u
On Tue, 2017-05-30 at 15:42 -0700, Rodrigo Vivi wrote:
> All here is pretty much like Kabylake, expect the PCH.
>
> This patch exclude the addition of DMC, GuC and most workardounds since
> they might have changes/updates.
>
> v2: Take advantage of IS_GEN9_BC minimizing the needed plumbing.
>
>
Hi Dave,
Smallish (by series count) -next pull request here comprised of a few moderately
sized series'. We gained mode_valid() hooks for crtc/encoder/bridge, and now
have
a clearer seperation between irq and vblank. Additionally we cleaned up some
legacy
code by turfing drm_for_each_connector an
ops, actually I take the rv-b back, sorry
On Fri, Jun 2, 2017 at 10:31 AM, Anusha Srivatsa
wrote:
> Add PCI Ids for U Skus of Coffeelake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 10 ++
Reviewed-by: Rodrigo Vivi
On Fri, Jun 2, 2017 at 10:31 AM, Anusha Srivatsa
wrote:
> Add PCI Ids for U Skus of Coffeelake.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> include/drm/i915_pciids.h | 10 ++
> 2 files changed,
On 6/2/2017 1:16 PM, Chris Wilson wrote:
Quoting Michel Thierry (2017-05-22 18:46:24)
+ /* try engine reset first, and continue if fails */
/* Please use sentences when convenient. It looks much neater that way. */
_less_ broken English:
/*
* Try engine reset when available. We fall
== Series Details ==
Series: series starting with [1/6] drm/i915/cnp: Introduce Cannonpoint PCH.
URL : https://patchwork.freedesktop.org/series/25223/
State : success
== Summary ==
Series 25223v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/25223/revisions/1/mbo
Quoting Michel Thierry (2017-05-22 18:46:24)
> + /* try engine reset first, and continue if fails */
/* Please use sentences when convenient. It looks much neater that way. */
> + if (intel_has_reset_engine(dev_priv)) {
> + struct intel_engine_cs *engine;
> +
Most of south engine display that is in PCH is still the
same as SPT and KBP, except for this key differences:
- Backlight: Backlight programming changed in CNP PCH.
- Panel Power: Sligh programming changed in CNP PCH.
- GMBUS and GPIO: The pin mapping has changed in CNP PCH.
All of these changes
On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.
v2: Don't drop "_BXT" as the indicator of the f
Panel Power sequences for CNP is similar to Broxton,
but with only one sequencer.
Main difference from SPT is that PP_DIVISOR was removed
and power cycle delay has been moved to PP_CONTROL.
v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
as on Broxton. (Found by DK)
v3: Impr
RAWCLK_FREQ register has changed for platforms with CNP+.
[29:26] This field provides the denominator for the fractional
part of the microsecond counter divider. The numerator
is fixed at 1. Program this field to the denominator of
the fractional portion of reference frequ
From: Dhinakaran Pandiyan
The first two bytes of PCI ID for CNP_LP PCH are the same as that of
SPT_LP. We should really be looking at the first 9 bits instead of the
first 8 to identify platforms, although this seems to have not caused any
problems on earlier platforms. Introduce a 9 bit extended
Split out BXT and CNP's setup_backlight(),enable_backlight(),
disable_backlight() and hz_to_pwm() into
two separate functions instead of reusing BXT function.
Reuse set_backlight() and get_backlight() since they have
no reference to the utility pin.
v2: Reuse BXT functions with controller 0 inste
Hi Dave,
Here's this week's fixes pull. Most noteworthy is the drm_unplug_dev change.
We've previously had discussion around cleanup on unplug for rockchip, but that
was mostly an academic issue (they wanted to unbind/bind at runtime). At the
time, this usecase was determined not to warrant the com
On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> This patch adds option to enable dynamic backlight for eDP
> panel that supports this feature via DPCD register and
> set minimum / maximum brightness to 0% and 100% of the
> normal brightness.
>
> Signed-off-by: Puthikorn Voravoot
From: Jani Nikula
Date: Wed, 31 May 2017 18:50:43 +0300
> From: Chris Wilson
>
> An error during suspend (e100e_pm_suspend),
...
> lead to complete failure:
...
> The unwind failures stems from commit 2800209994f8 ("e1000e: Refactor PM
> flows"), but it may be a later patch that introduced th
On Thu, Apr 06, 2017 at 12:15:24PM -0700, Rodrigo Vivi wrote:
> From: Ville Syrjälä
>
> Add support for reading out the cdclk frequency from the hardware on
> CNL. Very similar to BXT, with a few new twists and turns:
> * the PLL is now called CDCLK PLL, not DE PLL
> * reference clock can be 24 M
On Fri, 2017-06-02 at 17:42 +, Pandiyan, Dhinakaran wrote:
Somehow the CC's got removed in my previous reply, adding them back. See
one additional comment below.
> On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> > Add heuristic to decide that AUX or PWM pin should use for
== Series Details ==
Series: series starting with [1/3] drm/i915/cfl: Add Coffee Lake PCI IDs for U
Sku.
URL : https://patchwork.freedesktop.org/series/25219/
State : failure
== Summary ==
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK inclu
On Thu, Jun 1, 2017 at 11:17 PM, Saarinen, Jani wrote:
> HI,
>> -Original Message-
>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
>> Of Vivi, Rodrigo
>> Sent: Friday, June 2, 2017 2:05 AM
>> To: intel-gfx@lists.freedesktop.org; Vetter, Daniel
>> ; Nikula, Jan
On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> Add heuristic to decide that AUX or PWM pin should use for
> backlight brightness adjustment and modify i915 param description
> to have auto, force disable, and force enable.
>
> The heuristic to determine that using AUX pin is be
Add PCI Ids for H Sku by following the BSpec.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 6 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i9
Add PCI Ids for U Skus of Coffeelake.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
in
Add PCI Ids for S Sku following the BSpec.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/drm/i915_pciids.h | 6 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/
On 04/06/2017 12:15 PM, Rodrigo Vivi wrote:
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is also the new Spec style what makes the review much
more easy and straight
Hi,
> > When i915's dma-buf's release() callback is called it will try to
> > free the gem object associated with the dma-buf if its ref count is
> > 0. But in our case the ref count is 1 so no free callback is called
> > so we can not release allocations there.
Why the ref count is one? Who h
On Fri, 2 Jun 2017 09:31:41 +
"Chen, Xiaoguang" wrote:
> >-Original Message-
> >From: Alex Williamson [mailto:alex.william...@redhat.com]
> >Sent: Friday, June 02, 2017 11:35 AM
> >To: Chen, Xiaoguang
> >Cc: kra...@redhat.com; ch...@chris-wilson.co.uk; intel-
> >g...@lists.freedeskto
Quoting Mika Kuoppala (2017-06-02 13:38:34)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2017-06-02 13:02:57)
> >> Chris Wilson writes:
> >>
> >> > In commit 5763ff04dc4e ("drm/i915: Avoid GPU stalls from kswapd") we
> >> > stopped direct reclaim and kswapd from triggering GPU/client sta
Quoting Joonas Lahtinen (2017-06-02 11:19:13)
> On ke, 2017-05-31 at 10:35 +0800, Weinan Li wrote:
> > I915_GEM_GET_APERTURE ioctl is used to probe aperture size from userspace.
> > In gvt environment, each vm only use the ballooned part of aperture, so we
> > should return the correct available ap
Chris Wilson writes:
> Quoting Mika Kuoppala (2017-06-02 13:02:57)
>> Chris Wilson writes:
>>
>> > In commit 5763ff04dc4e ("drm/i915: Avoid GPU stalls from kswapd") we
>> > stopped direct reclaim and kswapd from triggering GPU/client stalls
>> > whilst running (by restricting the objects they c
On 31/05/17 22:41, Andy Shevchenko wrote:
> acpi_evaluate_dsm() and friends take a pointer to a raw buffer of 16
> bytes. Instead we convert them to use guid_t type. At the same time we
> convert current users.
>
> acpi_str_to_uuid() becomes useless after the conversion and it's safe to
> get rid
Quoting Mika Kuoppala (2017-06-02 13:02:57)
> Chris Wilson writes:
>
> > In commit 5763ff04dc4e ("drm/i915: Avoid GPU stalls from kswapd") we
> > stopped direct reclaim and kswapd from triggering GPU/client stalls
> > whilst running (by restricting the objects they could reap to be idle).
> >
> >
Chris Wilson writes:
> In commit 5763ff04dc4e ("drm/i915: Avoid GPU stalls from kswapd") we
> stopped direct reclaim and kswapd from triggering GPU/client stalls
> whilst running (by restricting the objects they could reap to be idle).
>
> However with abusive GPU usage, it becomes quite easy to
Actually CC'ing Petri. When adding Cc's, it's usually better to Cc the
whole series (and make sure Cc's were effective).
On ke, 2017-05-31 at 10:00 -0700, Antonio Argenziano wrote:
> The IGT test suite aims at testing the functionalities of the i915
> graphics driver. Because of an increasing effo
On to, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> Cannonlake also supports slice power gating on devices with more
> than one slice as SKL. Let's assume that this is the same for SKL+
> and exclude BXT only.
>
> v2: Also remove KBL.
>
Bspec: 12566
> Signed-off-by: Rodrigo Vivi
Reviewed-
On to, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> All registers and default configuration are the same for Skylake
> and Cannonlake.
>
> v2: Don't apply Wa for platforms without MOCS. (Paulo)
>
> Cc: Paulo Zanoni
> Signed-off-by: Rodrigo Vivi
Bspec: 12239
> @@ -191,8 +191,8 @@ static bo
On Thu, Jun 01, 2017 at 05:51:27PM -0700, Manasi Navare wrote:
> Validate the compliance test link parameters when the compliance
> test dpcd registers are read. Also validate them in compute_config
> before using them since the max values might have been reduced
> due to link training fallback.
>
On ke, 2017-05-31 at 10:49 +0800, Zhenyu Wang wrote:
> On 2017.05.30 11:37:50 +0300, Joonas Lahtinen wrote:
> >
> > I just noticed there is INTEL_VGT_IF_VERSION when I was looking to make
> > sure that vgt_if is zeroed. Neither the version is incremented nor do I
> > see VGT_PVINFO_PAGE getting ze
On to, 2017-06-01 at 14:33 +0100, Chris Wilson wrote:
> I tried __GFP_NORETRY in the belief that __GFP_RECLAIM was effective. It
> struggles with handling reclaim via kswapd (through inconsistency within
> throttle_direct_reclaim() and even then the race between multiple
> allocators makes the two
On to, 2017-06-01 at 14:33 +0100, Chris Wilson wrote:
> In commit 5763ff04dc4e ("drm/i915: Avoid GPU stalls from kswapd") we
> stopped direct reclaim and kswapd from triggering GPU/client stalls
> whilst running (by restricting the objects they could reap to be idle).
>
> However with abusive GPU
On ke, 2017-05-31 at 10:35 +0800, Weinan Li wrote:
> I915_GEM_GET_APERTURE ioctl is used to probe aperture size from userspace.
> In gvt environment, each vm only use the ballooned part of aperture, so we
> should return the correct available aperture size exclude the reserved part
> by balloon.
>
On 06/04/2017 20:15, Rodrigo Vivi wrote:
From: Ben Widawsky
Some commit message is needed, maybe just copy&paste the comment from below.
Signed-off-by: Ben Widawsky
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_lrc.c | 19 +++
1 file changed, 15 insertions
On 06/04/2017 20:15, Rodrigo Vivi wrote:
From: Michel Thierry
Some commit message needed just to satisfy the form.
v2: rebased to intel_lr_indirect_ctx_offset
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_lrc.c | 5 +
1 file changed, 5 i
>-Original Message-
>From: Alex Williamson [mailto:alex.william...@redhat.com]
>Sent: Friday, June 02, 2017 11:35 AM
>To: Chen, Xiaoguang
>Cc: kra...@redhat.com; ch...@chris-wilson.co.uk; intel-
>g...@lists.freedesktop.org; linux-ker...@vger.kernel.org;
>zhen...@linux.intel.com; Lv, Zhiy
On Fri, 02 Jun 2017, Jani Nikula wrote:
> On Fri, 02 Jun 2017, Manasi Navare wrote:
>> Validate the compliance test link parameters when the compliance
>> test dpcd registers are read. Also validate them in compute_config
>> before using them since the max values might have been reduced
>> due to
> struct vfio_vgpu_surface_info {
> __u64 start;
> __u32 width;
> __u32 height;
> __u32 stride;
> __u32 size;
> __u32 x_pos;
> __u32 y_pos;
> __u32 padding;
> /* Only used when VFIO_VGPU_SURFACE_DMABUF_* flags set */
>
On Fri, 02 Jun 2017, Manasi Navare wrote:
> Validate the compliance test link parameters when the compliance
> test dpcd registers are read. Also validate them in compute_config
> before using them since the max values might have been reduced
> due to link training fallback.
>
> Signed-off-by: Man
On Fri, 02 Jun 2017, Manasi Navare wrote:
> This function now takes the link rate and lane ocunt to be validated
> as an argument so that this can be used for validating even the
> compliance test link parameters.
>
> Signed-off-by: Manasi Navare
> Cc: Ville Syrjala
> Cc: Jani Nikula
Reviewed-
On Thu, 01 Jun 2017, Ville Syrjälä wrote:
> On Thu, Jun 01, 2017 at 05:47:45PM +0300, Jani Nikula wrote:
>> On Thu, 01 Jun 2017, ville.syrj...@linux.intel.com wrote:
>> > From: Ville Syrjälä
>> >
>> > Pass down the correct acquire context to the pipe A quirk load detect
>> > hack during display r
On Thu, 01 Jun 2017, "Pandiyan, Dhinakaran"
wrote:
> Based on your clarification the second option feels like the right
> choice, with a relevant comment in code. Like you said, we get to
> retain BXT register definitions and clarify that the register is on a
> PCH for CNP.
Ack. We can also clar
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