On Tuesday, April 18, 2017 9:56:14 AM PDT Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Engine discovery uAPI allows userspace to probe for engine
> configuration and features without needing to maintain the
> internal PCI id based database.
I don't understand why I would want to query the ex
Hi Logan,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.11-rc7 next-20170418]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Logan-Gunthorpe/dma-buf-Rename-dma-ops-to
On 18/04/17 17:26, Daniele Ceraolo Spurio wrote:
On 18/04/17 13:23, Michel Thierry wrote:
From: Arun Siluvery
GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be saved is controlled by
flags. We provide a minimal set of regist
On 18/04/17 13:23, Michel Thierry wrote:
From: Arun Siluvery
GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be saved is controlled by
flags. We provide a minimal set of registers that we want GuC to save and
restore. This is
== Series Details ==
Series: dma-buf: Rename dma-ops to prevent conflict with kunmap_atomic macro
URL : https://patchwork.freedesktop.org/series/23207/
State : failure
== Summary ==
LD drivers/pci/pcie/pcieportdrv.o
LD [M] sound/pci/hda/snd-hda-codec-generic.o
LD sound/pci/bui
Seeing the kunmap_atomic dma_buf_op shares the same name with a macro
in higmem.h, the former can be aliased if any dma-buf user includes
that header.
I'm personally trying to include highmem.h inside scatterlist.h and this
breaks the dma-buf code proper.
Christoph Hellwig suggested [1] renaming
== Series Details ==
Series: Enhancement to intel_dp_aux_backlight driver (rev3)
URL : https://patchwork.freedesktop.org/series/21086/
State : warning
== Summary ==
Series 21086v3 Enhancement to intel_dp_aux_backlight driver
https://patchwork.freedesktop.org/api/1.0/series/21086/revisions/3/mb
Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to match
that frequency as close as possible.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 56 +++
1 file changed, 56
Some panel will default to zero brightness when turning the
panel off and on again. This patch stores last brightness level
before turning off and set them back when panel is turning on.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 2 ++
1 file change
Currently the intel_dp_aux_backlight driver requires eDP panel
to not also support backlight adjustment via PWM pin to use
this driver.
This force the eDP panel that support both ways of backlight
adjustment to do it via PWM pin.
This patch adds the new prefer DPCD mode in the i915_param
to make
intel_dp_aux_enable_backlight() assumed that the register
BACKLIGHT_BRIGHTNESS_CONTROL_MODE can only has value 01
(DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET) when initialize.
This patch fixed that by handling all cases of that register.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/
This patch adds the following definition
- Bit mask for EDP_PWMGEN_BIT_COUNT and min/max cap
register which only use bit 0:4
- Base frequency (27 MHz) for backlight PWM frequency
generator.
Signed-off-by: Puthikorn Voravootivat
---
include/drm/drm_dp_helper.h | 2 ++
1 file changed, 2 insert
This patch enables dynamic backlight by default for eDP
panel that supports this feature via DPCD register and
set minimum / maximum brightness to 0% and 100% of the
normal brightness.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 31 ++
Rebase since this is not applied cleanly now.
This patch set contain 6 patches.
- First two patches allow enable DPCD backlight control when panel
can also do that via PWM pin and fix the usage of enable register.
- Next patch adds enable DBC by default
- Next patch makes the driver restore last
This test got inadvertently disabled by commit 83884e97 (Restore
"lib: Open debugfs files for the given DRM device").
Cc: Jeff McGee
Cc: Chris Wilson
Signed-off-by: Oscar Mateo
---
tests/pm_sseu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/pm_sseu.c b/tests/pm
On Tue, Apr 18, 2017 at 03:01:02PM -0700, Michel Thierry wrote:
>
>
> On 18/04/17 14:40, Chris Wilson wrote:
> >>+ /* try engine reset first, and continue if fails; look mom, no mutex! */
> >>+ if (intel_has_reset_engine(dev_priv) && !(engine_mask & (engine_mask -
> >>1))) {
> >
> >if (has_r
On 18/04/17 16:06, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 02:36:14PM -0700, Michel Thierry wrote:
On 18/04/17 14:20, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:32PM -0700, Michel Thierry wrote:
@@ -1329,10 +1331,29 @@ static int gen8_emit_bb_start(struct
drm_i915_gem_request *re
On Tue, Apr 18, 2017 at 02:36:14PM -0700, Michel Thierry wrote:
>
> On 18/04/17 14:20, Chris Wilson wrote:
> >On Tue, Apr 18, 2017 at 01:23:32PM -0700, Michel Thierry wrote:
> >>@@ -1329,10 +1331,29 @@ static int gen8_emit_bb_start(struct
> >>drm_i915_gem_request *req,
> >>req->ctx->p
On 18/04/17 14:40, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:19PM -0700, Michel Thierry wrote:
From: Arun Siluvery
This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series. The
On Tue, Apr 18, 2017 at 01:23:19PM -0700, Michel Thierry wrote:
> From: Arun Siluvery
>
> This is a preparatory patch which modifies error handler to do per engine
> hang recovery. The actual patch which implements this sequence follows
> later in the series. The aim is to prepare existing recove
On 18/04/17 14:20, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:32PM -0700, Michel Thierry wrote:
@@ -1329,10 +1331,29 @@ static int gen8_emit_bb_start(struct
drm_i915_gem_request *req,
req->ctx->ppgtt->pd_dirty_rings &=
~intel_engine_flag(req->engine);
}
-
On Tue, Apr 18, 2017 at 01:23:32PM -0700, Michel Thierry wrote:
> @@ -1329,10 +1331,29 @@ static int gen8_emit_bb_start(struct
> drm_i915_gem_request *req,
> req->ctx->ppgtt->pd_dirty_rings &=
> ~intel_engine_flag(req->engine);
> }
>
> - cs = intel_ring_begin(req, 4);
>
On 18/04/17 13:23, Michel Thierry wrote:
For watchdog / media reset, the firmware must know the address of the shared
data page (the first page of the default context).
This information should be in DWORD 9 of the GUC_CTL structure.
v2: Use guc_ggtt_offset (Chris).
Store the ggtt offset of th
On Tue, Apr 18, 2017 at 05:56:15PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Building on top of the previous patch which exported the concept
> of engine classes and instances, we can also use this instead of
> the current awkward engine selection uAPI.
>
> This is primarily intere
== Series Details ==
Series: Gen8+ engine-reset (rev2)
URL : https://patchwork.freedesktop.org/series/21868/
State : success
== Summary ==
Series 21868v2 Gen8+ engine-reset
https://patchwork.freedesktop.org/api/1.0/series/21868/revisions/2/mbox/
Test gem_exec_suspend:
Subgroup basic-s
From: Arun Siluvery
This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_params.c | 4 +
From: Daniele Ceraolo Spurio
The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV
register the GuC can use to restore the provided whitelist when an
engine reset via GuC (which we still don't support) is triggered.
We're currently adding the mmio_base of the engine to the absolu
From: Arun Siluvery
GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be saved is controlled by
flags. We provide a minimal set of registers that we want GuC to save and
restore. This is not an issue in case of engine reset as drive
Check that we can reset specific engines, also check the fallback to
full reset if something didn't work.
v2: rebase.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 147 +++
1 file changed, 147 insertions(+)
diff --git a/drivers/gpu/drm
Users/tests relying on the total reset count will start seeing a smaller
number since most of the hangs can be handled by engine reset.
Note that if reset engine x, context a running on engine y will be unaware
and unaffected.
To start the discussion, include just a total engine reset count. If it
This patch adds per engine reset and recovery (TDR) support when GuC is
used to submit workloads to GPU.
In the case of i915 directly submission to ELSP, driver manages hang
detection, recovery and resubmission. With GuC submission these tasks
are shared between driver and GuC. i915 is still respo
*** General ***
Watchdog timeout (or "media engine reset") is a feature that allows
userland applications to enable hang detection on individual batch buffers.
The detection mechanism itself is mostly bound to the hardware and the only
thing that the driver needs to do to support this form of hang
Save the watchdog threshold (in us) as part of the engine state.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
Emit the required commands into the ring buffer for starting and
stopping the watchdog timer before/after batch buffer start during
batch buffer submission.
v2: Support watchdog threshold per context engine, merge lri commands,
and move watchdog commands emission to emit_bb_start. Request space of
These patches add the reset-engine feature from Gen8. This is also
referred to as Timeout detection and recovery (TDR). This complements to
the full gpu reset feature available in i915 but it only allows to reset a
particular engine instead of all engines thus providing a light weight
engine reset
Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do the conversion to
'timestamps'.
The recommended default watchdog threshold for video engines is 6 us,
For watchdog / media reset, the firmware must know the address of the shared
data page (the first page of the default context).
This information should be in DWORD 9 of the GUC_CTL structure.
v2: Use guc_ggtt_offset (Chris).
Store the ggtt offset of the default ctx as we needed for
suspend/resume
From firmware v8.8, GuC provides the count of media engine resets
(watchdog timeout). This information is available in the GuC shared
context data struct, which resides in the first page of the default
(kernel) lrc context.
Since GuC handled engine resets are transparent for kernel and user,
provi
From: Mika Kuoppala
To perform engine reset we first disable engine to capture its state. This
is done by issuing a reset request. Because we are reusing existing
infrastructure, again when we actually reset an engine, reset function
checks engine mask and issues reset request again which is unne
From: Arun Siluvery
This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if necessary. This is only supported
from Gen8 onwards.
Hangchecker determines which engines a
From: Arun Siluvery
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_pa
From: Arun Siluvery
Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.
A follow-up patch will provide this information in debugfs.
v
As all other functions related to resetting engines are using
reset_engine.
v2: remove _request_ and use start/cancel instead (Chris)
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_uncore.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Arun Siluvery
This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series. The aim is to prepare existing recovery function to
adapt to this new function where applicable (which fails at
It has been replaced by I915_RESET_BACKOFF / I915_RESET_HANDOFF.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5c81de102e8..e06af46f5a5
From: Arun Siluvery
A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they are expected to trigger reset; these counts are checked before
and after the test to ensure the same.
v2: Include reset engi
On Tue, Apr 18, 2017 at 05:56:14PM +0100, Tvrtko Ursulin wrote:
> +enum drm_i915_gem_engine_class {
> + DRM_I915_ENGINE_CLASS_OTHER = 0,
> + DRM_I915_ENGINE_CLASS_RENDER = 1,
> + DRM_I915_ENGINE_CLASS_COPY = 2,
> + DRM_I915_ENGINE_CLASS_VIDEO_DECODE = 3,
> + DRM_I915_ENGINE_CLAS
== Series Details ==
Series: New engine discovery and execbuffer2 engine selection uAPI
URL : https://patchwork.freedesktop.org/series/23189/
State : failure
== Summary ==
Series 23189v1 New engine discovery and execbuffer2 engine selection uAPI
https://patchwork.freedesktop.org/api/1.0/series
From: Tvrtko Ursulin
Building on top of the previous patch which exported the concept
of engine classes and instances, we can also use this instead of
the current awkward engine selection uAPI.
This is primarily interesting for the VCS engine selection which
is a) currently done via disjoint set
From: Tvrtko Ursulin
Inspired by the recent introduction of the engine class and instance concept,
and a chat with Chris Wilson about a potential unification of PCI id based
device discovery across multiple userspace components, I have cooked up two
patches to gather some opinions on whether this
From: Tvrtko Ursulin
Engine discovery uAPI allows userspace to probe for engine
configuration and features without needing to maintain the
internal PCI id based database.
This enables removal of code duplications across userspace
components.
Probing is done via the new DRM_IOCTL_I915_GEM_ENGINE
On 18/04/17 09:50 AM, Konrad Rzeszutek Wilk wrote:
> I am not sure if you know, but you can add on each patch the respective
> maintainer via 'CC'. That way you can have certain maintainers CCed only
> on the subsystems they cover. You put it after (or before) your SoB and
> git send-email happil
On Tue, Apr 18, 2017 at 10:40:21AM -0400, Sean Paul wrote:
> On Tue, Apr 18, 2017 at 03:29:29PM +0300, Laurent Pinchart wrote:
> > Hi Daniel,
> >
> > Thank you for the patch.
> >
> > On Tuesday 18 Apr 2017 14:11:20 Daniel Vetter wrote:
> > > All the error codes we (ab)use are strictly not the rig
On Tue, Apr 18, 2017 at 02:10:07PM +, Lofstedt, Marta wrote:
> Sorry Peter, I still see regression on the Core2 machine, with your patch.
>
Blergh, ok. I'll see if I can dig out an actual Core2 machine somewhere.
I should have enough parts about.
__
On Tue, Apr 18, 2017 at 09:42:20AM -0600, Logan Gunthorpe wrote:
>
>
> On 18/04/17 08:27 AM, Konrad Rzeszutek Wilk wrote:
> > Interesting that you didn't CC any of the maintainers. Could you
> > do that in the future please?
>
> Please read the cover letter. The distribution list for the patchs
On 18/04/17 12:44 AM, Daniel Vetter wrote:
> On Thu, Apr 13, 2017 at 04:05:18PM -0600, Logan Gunthorpe wrote:
>> This is a single straightforward conversion from kmap to sg_map.
>>
>> Signed-off-by: Logan Gunthorpe
>
> Acked-by: Daniel Vetter
>
> Probably makes sense to merge through some oth
On 18/04/17 08:27 AM, Konrad Rzeszutek Wilk wrote:
> Interesting that you didn't CC any of the maintainers. Could you
> do that in the future please?
Please read the cover letter. The distribution list for the patchset
would have been way too large to cc every maintainer (even as limited as
it
On Tue, Apr 18, 2017 at 03:29:29PM +0300, Laurent Pinchart wrote:
> Hi Daniel,
>
> Thank you for the patch.
>
> On Tuesday 18 Apr 2017 14:11:20 Daniel Vetter wrote:
> > All the error codes we (ab)use are strictly not the right ones (since
> > they're all for the vfs, and the only thing we're allo
On Tue, Apr 18, 2017 at 02:13:59PM +, David Laight wrote:
> From: Logan Gunthorpe
> > Sent: 13 April 2017 23:05
> > Straightforward conversion to the new helper, except due to
> > the lack of error path, we have to warn if unmapable memory
> > is ever present in the sgl.
Interesting that you d
Hi Chris,
Ping for your feedback on my comments. Please help to make it to move forward.
:)
Thanks
Chuanxiao
> -Original Message-
> From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
> Behalf Of Dong, Chuanxiao
> Sent: Thursday, April 13, 2017 7:03 PM
> To: Chri
> -Original Message-
> From: Peter Zijlstra [mailto:pet...@infradead.org]
> Sent: Thursday, April 13, 2017 4:24 PM
> To: Martin Peres
> Cc: Lofstedt, Marta ;
> pasha.tatas...@oracle.com; intel-gfx@lists.freedesktop.org; Thomas
> Gleixner
> Subject: Re: freedesktop bug id: 100548, bisect
On Tue, Apr 18, 2017 at 3:12 PM, Chris Wilson wrote:
> Avoid having too large a stack by creating the fake struct inode/file on
> the heap instead.
>
> drivers/gpu/drm/i915/selftests/mock_drm.c: In function 'mock_file':
> drivers/gpu/drm/i915/selftests/mock_drm.c:46:1: error: the frame size of 132
On Tue, Apr 18, 2017 at 1:54 PM, Hans de Goede wrote:
> Several Cherry Trail devices (all of which ship with Windows 10) hide the
> LPSS PWM controller in ACPI, typically the _STA method looks like this:
>
> Method (_STA, 0, NotSerialized) // _STA: Status
> {
> If (OSID == One)
>
== Series Details ==
Series: drm/i915/selftests: Allocate inode/file dynamically
URL : https://patchwork.freedesktop.org/series/23183/
State : success
== Summary ==
Series 23183v1 drm/i915/selftests: Allocate inode/file dynamically
https://patchwork.freedesktop.org/api/1.0/series/23183/revisio
Avoid having too large a stack by creating the fake struct inode/file on
the heap instead.
drivers/gpu/drm/i915/selftests/mock_drm.c: In function 'mock_file':
drivers/gpu/drm/i915/selftests/mock_drm.c:46:1: error: the frame size of 1328
bytes is larger than 1280 bytes [-Werror=frame-larger-than=]
In at least SKL and GLK (possibly other devices too), using a cursor
plane to scan out an fb might result in a different pipe crc than when
using a regular plane at the same position with the same fb while using
the CSC logic to limit the color range. The differences could be caused
by the cursor p
== Series Details ==
Series: drm/cma-helper: Return ENOENT for "no such gem obj"
URL : https://patchwork.freedesktop.org/series/23172/
State : failure
== Summary ==
Series 23172v1 drm/cma-helper: Return ENOENT for "no such gem obj"
https://patchwork.freedesktop.org/api/1.0/series/23172/revisio
On Tue, Apr 18, 2017 at 12:41:14PM +0100, Tvrtko Ursulin wrote:
> +static void headless(int fd, uint32_t handle)
> +{
> + const struct intel_execution_engine *e = &intel_execution_engines[0];
> + unsigned int nr_connected = 0;
> + drmModeConnector *connector;
> + drmModeRes *res;
>
Hi Daniel,
Thank you for the patch.
On Tuesday 18 Apr 2017 14:11:20 Daniel Vetter wrote:
> All the error codes we (ab)use are strictly not the right ones (since
> they're all for the vfs, and the only thing we're allowed to do from
> an ioctl is EINVAL). But ENOENT is the common error code for fa
Chris Wilson writes:
> On Thu, Apr 13, 2017 at 02:15:27PM +0300, Mika Kuoppala wrote:
>> Previously with commit a9c1f90c8e17
>> ("drm/i915: Don't mask EI UP interrupt on IVB|SNB") certain,
>> seemingly unrelated bit (GEN6_PM_RP_UP_EI_EXPIRED) was needed
>> to be unmasked for IVB and SNB in order
All the error codes we (ab)use are strictly not the right ones (since
they're all for the vfs, and the only thing we're allowed to do from
an ioctl is EINVAL). But ENOENT is the common error code for failed to
look up an object throughout drm, so let's use it in the cma helpers,
too.
Cc: Laurent P
Patchwork writes:
> == Series Details ==
>
> Series: drm/i915: Fix system hang with EI UP masked on Haswell
> URL : https://patchwork.freedesktop.org/series/22991/
> State : failure
>
> == Summary ==
>
> Series 22991v1 drm/i915: Fix system hang with EI UP masked on Haswell
> https://patchwork.f
The INT0002 device is necessary to clear wakeup interrupt sources
on Cherry Trail devices, without it we get nobody cared IRQ msgs
and some systems don't properly resume at all without it.
Signed-off-by: Hans de Goede
---
Changes in v6:
-This is a new patch in v6 of this patch-set
---
drivers/ac
Just like on Cherry Trail, on some Bay Trail Windows 10 tablets we
need to enable the PWM controller to get working backlight even
though _STA returns 0.
Add an entry for the the Bay Trail PWM controller to list of
always-present devices to fix backlight control not working on
some Bay Trail devic
Several Cherry Trail devices (all of which ship with Windows 10) hide the
LPSS PWM controller in ACPI, typically the _STA method looks like this:
Method (_STA, 0, NotSerialized) // _STA: Status
{
If (OSID == One)
{
Return (Zero)
}
Return (0x0F)
From: Tvrtko Ursulin
Check that no-op execution speed is the same in headless mode
and with the display active.
v2:
* Set graphics mode for the test to disable blanking. (Imre)
* Use igt stats framework as suggested by Chris.
Signed-off-by: Tvrtko Ursulin
Bugzilla: https://bugs.freedesktop.o
Hi,
> [Zhang, Xiong Y] Thanks for your teach and propose.
> For smbios, could you teach me which type and field could be used ?
qemu adds a specific subsystem id to all virtual devices, so you can use
that to figure you are running on qemu. One good candidate to check is
the host bridge (easy
== Series Details ==
Series: drm/i915: Fix GCC 4.4 build issue with __intel_wait_for_register_fw
(rev2)
URL : https://patchwork.freedesktop.org/series/23020/
State : failure
== Summary ==
Series 23020v2 drm/i915: Fix GCC 4.4 build issue with
__intel_wait_for_register_fw
https://patchwork.fre
On Tue, Apr 18, 2017 at 11:52:11AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Move the BUILD_BUG_ONs for busy-wait duration outside the
> _wait_for_atomic macro as discussed on the mailing list.
>
> v2: Simplify the macro by omitting the ret__ local. (Chris Wilson)
>
> Signed-off-b
From: Tvrtko Ursulin
Move the BUILD_BUG_ONs for busy-wait duration outside the
_wait_for_atomic macro as discussed on the mailing list.
v2: Simplify the macro by omitting the ret__ local. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Michal Wajdeczko
Fixes: 1d1a9774e404 ("drm/i91
On Tue, Apr 18, 2017 at 11:29:34AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Verify that we reject attempts to create object larger than
> INT_MAX * PAGE_SIZE since i915 currently cannot support that.
>
> Also removed the skip on simulation since I don't know why
> would that be ne
On 18/04/17 12:14, Dan Carpenter wrote:
On Tue, Apr 18, 2017 at 10:58:44AM +0300, Jani Nikula wrote:
On Mon, 17 Apr 2017, Dan Carpenter wrote:
On Fri, Apr 14, 2017 at 08:13:43PM -, Patchwork wrote:
== Series Details ==
Series: drm/i915: uninitialized value on error path (rev3)
URL : ht
From: Tvrtko Ursulin
Verify that we reject attempts to create object larger than
INT_MAX * PAGE_SIZE since i915 currently cannot support that.
Also removed the skip on simulation since I don't know why
would that be needed here.
v2: Removed basic tag and adjusted commit msg.
Signed-off-by: Tvr
From: Michel Dänzer
This allows making the master screen's pixmap_dirty_list entries
explicitly reflect that we're now tracking the root window instead of
the screen pixmap, in order to allow Present page flipping on master
outputs while there are active slave outputs.
Define HAS_DIRTYTRACKING_D
From: Michel Dänzer
Signed-off-by: Michel Dänzer
---
Chris / Ilia / Ben, this should be manageable for the intel/nouveau
drivers, right?
src/amdgpu_drv.h | 26 ++
src/amdgpu_kms.c | 18 +-
src/drmmode_display.c | 8 ++--
3 files changed,
On Mon, Apr 17, 2017 at 11:39:45AM +0100, Daniel Stone wrote:
> Hi Sean,
>
> On 14 April 2017 at 16:47, Sean Paul wrote:
> > On Mon, Apr 10, 2017 at 12:05:43PM -0400, Sean Paul wrote:
> >> Add a bit more colour to the -misc branch explanations, and add a merge
> >> timeline
> >> similar to the c
On Thu, Apr 13, 2017 at 12:54:22PM +0300, Jari Tahvanainen wrote:
> Daniel has posted empty feat_profile.json as template to be used.
> This is my understanding about the features and what tests are covering those.
>
> Usage: piglit summary feature json-filename output-directory results-directory
On Tue, 18 Apr 2017, Dan Carpenter wrote:
> On Tue, Apr 18, 2017 at 10:58:44AM +0300, Jani Nikula wrote:
>> On Mon, 17 Apr 2017, Dan Carpenter wrote:
>> > On Fri, Apr 14, 2017 at 08:13:43PM -, Patchwork wrote:
>> >> == Series Details ==
>> >>
>> >> Series: drm/i915: uninitialized value on er
Hi all,
First slice of 4.13 features:
new uabi:
- extend error state dumping to include non-batch buffers requested by
userspace (Chris), so that mesa gets more useful error state dumps
- reapply the link status patch, for handlig dp link failures
(Manasi). This needs updated -modesetting to
On Tue, Apr 18, 2017 at 10:58:44AM +0300, Jani Nikula wrote:
> On Mon, 17 Apr 2017, Dan Carpenter wrote:
> > On Fri, Apr 14, 2017 at 08:13:43PM -, Patchwork wrote:
> >> == Series Details ==
> >>
> >> Series: drm/i915: uninitialized value on error path (rev3)
> >> URL : https://patchwork.fre
On Mon, 2017-04-10 at 17:49 +0200, Hans de Goede wrote:
> Several cherrytrail devices (all of which ship with windows 10) hide
> the
> lpss pwm controller in ACPI, typically the _STA method looks like
> this:
CherryTrail
PWM
LPSS
>
> Method (_STA, 0, NotSerialized) // _STA: Status
> {
>
== Series Details ==
Series: Introduce common scatterlist map function
URL : https://patchwork.freedesktop.org/series/23149/
State : success
== Summary ==
Series 23149v1 Introduce common scatterlist map function
https://patchwork.freedesktop.org/api/1.0/series/23149/revisions/1/mbox/
Test gem
On Mon, 17 Apr 2017, Dan Carpenter wrote:
> On Fri, Apr 14, 2017 at 08:13:43PM -, Patchwork wrote:
>> == Series Details ==
>>
>> Series: drm/i915: uninitialized value on error path (rev3)
>> URL : https://patchwork.freedesktop.org/series/23038/
>> State : success
>
> These patchwork emails
This conversion is a bit complicated. We modiy the read_fifo,
write_fifo and copy_page functions to take a scatterlist instead of a
page. Thus we can use sg_map instead of kmap_atomic. There's a bit of
accounting that needed to be done for the offset for this to work.
(Seeing sg_map takes care of t
Conversion of a couple kmap_atomic instances to the sg_map helper
function.
However, it looks like there was a bug in the original code: the source
scatter lists offset (t->offset) was passed to ablkcipher_get which
added it to the destination address. This doesn't make a lot of
sense, but t->offs
This patch introduces functions which kmap the pages inside an sgl. Two
variants are provided: one if an offset is required and one if the
offset is zero. These functions replace a common pattern of
kmap(sg_page(sg)) that is used in about 50 places within the kernel.
The motivation for this work i
On 04/14/2017 06:03 PM, Logan Gunthorpe wrote:
>
>
> On 14/04/17 02:39 AM, Christoph Hellwig wrote:
>> On Thu, Apr 13, 2017 at 04:05:22PM -0600, Logan Gunthorpe wrote:
>>> Very straightforward conversion to the new function in all four spots.
>>
>> I think the right fix here is to switch dm-crypt
> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> index 0007b79..b95934b 100644
> --- a/drivers/dma-buf/dma-buf.c
> +++ b/drivers/dma-buf/dma-buf.c
> @@ -37,6 +37,9 @@
>
> #include
>
> +/* Prevent the highmem.h macro from aliasing ops->kunmap_atomic */
> +#undef kunmap_at
Straightforward conversion, but we have to WARN if unmappable
memory finds its way into the sgl.
Signed-off-by: Logan Gunthorpe
---
drivers/memstick/host/jmb38x_ms.c | 23 ++-
drivers/memstick/host/tifm_ms.c | 22 +-
2 files changed, 35 insertions(+), 10
Straightforward conversion to the new helper, except due to
the lack of error path, we have to warn if unmapable memory
is ever present in the sgl.
Signed-off-by: Logan Gunthorpe
---
drivers/block/xen-blkfront.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletion
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