== Series Details ==
Series: drm/i915/psr: disable psr2 for resolution greater than 32X20
URL : https://patchwork.freedesktop.org/series/17737/
State : success
== Summary ==
Series 17737v1 drm/i915/psr: disable psr2 for resolution greater than 32X20
https://patchwork.freedesktop.org/api/1.0/se
On Mon, 09 Jan 2017, "Yadav, Jyoti R" wrote:
> Hi Jani,
>
> Thanks for finding time to review the patch. Please find my comments inline.
Please try to use the usual reply quoting style of the mailist lists.
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, January 9, 2017 2:30 P
With KBL/SKL and USB-C (DP) to HDMI adapters, we still see
rainbow-like colours on external devices [1] under Linux, though the
issue doesn't reproduce on Windows.
Let me know of any suggestions/patches/changes I can try to aid in
debugging this.
Thanks!
Daniel
[1] https://bugs.freedesktop.org
== Series Details ==
Series: Fix issues caused by gvt init timing
URL : https://patchwork.freedesktop.org/series/17736/
State : success
== Summary ==
Series 17736v1 Fix issues caused by gvt init timing
https://patchwork.freedesktop.org/api/1.0/series/17736/revisions/1/mbox/
Test kms_force_con
On ma, 2017-01-09 at 16:16 +, Chris Wilson wrote:
> Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
> i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
Extra space here --^
> better match usage. Similarly move the pair of functions into
> i915_gem_
On ma, 2017-01-09 at 16:16 +, Chris Wilson wrote:
> Computing the tile row size of a tiled object (for use with fence
> registers) is repeated, so extract it to a common helper.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
Open Source Tec
PSR2 is restricted to work with panel resolutions upto 3200x2000,
move the check to intel_psr_match_conditions and fully block psr.
Cc: Rodrigo Vivi
Cc: Jim Bride
Suggested-by: Rodrigo Vivi
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/intel_psr.c | 15 ---
1 file chan
We only depend on pvinfo register for GVT-g state detection,
not require hypervisor host detect any more.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/gvt.c | 7 ---
drivers/gpu/drm/i915/gvt/hypercall.h | 1 -
drivers/gpu/drm/i915/gvt/kvmgt.c | 32 -
As now gvt init is late after MMIO initialization, use normal MMIO
read function for initial firmware exposure if no available firmware
loaded.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/firmware.c | 47 -
1 file changed, 4 insertions(+), 43 delet
As now gvt init after knowing hw resource info, we can determine vGPU
type from machine size instead of pre-defined value.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/vgpu.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/vgp
This trys to change origin gvt init time which was too early that caused several
workarounds be applied in GVT-g device model driver. To move gvt init a bit
later,
we can fix up those without workarounds.
First one in series touches i915 driver init path that need to be acked.
thanks
Zhenyu Wan
Prepare to remove detect_host() hook. Move intel iommu detection early
in intel_gvt_init().
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/gvt.c | 7 +++
drivers/gpu/drm/i915/gvt/kvmgt.c | 6 --
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i91
Previously intel_gvt_init() was called very early even before
MMIO initialization which had several drawbacks:
- Have to handle MMIO access for initial MMIO state dump if golden
state firmware is not available
- Hypervisor detection should depend on pvinfo only instead of detecting
hypervisor s
Hi,
Please pull GVT-g device model fixes for rc4. This is based on rc3 with
new vfio/mdev interface change.
Thanks.
---
The following changes since commit a121103c922847ba5010819a3f250f1f7fc84ab8:
Linux 4.10-rc3 (2017-01-08 14:18:17 -0800)
are available in the git repository at:
https://
Hi All,
We are seeing CRC check failures in some of the 18bpp video pattern
DP Compliance tests causing the tests to fail. On further investigation, it is
rootcaused to dithering that the i915 driver enables in case of 18bpp pipe
configuration that messes up the CRC and causes the test to fail.
S
Hi Jerome,
[auto build test WARNING on ]
url:
https://github.com/0day-ci/linux/commits/Jerome-Anand/Add-support-for-Legacy-HDMI-audio-drivers/20170110-062228
base:
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
make[3]: warning: jobserver unavailable: using -j1. Ad
On Mon, Jan 09, 2017 at 06:52:52PM +0200, Mika Kuoppala wrote:
> Move the invariant parts of context desc setup from execlist init
> to context creation. This is advantageous when we need to
> create different templates based on the context parametrization,
> ie. for svm capable contexts.
>
> Cc:
On Mon, Jan 09, 2017 at 06:52:53PM +0200, Mika Kuoppala wrote:
> +static int i915_gem_context_enable_svm(struct i915_gem_context *ctx)
> +{
> + int ret;
> +
> + if (!HAS_SVM(ctx->i915))
> + return -ENODEV;
How does legacy execbuf work with an svm context? It will write the
ppgt
The WaDisableLSQCROPERFforOCL workaround has the side effect of
disabling an L3SQ optimization that has huge performance implications
and is unlikely to be necessary for the correct functioning of usual
graphic workloads. Userspace is free to re-enable the workaround on
demand, and is generally in
On Mon, Jan 09, 2017 at 06:52:54PM +0200, Mika Kuoppala wrote:
> From: Jesse Barnes
>
> We just need to pass in an address to execute and some flags, since we
> don't have to worry about buffer relocation or any of the other usual
> stuff. Takes in a fance and returns a fence to be used for
> sy
On Mon, Jan 9, 2017 at 12:22 PM, Dave Hansen wrote:
> On 01/09/2017 08:59 AM, Daniel Vetter wrote:
>> On Mon, Jan 9, 2017 at 5:50 PM, Dave Hansen wrote:
>>> On 01/09/2017 08:41 AM, Daniel Vetter wrote:
On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
> Well, now I found where the -2 c
On Thu, Jan 5, 2017 at 7:14 AM, wrote:
> From: Ville Syrjälä
>
> SKL+ display engine can scan out certain kinds of compressed surfaces
> produced by the render engine. This involved telling the display engine
> the location of the color control surfae (CCS) which describes
> which parts of the m
tags/drm-intel-next-2017-01-09
for you to fetch changes up to 5d799acdd057e4f10fdd09ade22028c83f829f3e:
drm/i915: Update DRIVER_DATE to 20170109 (2017-01-09 10:12:02 +0100)
More 4.11 stuff, holidays edition (i.e. not much
Hi Dave,
Another lonely core fix, picket up by Archit. I think there's 1-2 low-prio
core fixes currently under discussion on dri-devel, I guess that means
another pull somewhen next week or so at lca.
Cheers, Daniel
The following changes since commit aebe55c2d4b998741c0847ace1b4af47d73c763b:
Hi Dave,
Back to regular -misc pulls with reasonable sizes:
- dma_fence error clarification (Chris)
- drm_crtc_from_index helper (Shawn), pile more patches on the m-l to roll
this out to drivers
- mmu-less support for fbdev helpers from Benjamin
- piles of kerneldoc work
- some polish for crc su
== Series Details ==
Series: drm/atomic: Add helper for hw_done and fix suspend.
URL : https://patchwork.freedesktop.org/series/17712/
State : success
== Summary ==
Series 17712v1 drm/atomic: Add helper for hw_done and fix suspend.
https://patchwork.freedesktop.org/api/1.0/series/17712/revisio
== Series Details ==
Series: Add support for Legacy HDMI audio drivers (rev4)
URL : https://patchwork.freedesktop.org/series/16254/
State : success
== Summary ==
Series 16254v4 Add support for Legacy HDMI audio drivers
https://patchwork.freedesktop.org/api/1.0/series/16254/revisions/4/mbox/
T
== Series Details ==
Series: SVM for kbl
URL : https://patchwork.freedesktop.org/series/17710/
State : failure
== Summary ==
Series 17710v1 SVM for kbl
https://patchwork.freedesktop.org/api/1.0/series/17710/revisions/1/mbox/
Test kms_force_connector_basic:
Subgroup force-connector-sta
On 01/09/2017 08:59 AM, Daniel Vetter wrote:
> On Mon, Jan 9, 2017 at 5:50 PM, Dave Hansen wrote:
>> On 01/09/2017 08:41 AM, Daniel Vetter wrote:
>>> On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
Well, now I found where the -2 comes from.
intel_dp_register_mst_connector() calls drm
== Series Details ==
Series: series starting with [1/6] drm/i915: Extract tile_row_size for fencing
URL : https://patchwork.freedesktop.org/series/17709/
State : success
== Summary ==
Series 17709v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/17709/revisions/1/
On 01/09/2017 08:59 AM, Daniel Vetter wrote:
> On Mon, Jan 9, 2017 at 5:50 PM, Dave Hansen wrote:
>> On 01/09/2017 08:41 AM, Daniel Vetter wrote:
>>> On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
Well, now I found where the -2 comes from.
intel_dp_register_mst_connector() calls drm
On Mon, 2017-01-09 at 18:26 +0530, vathsala nagaraju wrote:
> Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
> psr1 should be disabled.When psr2 is exited , bit 31 of reg
> PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
> (psr1 control register)is set to 0.
> Also ,PSR2_ID
Reviewed-by: Rodrigo Vivi
On Mon, 2017-01-09 at 16:51 +0200, Ander Conselvan de Oliveira wrote:
> From: Michel Thierry
>
> Commit cc3f90f0633c ("drm/i915/glk: Reuse broxton code for geminilake")
> missed a few of occurences of IS_BROXTON() that should have been
> coverted to IS_GEN9_LP().
>
>
Hi Jani,
Thanks for finding time to review the patch. Please find my comments inline.
Regards
Jyoti
-Original Message-
From: Nikula, Jani
Sent: Monday, January 9, 2017 2:30 PM
To: Yadav, Jyoti R ; intel-gfx@lists.freedesktop.org
Cc: Kahola, Mika ; Syrjala, Ville
; mi-jenkins-ci
Subjec
Fix hw_done in i915 and make nouveau use drm_atomic_helper_disable_all()
after fixing it to properly disable everything.
Maarten Lankhorst (3):
drm/atomic: move waiting for hw_done to a helper
drm/i915: Wait for pending modesets to complete before trying link
training
drm/atomic: Make di
It seems that nouveau requires this, so best to do this in the helper.
This allows nouveau to use the atomic suspend helper.
Cc: nouv...@lists.freedesktop.org
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_atomic_helper.c | 51 ++
drivers/gpu/drm/nouveau/nouveau_disp
Hdmi audio driver based on the child platform device
created by gfx driver is implemented.
This audio driver is derived from legacy intel
hdmi audio driver.
The interfaces for interaction between gfx and audio
are updated and the driver implementation updated to
derive interrupts in its own addres
We're protected by the connection_mutex lock against blocking modesets,
but nonblocking modesets are performed without any locking. This is
causing WARN in drm_wait_for_vblank and in general it's better to wait
before modeset completes before trying anything.
Signed-off-by: Maarten Lankhorst
---
Enable support for HDMI LPE audio mode on Baytrail and
Cherrytrail when HDaudio controller is not detected
Setup minimum required resources during i915_driver_load:
1. Create a platform device to share MMIO/IRQ resources
2. Make the platform device child of i915 device for runtime PM.
3. Create IR
On Baytrail and Cherrytrail, HDaudio may be fused out or disabled
by the BIOS. This driver enables an alternate path to the i915
display registers and DMA.
Although there is no hardware path between i915 display and LPE/SST
audio clusters, this HDMI capability is referred to in the documentation
a
Notifiations like mode change, hot plug and edid to
the audio driver are added. This is inturn used by the
audio driver for its functionality.
A new interface file capturing the notifications needed by the
audio driver is added
Signed-off-by: Pierre-Louis Bossart
Signed-off-by: Jerome Anand
---
This will allow i915 to perform a wait on pending modeset using the
same code.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_atomic_helper.c | 51 +++--
include/drm/drm_atomic_helper.h | 1 +
2 files changed, 38 insertions(+), 14 deletions(-)
diff
When the display resolution changes, the drm disables the
display pipes due to which audio rendering stops. At this
time, we need to ensure the existing audio pointers and
buffers are cleared out so that the playback can restarted
once the display pipe is enabled with a different N/CTS values
Sign
Legacy (CherryTrail/ Baytrail) HDMI audio drivers added
Legacy hdmi audio-Gfx interaction/ interfacing is updated to use
irq chip framework
This patch series has only been tested on hardware with
a single HDMI connector/pipe and additional work may be needed for newer
machines with 2 connectors
On Mon, Jan 9, 2017 at 5:50 PM, Dave Hansen wrote:
> On 01/09/2017 08:41 AM, Daniel Vetter wrote:
>> On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
>>> Well, now I found where the -2 comes from.
>>> intel_dp_register_mst_connector() calls drm_connector_register(), which
>>> fails to add the k
From: Jesse Barnes
We just need to pass in an address to execute and some flags, since we
don't have to worry about buffer relocation or any of the other usual
stuff. Takes in a fance and returns a fence to be used for
synchronization.
v2: add a request after batch submission (Jesse)
v3: add a
From: Jesse Barnes
Use David's new IOMMU layer functions for supporting SVM in i915.
TODO:
error record collection for failing SVM contexts
callback handling for fatal faults
scheduling
v2: integrate David's core IOMMU support
make sure we don't clobber the PASID in the context reg st
Move the invariant parts of context desc setup from execlist init
to context creation. This is advantageous when we need to
create different templates based on the context parametrization,
ie. for svm capable contexts.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_
Hi,
Now when the blocking problems with iommu layer have been
solved by commits 910170442944e1f8674fd5ddbeeb8ccd1877ea98
and 65ca7f5f7d1cdde6c25172fe6107cd16902f826f it is possible
to test and experiment with this code on KBL.
I have tried to accomodate all the review feedback that
was given by t
On 01/09/2017 08:41 AM, Daniel Vetter wrote:
> On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
>> Well, now I found where the -2 comes from.
>> intel_dp_register_mst_connector() calls drm_connector_register(), which
>> fails to add the kobject (warning below). But, it does zero error
>> checki
On Mon, Jan 9, 2017 at 2:40 PM, Dave Hansen wrote:
> Well, now I found where the -2 comes from.
> intel_dp_register_mst_connector() calls drm_connector_register(), which
> fails to add the kobject (warning below). But, it does zero error
> checking on the drm_connector_register() call and leaves
On Mon, Jan 09, 2017 at 04:19:03PM +, Tvrtko Ursulin wrote:
> >diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> >b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> >index a5fe299da1d3..c6922a5f0514 100644
> >--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> >+++ b/drivers/gpu/drm/i915/i9
On 31/12/2016 12:07, Chris Wilson wrote:
Start converting over from the byte count to its semantic macro, either
we want to allocate the size of a physical page in main memory or we
want the size of a virtual page in the GTT. 4096 could mean either, but
PAGE_SIZE and I915_GTT_PAGE_SIZE are expli
Ensure the view occupies the full tile row so that reads/writes into the
VMA do not escape (via fenced detiling) into neighbouring objects - we
will pad the object with scratch pages to satisfy the fence. This
applies the lazy-tiling we employed on gen2/3 to gen4+.
Signed-off-by: Chris Wilson
Rev
Rename i915_gem_get_ggtt_size() and i915_gem_get_ggtt_alignment() to
i915_gem_fence_size() and i915_gem_fence_alignment() respectively to
better match usage. Similarly move the pair of functions into
i915_gem_tiling.c next to the fence restrictions.
Suggested-by: Joonas Lahtinen
Signed-off-by: C
The fence size/alignment is a combination of the vma size plus object
tiling parameters. Those parameters are rarely changed, making the fence
size/alignemnt roughly constant for the lifetime of the VMA. We can
simplify subsequent calculations by precalculating the size/alignment
required for GGTT
Restricting the fence to the end of the previous tile-row breaks access
to the final portion of the object. On gen2/3 we employed lazy fencing
to pad out the fence with scratch page to provide access to the tail,
and now we also pad out the object on gen4+ we can apply the same fix.
Fixes: af1a730
Computing the tile row size of a tiled object (for use with fence
registers) is repeated, so extract it to a common helper.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 7 +--
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++
drivers/gpu/drm/i915/i915_gem
All of these conditions are prechecked by i915_tiling_ok() before we
allow setting the tiling/stride on the object and so we should never
fail asserting those conditions before writing the register.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_fence
On 09/01/2017 15:58, Chris Wilson wrote:
On Mon, Jan 09, 2017 at 03:43:46PM +, Tvrtko Ursulin wrote:
On 31/12/2016 12:06, Chris Wilson wrote:
Expose an interface for changing the tiling and stride on an object,
that includes the complexity of checking for conflicting bindings and
fence re
On Mon, Jan 09, 2017 at 03:43:46PM +, Tvrtko Ursulin wrote:
>
> On 31/12/2016 12:06, Chris Wilson wrote:
> >Expose an interface for changing the tiling and stride on an object,
> >that includes the complexity of checking for conflicting bindings and
> >fence registers.
> >
> >Signed-off-by: Ch
== Series Details ==
Series: series starting with [1/3] drm/i915/DMC/GLK: Load DMC on GLK (rev2)
URL : https://patchwork.freedesktop.org/series/16926/
State : warning
== Summary ==
Series 16926v2 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/16926/revisions/2/mbo
On 31/12/2016 12:06, Chris Wilson wrote:
Expose an interface for changing the tiling and stride on an object,
that includes the complexity of checking for conflicting bindings and
fence registers.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_object.h | 3 +
drivers/gpu/drm/
On 20 December 2016 at 13:08, Chris Wilson wrote:
> A very simple mockery, just a random manager and timeline. Useful for
> inserting objects and ordering retirement; and not much else.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++
> drivers/gp
On 31/12/2016 12:06, Chris Wilson wrote:
Make it clear that these functions are the user entry points for
the tiling/fence registers.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c| 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 8
drivers/gpu/drm/i915/i9
Hey,
Op 26-12-16 om 19:45 schreef Paulo Zanoni:
> Ville pointed out that intel_fbc_choose_crtc() is iterating over all
> planes instead of just the primary planes. There are no real
> consequences of this problem for HSW+, and for the other platforms it
> just means that in some obscure multi-scre
On 20 December 2016 at 13:08, Chris Wilson wrote:
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem.c | 1 +
> drivers/gpu/drm/i915/selftests/mock_gem_device.c | 109
> +++
> drivers/gpu/drm/i915/selftests/mock_gem_device.h | 8 ++
> dr
On Mon, Jan 09, 2017 at 08:13:11PM +0530, Sumit Semwal wrote:
> Hi Chris,
>
> On 4 January 2017 at 19:42, Chris Wilson wrote:
> > The dma_fence.error field (formerly known as dma_fence.status) is an
> > optional field that may be set by drivers before calling
> > dma_fence_signal(). The field can
From: Michel Thierry
Commit cc3f90f0633c ("drm/i915/glk: Reuse broxton code for geminilake")
missed a few of occurences of IS_BROXTON() that should have been
coverted to IS_GEN9_LP().
v2: Cite the right commit. (Ander)
Fixes: cc3f90f0633c ("drm/i915/glk: Reuse broxton code for geminilake")
Cc:
On ti, 2016-12-13 at 19:15 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915:
> s/gen8_setup_page_directory/gen8_setup_pdpe/
> URL : https://patchwork.freedesktop.org/series/16751/
> State : success
>
Merged the series. Thanks for the patches and r
Hi Chris,
On 4 January 2017 at 19:42, Chris Wilson wrote:
> The dma_fence.error field (formerly known as dma_fence.status) is an
> optional field that may be set by drivers before calling
> dma_fence_signal(). The field can be used to indicate that the fence was
> completed in err rather than wit
On Mon, Jan 09, 2017 at 04:05:01PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
>
> Commit message missing.
>
> > Signed-off-by: Chris Wilson
>
>
>
> > @@ -3360,11 +3360,10 @@ int i915_gem_object_attach_phys(struct
> > drm_i915_gem_object *obj,
> > i
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> Since the partial offset must be page aligned, we can use those low 12
> bits to encode the size of the partial view (which then cannot be larger
> than 8MiB in pages).
>
> Signed-off-by: Chris Wilson
Lets just not, it makes the code unnece
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> The VMA is later clipped against the vm_area_struct before insertion of
> the faulting PTE so we are free to create the partial view as we desire.
> If we use the object as the extents rather than the area, this partial
> can then be used for
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
Commit message missing.
> Signed-off-by: Chris Wilson
> @@ -3360,11 +3360,10 @@ int i915_gem_object_attach_phys(struct
> drm_i915_gem_object *obj,
> int i915_gem_open(struct drm_device *dev, struct drm_file *file);
> void i915_gem_relea
== Series Details ==
Series: drm/i915: check ppgtt validity when init reg state (rev2)
URL : https://patchwork.freedesktop.org/series/17691/
State : warning
== Summary ==
Series 17691v2 drm/i915: check ppgtt validity when init reg state
https://patchwork.freedesktop.org/api/1.0/series/17691/re
-untouched-framebuffers-before-display-on-llc/20170109-190816
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-s3-01092001 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
On 01/09/2017 05:40 AM, Dave Hansen wrote:
> Is there some stable code to go back to here? Or, is there something
> about my configuration that's unique? I really wonder why nobody else
> is running into this.
Here are a couple of similar-looking reports, if that helps:
https://bugzilla.redhat.
-Srinivas/drm-i915-Check-for-platform-specific-GPIO-config/20170109-175734
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make
Well, now I found where the -2 comes from.
intel_dp_register_mst_connector() calls drm_connector_register(), which
fails to add the kobject (warning below). But, it does zero error
checking on the drm_connector_register() call and leaves the
partially-constructed connector in place.
The next time
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> All of these conditions are prechecked by i915_tiling_ok() before we
> allow setting the tiling/stride on the object and so we should never
> fail asserting those conditions before writing the register.
>
> Signed-off-by: Chris Wilson
Spott
On Mon, Jan 09, 2017 at 03:21:43PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> > Ensure the view occupies the full tile row so that reads/writes into the
> > VMA do not escape (via fenced detiling) into neighbouring objects - we
> > will pad the object wi
On Mon, Jan 09, 2017 at 09:14:53PM +0800, Zhenyu Wang wrote:
> Check if ppgtt is valid for context when init reg state. For gvt
> context which has no i915 allocated ppgtt, failed to check that
> would cause kernel null ptr reference error.
>
> v2: remove !48bit ppgtt case as we'll always update b
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> Ensure the view occupies the full tile row so that reads/writes into the
> VMA do not escape (via fenced detiling) into neighbouring objects - we
> will pad the object with scratch pages to satisfy the fence. This
> applies the lazy-tiling we
Check if ppgtt is valid for context when init reg state. For gvt
context which has no i915 allocated ppgtt, failed to check that
would cause kernel null ptr reference error.
v2: remove !48bit ppgtt case as we'll always update before submit (Chris)
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
psr2 enable sequence.
Program Transcoder EDP VSC DIP header with a valid setting for PSR2
and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable header
packet.
Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
v2
On Mon, Jan 09, 2017 at 12:40:07PM +, Tvrtko Ursulin wrote:
>
> On 09/01/2017 12:28, Chris Wilson wrote:
> >On Mon, Jan 09, 2017 at 12:23:37PM +, Tvrtko Ursulin wrote:
> >>
> >>Hi,
> >>
> >>On 20/12/2016 13:42, Tvrtko Ursulin wrote:
> >>>From: Tvrtko Ursulin
> >>>
> >>>Rather than freeing
== Series Details ==
Series: drm/i915: Flush untouched framebuffers before display on !llc
URL : https://patchwork.freedesktop.org/series/17694/
State : failure
== Summary ==
^
drivers/gpu/drm/i915/i915_gem.c:2301:2: note: in expansion of macro ‘GEM_BUG_ON’
GEM_BUG_
On 01/09/2017 02:15 AM, Daniel Vetter wrote:
...
> Can you pls do some printk tracing to make sure that without your patch
> we're indeed releasing the same connector twice from this loop? I suspect
> you're just ever-so-slightly shifting the timing and things blow up
> somewhre else. But no idea w
Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_S
-for-platform-specific-GPIO-config/20170109-175734
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make
rule.
includ
On 09/01/2017 12:28, Chris Wilson wrote:
On Mon, Jan 09, 2017 at 12:23:37PM +, Tvrtko Ursulin wrote:
Hi,
On 20/12/2016 13:42, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Rather than freeing and re-allocating the pages when DMA mapping
in large chunks fails, we can just rebuild the sg ta
-Srinivas/drm-i915-Check-for-platform-specific-GPIO-config/20170109-175734
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce: make htmldocs
All warnings (new ones prefixed by >>):
make[3]: warning: jobserver unavailable: using -j1. Add '+' to parent make
On Mon, Jan 09, 2017 at 12:23:37PM +, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 20/12/2016 13:42, Tvrtko Ursulin wrote:
> >From: Tvrtko Ursulin
> >
> >Rather than freeing and re-allocating the pages when DMA mapping
> >in large chunks fails, we can just rebuild the sg table with no
> >coalescing.
Hi,
On 20/12/2016 13:42, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Rather than freeing and re-allocating the pages when DMA mapping
in large chunks fails, we can just rebuild the sg table with no
coalescing.
Also change back the page counter to unsigned int because that
is what the sg API s
On Mon, Jan 09, 2017 at 01:46:52PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> > Restricting the fence to the end of the previous tile-row breaks access
> > to the final portion of the object. On gen2/3 we employed lazy fencing
> > to pad out the fence wi
On Mon, Jan 09, 2017 at 05:16:01PM +0800, Zhenyu Wang wrote:
> Check if ppgtt is valid for context when init reg state. For gvt
> context which has no i915 allocated ppgtt, failed to check that
> would cause kernel null ptr reference error.
>
> Signed-off-by: Zhenyu Wang
Bah, we could remove the
== Series Details ==
Series: drm/i915: check ppgtt validity when init reg state
URL : https://patchwork.freedesktop.org/series/17691/
State : success
== Summary ==
Series 17691v1 drm/i915: check ppgtt validity when init reg state
https://patchwork.freedesktop.org/api/1.0/series/17691/revisions
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> Restricting the fence to the end of the previous tile-row breaks access
> to the final portion of the object. On gen2/3 we employed lazy fencing
> to pad out the fence with scratch page to provide access to the tail,
> and now we also pad out
Patch subject still needs s/Extact/Extract/.
Regards, Joonas
On pe, 2017-01-06 at 15:25 +, Chris Wilson wrote:
> In order to reuse the partial view for selftesting, extract the common
> function for computing the view.
>
> Signed-off-by: Chris Wilson
> Reviewed-by: Joonas Lahtinen
--
Joon
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