On Tue, 3 Jan 2017 10:59:29 +0800
Zhenyu Wang wrote:
> On 2017.01.03 10:42:39 +1100, Stephen Rothwell wrote:
> > Hi all,
> >
> > After merging the drm-intel-fixes tree, today's linux-next build (x86_64
> > allmodconfig) failed like this:
> >
> > drivers/gpu/drm/i915/gvt/kvmgt.c: In function 'in
Hi Zhenyu,
On Tue, 3 Jan 2017 10:59:29 +0800 Zhenyu Wang wrote:
>
> Alex, I liked to have kvmgt related mdev interface change be merged through
> vfio tree, but wasn't awared one of Jike's fix had conflict. Could you apply
> below fix in your tree? I think in general for possible interface change
>-Original Message-
>From: Wajdeczko, Michal
>Sent: Tuesday, December 27, 2016 9:28 AM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai ; Peter Antoine
>
>Subject: Re: [Intel-gfx] [PATCH 1/8] drm/i915/guc: Make the GuC fw loading
>helper functions general
>
>On Thu, D
On 2017.01.03 10:42:39 +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-intel-fixes tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/gpu/drm/i915/gvt/kvmgt.c: In function 'intel_vgpu_open':
> drivers/gpu/drm/i915/gvt/kvmgt.c:511:32: error: der
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/intel_pm.c
between commit:
e339d67eeb02 ("drm/i915: Pass crtc state to vlv_compute_wm_level()")
from the drm-intel tree and commit:
353c85989963 ("drm: Replace drm_format_plane_cpp() with fb->f
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/intel_overlay.c
between commit:
39ccc04e7435 ("drm/i915: Use primary plane->state for overlay ckey setup")
from the drm-intel tree and commits:
1967b34d5afb ("drm/i915: Add local 'fb' variables
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/i915_vma.c
between commit:
7d1d9aea3ee0 ("drm/i915: Tidy i915_gem_valid_gtt_space()")
from the drm-intel tree and commit:
3f85fb3462dc ("drm: Wrap drm_mm_node.hole_follows")
from the drm-misc
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/i915_gem_evict.c
between commit:
49d73912cbfc ("drm/i915: Convert vm->dev backpointer to vm->i915")
from the drm-intel tree and commit:
9a71e277888b ("drm: Extract struct drm_mm_scan from struc
>-Original Message-
>From: Wajdeczko, Michal
>Sent: Tuesday, December 27, 2016 9:51 AM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Alex Dai ; Peter Antoine
>
>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
>
>On Thu, Dec 22, 2016 at 03:12:19
Hi all,
After merging the drm-intel-fixes tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/gpu/drm/i915/gvt/kvmgt.c: In function 'intel_vgpu_open':
drivers/gpu/drm/i915/gvt/kvmgt.c:511:32: error: dereferencing pointer to
incomplete type 'struct mdev_device'
vfio_u
Hi all,
Today's linux-next merge of the drm-intel-fixes tree got a conflict in:
drivers/gpu/drm/i915/gvt/kvmgt.c
between commit:
99e3123e3d72 ("vfio-mdev: Make mdev_device private and abstract interfaces")
from the vfio-fixes tree and commit:
364fb6b789ff ("drm/i915/gvt/kvmgt: prevent d
On 1/2/2017 4:18 AM, Michał Winiarski wrote:
On Thu, Dec 29, 2016 at 05:32:47PM -0800, daniele.ceraolospu...@intel.com wrote:
From: Daniele Ceraolo Spurio
The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV
register the GuC can use to restore the provided whitelist when an
On 16-12-05 16:44:44, Matt Turner wrote:
On Sat, Dec 3, 2016 at 7:46 AM, Chris Wilson wrote:
Introduce a new execobject.flag (EXEC_OBJECT_CAPTURE) that userspace may
use to indicate that it wants the contents of this buffer preserved in
the error state (/sys/class/drm/cardN/error) following a G
Acked-by: Ben Widawsky
On 16-12-06 16:06:50, Tomeu Vizoso wrote:
Add a few subtests that check that lossless compressed render targets
are properly displayed. Also test a few error conditions.
Cc: Ville Syrjälä
Cc: Ben Widawsky
Signed-off-by: Tomeu Vizoso
---
Hi,
this has been tested with
On Mon, Jan 02, 2017 at 03:28:45PM +, Chris Wilson wrote:
> Ville explained that the wakelock was being acquired during set-idle in
> order to flush the voltage change from the punit.
>
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä ---
> drivers/gpu/drm/i915/intel_pm.c | 14
== Series Details ==
Series: drm/i915: Update comment in vlv_set_rps_idle()
URL : https://patchwork.freedesktop.org/series/17375/
State : warning
== Summary ==
Series 17375v1 drm/i915: Update comment in vlv_set_rps_idle()
https://patchwork.freedesktop.org/api/1.0/series/17375/revisions/1/mbox/
I am wondering why the number of sprite initialization is not done in
runtime init for skylake/glk similarly.
On 1/2/2017 8:27 PM, Chris Wilson wrote:
On Mon, Jan 02, 2017 at 03:54:41PM +0200, Ander Conselvan de Oliveira wrote:
After commit 1c74eeaf16b8 ("drm/i915: Move number of scalers initi
Ville explained that the wakelock was being acquired during set-idle in
order to flush the voltage change from the punit.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä rps.cur_freq <= val)
return;
- /* Wake up the media well, as that takes a lot less
-* power than
On Sat, Dec 31, 2016 at 12:06:41PM +, Chris Wilson wrote:
> The GuC uses a special mapping for the upper end of the Global GTT,
> similar to the way it uses a special mapping for the lower end, so
> exclude it from our drm_mm to prevent us using it.
>
> v2: Rename to reflect that it is unmappa
== Series Details ==
Series: drm/i915: Initialize num_scalers for skl and glk too
URL : https://patchwork.freedesktop.org/series/17372/
State : success
== Summary ==
Series 17372v1 drm/i915: Initialize num_scalers for skl and glk too
https://patchwork.freedesktop.org/api/1.0/series/17372/revis
On Mon, Jan 02, 2017 at 05:02:25PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 02, 2017 at 02:53:59PM +, Chris Wilson wrote:
> > On Mon, Jan 02, 2017 at 04:40:05PM +0200, Ville Syrjälä wrote:
> > > On Mon, Jan 02, 2017 at 02:21:58PM +, Chris Wilson wrote:
> > > > On Mon, Jan 02, 2017 at 04:10
On Mon, Jan 02, 2017 at 02:53:59PM +, Chris Wilson wrote:
> On Mon, Jan 02, 2017 at 04:40:05PM +0200, Ville Syrjälä wrote:
> > On Mon, Jan 02, 2017 at 02:21:58PM +, Chris Wilson wrote:
> > > On Mon, Jan 02, 2017 at 04:10:49PM +0200, Ville Syrjälä wrote:
> > > > On Mon, Jan 02, 2017 at 11:37
On Mon, Jan 02, 2017 at 03:54:41PM +0200, Ander Conselvan de Oliveira wrote:
> After commit 1c74eeaf16b8 ("drm/i915: Move number of scalers initialization to
> runtime init"), scalers are not initialized properly for skl and glk
> since num_scalers is left as 0 for those platforms.
Next question i
On Mon, Jan 02, 2017 at 04:40:05PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 02, 2017 at 02:21:58PM +, Chris Wilson wrote:
> > On Mon, Jan 02, 2017 at 04:10:49PM +0200, Ville Syrjälä wrote:
> > > On Mon, Jan 02, 2017 at 11:37:59AM +, Chris Wilson wrote:
> > > > On Sun, Jan 01, 2017 at 09:48
On Mon, Jan 02, 2017 at 02:21:58PM +, Chris Wilson wrote:
> On Mon, Jan 02, 2017 at 04:10:49PM +0200, Ville Syrjälä wrote:
> > On Mon, Jan 02, 2017 at 11:37:59AM +, Chris Wilson wrote:
> > > On Sun, Jan 01, 2017 at 09:48:53PM +0100, Hans de Goede wrote:
> > > > Hi,
> > > >
> > > > On 01-01
Hi Petri,
I'm not sure what are the i-g-t rules regarding R-b tags nowadays. Does this
require one or can I push it?
Thanks,
Ander
On Tue, 2016-12-20 at 14:33 +0200, Ander Conselvan de Oliveira wrote:
> Copy the include/drm/i915_pciids.h file from following kernel commit,
> which includes Gemin
On Mon, Jan 02, 2017 at 04:10:49PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 02, 2017 at 11:37:59AM +, Chris Wilson wrote:
> > On Sun, Jan 01, 2017 at 09:48:53PM +0100, Hans de Goede wrote:
> > > Hi,
> > >
> > > On 01-01-17 21:24, Chris Wilson wrote:
> > > >On Sun, Jan 01, 2017 at 09:14:02PM +
Hi,
On 02-01-17 15:12, Ville Syrjälä wrote:
On Sun, Jan 01, 2017 at 09:14:00PM +0100, Hans de Goede wrote:
The punit on baytrail / cherrytrail systems is not only accessed through
the iosf_mbi functions, but also by the i915 code. Add a mutex to protect
the punit against simultaneous accesses a
On Sun, Jan 01, 2017 at 09:14:00PM +0100, Hans de Goede wrote:
> The punit on baytrail / cherrytrail systems is not only accessed through
> the iosf_mbi functions, but also by the i915 code. Add a mutex to protect
> the punit against simultaneous accesses and 2 functions to lock / unlock
> this mut
On Mon, Jan 02, 2017 at 11:37:59AM +, Chris Wilson wrote:
> On Sun, Jan 01, 2017 at 09:48:53PM +0100, Hans de Goede wrote:
> > Hi,
> >
> > On 01-01-17 21:24, Chris Wilson wrote:
> > >On Sun, Jan 01, 2017 at 09:14:02PM +0100, Hans de Goede wrote:
> > >>All callers of valleyview_set_rps() get at
After commit 1c74eeaf16b8 ("drm/i915: Move number of scalers initialization to
runtime init"), scalers are not initialized properly for skl and glk
since num_scalers is left as 0 for those platforms.
Fixes: 1c74eeaf16b8 ("drm/i915: Move number of scalers initialization to
runtime init")
Cc: Naben
On Mon, 02 Jan 2017, Petri Latvala wrote:
> On Fri, Dec 23, 2016 at 10:12:17AM +0200, Jani Nikula wrote:
>> The list is perpetually out of date, but giving an idea of what the
>> dependencies are is helpful.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> README | 2 ++
>> 1 file changed, 2 insertio
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Patchwork
> Sent: Monday, January 2, 2017 3:24 PM
> To: Chauhan, Madhav
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✗ Fi.CI.BAT: warning for GLK MIPI DSI VIDEO MODE PATCH
On Tue, 2016-11-29 at 11:23 +0530, Nabendu Maiti wrote:
> In future patches, we require greater flexibility in describing
> the number of scalers available on each CRTC. To ease that transition
> we move the current assignment to intel_device_info.
>
> Scaler structure initialisation is done if sc
== Series Details ==
Series: GLK MIPI DSI VIDEO MODE PATCHES (rev3)
URL : https://patchwork.freedesktop.org/series/16542/
State : warning
== Summary ==
Series 16542v3 GLK MIPI DSI VIDEO MODE PATCHES
https://patchwork.freedesktop.org/api/1.0/series/16542/revisions/3/mbox/
Test gem_sync:
Sure, Thank you Ander.
On 1/2/2017 6:34 PM, Ander Conselvan De Oliveira wrote:
On Mon, 2017-01-02 at 15:00 +0200, Ander Conselvan De Oliveira wrote:
On Tue, 2016-11-29 at 11:23 +0530, Nabendu Maiti wrote:
In future patches, we require greater flexibility in describing
the number of scalers av
On Mon, 2017-01-02 at 15:00 +0200, Ander Conselvan De Oliveira wrote:
> On Tue, 2016-11-29 at 11:23 +0530, Nabendu Maiti wrote:
> >
> > In future patches, we require greater flexibility in describing
> > the number of scalers available on each CRTC. To ease that transition
> > we move the current
On Tue, 2016-11-29 at 11:23 +0530, Nabendu Maiti wrote:
> In future patches, we require greater flexibility in describing
> the number of scalers available on each CRTC. To ease that transition
> we move the current assignment to intel_device_info.
>
> Scaler structure initialisation is done if sc
Use drm_accurate_vblank_count so we have the full 32 bit to represent
the frame counter and userspace has a simpler way of knowing when the
counter wraps around.
Signed-off-by: Tomeu Vizoso
Reviewed-by: Emil Velikov
Reviewed-by: Robert Foss
---
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
1 fi
The core provides now an ABI to userspace for generation of frame CRCs,
so implement the ->set_crc_source() callback and reuse as much code as
possible with the previous ABI implementation.
When handling the pageflip interrupt, we skip 1 or 2 frames depending on
the HW because they contain wrong v
Hi,
here are the patches that remain to be merged in this series.
Since v13, I have added a patch that makes open() block until the first
CRC comes. This is because otherwise, userspace would need to guess how
much time this particular HW takes to become ready to generate frame
CRCs. This patch c
From: Deepak M
Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +
1 file changed, 13 insertion
From: Deepak M
Register MIPI_CLOCK_CTRL is applicable only
for BXT platform. Future platform have other
registers to program the escape clock dividers.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 25 +++--
1 file changed
From: Deepak M
PLL divider range for GLK is different than that of
BXT, hence adding the GLK range check in this patch.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_dsi_pll.c | 20 ++--
2 f
From: Deepak M
For GEMINILAKE, dphy param reg values are programmed in terms
of HS byte clock count while for legacy platforms in terms of
HS ddr clk count.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 33 +++---
From: Deepak M
v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Jani's Review comment for aligning code to platforms and added
wrapper functions.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi.c | 183
From: Deepak M
v2: Addressed Jani's Review comments(renamed bit field macros)
Txesc clock divider is calculated and programmed
for geminilake platform.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++
drivers/gpu/drm/i915/intel_dsi_pll.
From: Deepak M
Program the clk lane and tlpx time count registers
to configure DSI PHY.
v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.
Signed-off-by: Deepak M
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_r
The patches in this list enable MIPI DSI video mode
support for GLK platform. Tesed locally.
v2: Renamed bitfields macros as per review comments(Jani)
v3: Code alignment/abstraction as per arch (Jani review comments)
Deepak M (7):
drm/i915/glk: Program dphy param reg for GLK
drm/i915/glk: Prog
Hi,
On 02-01-17 12:37, Chris Wilson wrote:
On Sun, Jan 01, 2017 at 09:48:53PM +0100, Hans de Goede wrote:
Hi,
On 01-01-17 21:24, Chris Wilson wrote:
On Sun, Jan 01, 2017 at 09:14:02PM +0100, Hans de Goede wrote:
All callers of valleyview_set_rps() get at least FORCEWAKE_MEDIA, except
for int
On Thu, Dec 29, 2016 at 05:32:47PM -0800, daniele.ceraolospu...@intel.com wrote:
> From: Daniele Ceraolo Spurio
>
> The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV
> register the GuC can use to restore the provided whitelist when an
> engine reset via GuC (which we still don
== Series Details ==
Series: enable psr2 for idle_screen on y-cordinate panel (rev2)
URL : https://patchwork.freedesktop.org/series/17295/
State : success
== Summary ==
Series 17295v2 enable psr2 for idle_screen on y-cordinate panel
https://patchwork.freedesktop.org/api/1.0/series/17295/revisi
On Mon, Jan 02, 2017 at 06:43:00AM -0500, Robert Foss wrote:
>
>
> On 2017-01-02 05:42 AM, Chris Wilson wrote:
> >On Mon, Jan 02, 2017 at 05:25:53AM -0500, Robert Foss wrote:
> >>Added and applied 32/64-bit wrapper for pointers used in ioctls.
> >>
> >>Robert Foss (2):
> >> tests/perf: Fix point
On 2017-01-02 05:42 AM, Chris Wilson wrote:
On Mon, Jan 02, 2017 at 05:25:53AM -0500, Robert Foss wrote:
Added and applied 32/64-bit wrapper for pointers used in ioctls.
Robert Foss (2):
tests/perf: Fix pointer length compilation errors on 32-bit systems
lib/ioctl_wrappers.h: Add to_user_
On Sun, Jan 01, 2017 at 09:48:53PM +0100, Hans de Goede wrote:
> Hi,
>
> On 01-01-17 21:24, Chris Wilson wrote:
> >On Sun, Jan 01, 2017 at 09:14:02PM +0100, Hans de Goede wrote:
> >>All callers of valleyview_set_rps() get at least FORCEWAKE_MEDIA, except
> >>for intel_set_rps(). Since intel_set_rp
Psr2 is enabled only for y cordinate panels.Once GTC (global time code)
is implemented,this restriction is removed so that psr2
can work on panels without y cordinate support.
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Patil Deepti
---
drivers/gpu/drm/i915/
As per edp1.4 spec , alpm is required for psr2 operation as it's
used for all psr2 main link power down management and alpm enable
bit must be set for psr2 operation.
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: vathsala nagaraju
Signed-off-by: Patil Deepti
---
drivers/gpu/drm/i915/i915_drv
PSR1 and PSR2 enable sequence are mutually exclusive.
Register SRD_PERF_COUNT increments while system is in psr1.
This register is not valid for psr2.while in psr2,SRD_PERF_COUNT
is always 0.
Reporting psr perfcount from SRD_PERF_COUNT is not valid for psr2 case.
Also, if dc6 is disabled via kernel
As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: vathsala nagaraju
Signed-off-by: Patil Deepti
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++
dri
Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.
Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.
Cc: Rodrigo Vivi
Cc: Jim Bride
S
Reports live state of PSR2 form PSR2_STATUS register.
bit field 31:28 gives the live state of PSR2.
It can be used to check if system is in deep sleep,
selective update or selective update standby.
During video play back, we can use this to check
if system is entering SU mode or not.
when system i
Screen freeze observed if AUX_FRAME_SYNC is not disabled
on psr2 exit.AUX_FRAME_SYNC needed for psr2 is enabled during
psr2 entry. It must be disabled on psr2 exit.
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Patil Deepti
---
drivers/gpu/drm/i915/intel_psr.c
Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_S
This series enables psr2 on idle on screen for y cordinate panel.
Code is tested on sharp 32X18 edp 1.4 y cordinate enabled panel.
if system enters psr2, the system must go to deep sleep state.
Can be verifed by checking psr2_status register bit 31:28.
DEEP_SLEEP[value 8] must be entered while in
PSR2 vsc revision number hb2( as per table 6-11)is updated to
4 or 5 based on Y cordinate and Colorimetry Format as below
04h = 3D stereo + PSR/PSR2 + Y-coordinate.
05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
Format indication. A DP Source device is allowed to indicate
Function hsw_psr_setup handles vsc header setup for psr1 and
skl_psr_setup_vsc handles vsc header setup for psr2.
Setup VSC header in function skl_psr_setup_vsc for psr2 support,
as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
operation.
v2: (Jani)
- Initialize variables to 0
-
On Fri, Dec 23, 2016 at 10:12:17AM +0200, Jani Nikula wrote:
> The list is perpetually out of date, but giving an idea of what the
> dependencies are is helpful.
>
> Signed-off-by: Jani Nikula
> ---
> README | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/README b/README
> index d302
On Mon, Jan 02, 2017 at 05:25:53AM -0500, Robert Foss wrote:
> Added and applied 32/64-bit wrapper for pointers used in ioctls.
>
> Robert Foss (2):
> tests/perf: Fix pointer length compilation errors on 32-bit systems
> lib/ioctl_wrappers.h: Add to_user_pointer() helper
How come these ended
Fix pointer length compilations errors on 32-bit systems.
Signed-off-by: Robert Foss
---
tests/perf.c | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/tests/perf.c b/tests/perf.c
index 87df9f00..c9c5c57e 100644
--- a/tests/perf.c
++
Add to_user_pointer() helper function which helps cast
pointers properly when being used with ioctls.
Signed-off-by: Robert Foss
---
lib/ioctl_wrappers.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 26270975..2ac57f47 100644
-
Added and applied 32/64-bit wrapper for pointers used in ioctls.
Robert Foss (2):
tests/perf: Fix pointer length compilation errors on 32-bit systems
lib/ioctl_wrappers.h: Add to_user_pointer() helper
lib/ioctl_wrappers.h | 11 +++
tests/perf.c | 42 +-
On Mon, 2017-01-02 at 10:55 +0100, Hans de Goede wrote:
> Hi,
>
> On 02-01-17 10:36, Andy Shevchenko wrote:
> > On Sun, 2017-01-01 at 21:15 +0100, Hans de Goede wrote:
> > > Use iosf_mbi_modify instead of iosf_mbi_read + iosf_mbi_write so
> > > that
> > > we keep the iosf_mbi_lock locked during th
Hi,
On 02-01-17 10:36, Andy Shevchenko wrote:
On Sun, 2017-01-01 at 21:15 +0100, Hans de Goede wrote:
Use iosf_mbi_modify instead of iosf_mbi_read + iosf_mbi_write so that
we keep the iosf_mbi_lock locked during the read-modify-write done to
reset the semaphore.
While patch itself looks good
On Fri, 2016-12-30 at 20:04 +0100, Daniel Vetter wrote:
> On Thu, Dec 29, 2016 at 05:22:13PM +0200, Ander Conselvan de Oliveira wrote:
> >
> > The function intel_atomic_get_shared_dpll_state() is only called from
> > intel_dpll_mgr.c and it concerns the same data structures as the other
> > functi
On Sun, 2017-01-01 at 21:15 +0100, Hans de Goede wrote:
> Use iosf_mbi_modify instead of iosf_mbi_read + iosf_mbi_write so that
> we keep the iosf_mbi_lock locked during the read-modify-write done to
> reset the semaphore.
>
While patch itself looks good to me, I think it reduces a probability to
On Mon, Jan 2, 2017 at 9:43 AM, Nagaraju, Vathsala
wrote:
> Hi Daniel,
>
> In the series ,this is the only patch which has changes in
> drm/drm_dp_helper.h, and just now, Jani put the reviewed-tag.
> Should I post the series to dri-de...@lists.freedesktop.org ? please advise.
Yes. Context m
On Sat, 31 Dec 2016, vathsala nagaraju wrote:
> PSR2 vsc revision number hb2( as per table 6-11)is updated to
> 4 or 5 based on Y cordinate and Colorimetry Format as below
> 04h = 3D stereo + PSR/PSR2 + Y-coordinate.
> 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
> Form
On Sun, Jan 01, 2017 at 12:33:53PM +, Xu, Terrence wrote:
> > On Sat, Dec 31, 2016 at 01:24:53AM +0800, Terrence Xu wrote:
> > > GVT-g (Intel® Graphics Virtualization Technology) is a full GPU
> > > virtualization solution with mediated pass-through support.
> > >
> > > This case is for create
On Sat, 2016-12-31 at 22:29 +0100, Hans de Goede wrote:
> This makes sense, the iosf_mbi code which is used by the
> i2c bus semaphore code has this:
>
> arch/x86/platform/intel/iosf_mbi.c:
>
> int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
> {
> u32 mcr, mcrx;
> u
On Sat, Dec 31, 2016 at 07:48:38AM +0530, vathsala nagaraju wrote:
> PSR2 vsc revision number hb2( as per table 6-11)is updated to
> 4 or 5 based on Y cordinate and Colorimetry Format as below
> 04h = 3D stereo + PSR/PSR2 + Y-coordinate.
> 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encodin
On Mon, Jan 02, 2017 at 11:53:03AM +0530, Archit Taneja wrote:
>
>
> On 12/30/2016 2:18 AM, Daniel Vetter wrote:
> > I just learned that &struct_name.member_name works and looks pretty
> > even. It doesn't (yet) link to the member directly though, which would
> > be really good for big structures
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