On Fri, 28 Oct 2016, Fabian Pie wrote:
> Hi,
> I'm testing Baytrail device with mipi/dsi display and hdmi output. When I
> boot without the hdmi connected the mipi/dsi works OK and after connecting
> the hdmi both mipi/dsi and hdmi display graphics OK.
> If I boot with the hdmi connected it's sele
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Pandiyan, Dhinakaran
> Sent: Thursday, October 27, 2016 2:14 AM
> To: ville.syrj...@linux.intel.com
> Cc: Nikula, Jani ; Kp, Jeeja ;
> intel-gfx@lists.freedesktop.org; libin.y...@linux.in
On Thu, 27 Oct 2016, Pierre-Louis Bossart
wrote:
> While testing our upcoming HDMI audio patches, I experienced pretty bad
> screen flicker regressions on my Baytrail compute stick. This happens
> with both v09-rc2 and drm-intel-nightly.
>
> A quick bisect with all the audio patches removed poi
This file has useful information regarding the pci-id --> gen
conversion. The gen determines which scanout formats a chipset
supports (for example, the SKL display engine can scanout Y-tiled
formats). This would be useful for the ozone-gbm interface.
Signed-off-by: Gurchetan Singh
---
intel/Ma
== Series Details ==
Series: Enable i915 perf stream for Haswell OA unit
URL : https://patchwork.freedesktop.org/series/14505/
State : failure
== Summary ==
Series 14505v1 Enable i915 perf stream for Haswell OA unit
https://patchwork.freedesktop.org/api/1.0/series/14505/revisions/1/mbox/
Test
On Wed, 2016-10-26 at 18:14 +, Pandiyan, Dhinakaran wrote:
> On Wed, 2016-10-26 at 12:11 +0300, Ville Syrjälä wrote:
> > On Tue, Oct 25, 2016 at 07:37:36PM -0700, Dhinakaran Pandiyan wrote:
> > > Enabling DP audio stall fix is necessary to play audio over DP HBR2. So,
> > > let's set this bit r
Consistent with the kernel.perf_event_paranoid sysctl option that can
allow non-root users to access system wide cpu metrics, this can
optionally allow non-root users to access system wide OA counter metrics
from Gen graphics hardware.
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
d
In particular this tries to capture for posterity some of the early
challenges we had with using the core perf infrastructure in case we
ever want to revisit adapting perf for device metrics.
Cc: Chris Wilson
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_p
The minimal sampling period is now configurable via a
dev.i915.oa_min_timer_exponent sysctl parameter.
Following the precedent set by perf, the default is the minimum that
won't (on its own) exceed the default kernel.perf_event_max_sample_rate
default of 10 samples/s.
Signed-off-by: Robert Br
Each metric set is given a sysfs entry like:
/sys/class/drm/card0/metrics//id
This allows userspace to enumerate the specific sets that are available
for the current system. The 'id' file contains an unsigned integer that
can be used to open the associated metric set via
DRM_IOCTL_I915_PERF_OPEN.
This adds 'compute', 'compute extended', 'memory reads', 'memory writes'
and 'sampler balance' metric sets for Haswell.
The code is auto generated from an XML description of metric sets,
currently maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-pe
Adds a static OA unit, MUX + B Counter configuration for basic render
metrics on Haswell. This is auto generated from an XML
description of metric sets, currently maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-perf-kernelgen.py
$ make -C gpu
Gen graphics hardware can be set up to periodically write snapshots of
performance counters into a circular buffer via its Observation
Architecture and this patch exposes that capability to userspace via the
i915 perf interface.
v2:
Make sure to initialize ->specific_ctx_id when opening, withou
Being able to program OACONTROL from a non-privileged batch buffer is
not sufficient to be able to configure the OA unit. This was originally
allowed to help enable Mesa to expose OA counters via the
INTEL_performance_query extension, but the current implementation based
on programming OACONTROL vi
OACONTROL changes quite a bit for gen8, with some bits split out into a
per-context OACTXCONTROL register. Rename now before adding more gen7 OA
registers
Signed-off-by: Robert Bragg
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gvt/handlers.c| 2 +-
drivers/gpu/drm/i915/i915_cmd_parse
Rebased on nightly, and updated as per review from Matt and Chris
The first patch from Chris adds an i915_gem_context_pin_legacy() utility that
I'm depending on now - though it doesn't really form part of the i915-perf
series proper. I'm assuming Chris plans to send a version of this to the list
h
Adds base i915 perf infrastructure for Gen performance metrics.
This adds a DRM_IOCTL_I915_PERF_OPEN ioctl that takes an array of uint64
properties to configure a stream of metrics and returns a new fd usable
with standard VFS system calls including read() to read typed and sized
records; ioctl()
From: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 34 ++---
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 55afb66.
check_cmd() is checking whether a command adheres to certain
restrictions that ensure it's safe to execute within a privileged batch
buffer. Returning false implies a privilege problem, not that the
command is invalid.
The distinction makes the difference between allowing the buffer to be
executed
Hi,
On link training failure, I set the connector link_status property
to "Bad" and send a uevent to the userspace. The userspace then detects
this change in property and calls drm_mode_setcrtc that triggers a modeset.
However in the driver atomic check, it calls drm_atomic_helper_check_modeset()
On Thu, 2016-10-27 at 15:35 -0700, Matt Roper wrote:
> On Thu, Oct 27, 2016 at 06:15:32PM -0400, Lyude Paul wrote:
> >
> > On Wed, 2016-10-26 at 15:51 -0700, Matt Roper wrote:
> > >
> > > Gen9 has a traditional cursor plane that is mutually exclusive
> > > with
> > > the
> > > system's top-most "
On Thu, Oct 27, 2016 at 06:15:32PM -0400, Lyude Paul wrote:
> On Wed, 2016-10-26 at 15:51 -0700, Matt Roper wrote:
> > Gen9 has a traditional cursor plane that is mutually exclusive with
> > the
> > system's top-most "universal" plane; it seems likely that two planes
> > are
> > really a single sha
On Wed, 2016-10-26 at 15:51 -0700, Matt Roper wrote:
> Gen9 has a traditional cursor plane that is mutually exclusive with
> the
> system's top-most "universal" plane; it seems likely that two planes
> are
> really a single shared hardware unit with two different register
> interfaces. Thus far i9
On Thu, Oct 27, 2016 at 06:03:54PM -0200, Paulo Zanoni wrote:
> Em Qua, 2016-10-26 às 15:51 -0700, Matt Roper escreveu:
> > Gen9 has a traditional cursor plane that is mutually exclusive with
> > the
> > system's top-most "universal" plane; it seems likely that two planes
> > are
> > really a singl
Em Qua, 2016-10-26 às 15:51 -0700, Matt Roper escreveu:
> Gen9 has a traditional cursor plane that is mutually exclusive with
> the
> system's top-most "universal" plane; it seems likely that two planes
> are
> really a single shared hardware unit with two different register
> interfaces. Thus far
Em Qua, 2016-10-26 às 15:41 +0200, Maarten Lankhorst escreveu:
> Move calculating minimum allocations to a helper, which cleans up the
> code some more. The cursor is still allocated in advance because it
> doesn't count towards data rate and should always be reserved.
>
> changes since v1:
> - Ch
Hi Dave,
So the scripting work is taking a bit longer, and I didn't want to rush
the migration of drm-misc right before ks and leave a mess behind, so this
is still from the old repo.
Pull request already again to get the s/fence/dma_fence/ stuff in and
allow everyone to resync. Otherwise really
While testing our upcoming HDMI audio patches, I experienced pretty bad
screen flicker regressions on my Baytrail compute stick. This happens
with both v09-rc2 and drm-intel-nightly.
A quick bisect with all the audio patches removed points to the
following commit:
2efb813d5388e18255c54afac77
Em Qua, 2016-10-26 às 15:41 +0200, Maarten Lankhorst escreveu:
> It's only used in one function, and can be calculated without caching
> it
> in the global struct by using
> drm_atomic_crtc_state_for_each_plane_state.
>
> There are loops over all planes, including planes that don't exist.
> This i
Em Qui, 2016-10-27 às 10:47 -0700, Matt Roper escreveu:
> On Wed, Oct 26, 2016 at 03:41:31PM +0200, Maarten Lankhorst wrote:
> >
> > This will allow us to find all allocations that may have changed,
> > not just the one added by the atomic state.
> >
> > This is required to stop adding planes to
On Thu, Oct 27, 2016 at 03:48:19PM -0200, Paulo Zanoni wrote:
> Em Qui, 2016-10-27 às 10:31 +0200, Maarten Lankhorst escreveu:
> > Op 27-10-16 om 09:12 schreef Daniel Vetter:
> > >
> > > On Wed, Oct 26, 2016 at 03:41:29PM +0200, Maarten Lankhorst wrote:
> > > >
> > > > Changes since v1:
> > > > -
Em Qui, 2016-10-27 às 10:31 +0200, Maarten Lankhorst escreveu:
> Op 27-10-16 om 09:12 schreef Daniel Vetter:
> >
> > On Wed, Oct 26, 2016 at 03:41:29PM +0200, Maarten Lankhorst wrote:
> > >
> > > Changes since v1:
> > > - Remove plane->pipe checks, they're implied by the macros.
> > > - Split unr
On Wed, Oct 26, 2016 at 03:41:31PM +0200, Maarten Lankhorst wrote:
> This will allow us to find all allocations that may have changed,
> not just the one added by the atomic state.
>
> This is required to stop adding planes to state when its
> allocation changes, and is useful for finding bugs.
>
== Series Details ==
Series: drm/i915: Convert breadcrumbs spinlock to be irqsafe
URL : https://patchwork.freedesktop.org/series/14488/
State : success
== Summary ==
Series 14488v1 drm/i915: Convert breadcrumbs spinlock to be irqsafe
https://patchwork.freedesktop.org/api/1.0/series/14488/revis
The breadcrumbs are about to be used from within IRQ context sections,
therefore we need to employ the irqsafe spinlock variants.
(This is split out of the defer global seqno allocation patch due to
realisation that we need a more complete conversion if we want to defer
request submission even fur
On Thu, Oct 27, 2016 at 03:05:16PM +0100, Chris Wilson wrote:
> Use a priority stored in the context as the initial value when
> submitting a request. This allows us to change the default priority on a
> per-context basis, allowing different contexts to be favoured with GPU
> time at the expense of
== Series Details ==
Series: drm/i915/gen9+: Whitelist TIMESTAMP register from BLT ring
URL : https://patchwork.freedesktop.org/series/14482/
State : warning
== Summary ==
Series 14482v1 drm/i915/gen9+: Whitelist TIMESTAMP register from BLT ring
https://patchwork.freedesktop.org/api/1.0/series
From: Akash Goel
This patch provides the testcase to exercise the TRTT hardware.
Some platforms have an additional address translation hardware support in
form of Tiled Resource Translation Table (TR-TT) which provides an extra level
of abstraction over PPGTT.
This is useful for mapping Sparse/T
On Wed, Oct 26, 2016 at 03:41:30PM +0200, Maarten Lankhorst wrote:
> I'm planning on getting rid of all obj->state dereferences,
> and replace thhem with accessor functions.
> Remove this one early, they're equivalent because removed
> planes are already part of the state, else they could not
> hav
Since gen9 timestamp can be read from BLT ring (TIMESTAMP_BCSUNIT).
Add this register to reg_read ioctl whitelist.
cc=ch...@chris-wilson.co.uk
cc=arkadiusz.hi...@intel.com
cc=michal.winiar...@intel.com
Signed-off-by: Andrzej Lawrynowicz
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +++
1 file ch
Signed-off-by: Chris Wilson
---
lib/igt_debugfs.c | 14 ++
lib/igt_debugfs.h | 1 +
tests/Makefile.sources| 1 +
tests/gem_exec_schedule.c | 407 ++
4 files changed, 423 insertions(+)
create mode 100644 tests/gem_exec_schedule.
On Thu, Oct 27, 2016 at 09:22:16AM +0200, Daniel Vetter wrote:
> I wanted to wrap a bunch of ida_simple_get calls into their own
> locking, until I dug around and read the original commit message.
> Stuff like this should imo be added to the kernel doc, let's do that.
>
> v2: Improve the kerneldoc
The execlist_lock is now completely subsumed by the engine->timeline->lock,
and so we can remove the redundant layer of locking.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_engine_c
On 27/10/2016 14:16, Patchwork wrote:
== Series Details ==
Series: drm/i915: Correct pipe fault reporting string
URL : https://patchwork.freedesktop.org/series/14478/
State : success
== Summary ==
Series 14478v1 drm/i915: Correct pipe fault reporting string
https://patchwork.freedesktop.org
The start of the scheduler, add a hook into request submission for the
scheduler to see the arrival of new requests and prepare its runqueues.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_gem_request.c | 13 +
drivers/gp
Defer the transfer from the client's timeline onto the execution
timeline from the point of readiness to the point of actual submission.
For example, in execlists, a request is finally submitted to hardware
when the hardware is ready, and only put onto the hardware queue when
the request is ready.
Use a priority stored in the context as the initial value when
submitting a request. This allows us to change the default priority on a
per-context basis, allowing different contexts to be favoured with GPU
time at the expense of lower importance work. The user can adjust the
context's priority via
Boost the priority of any rendering required to show the next pageflip
as we want to avoid missing the vblank by being delayed by invisible
workload. We prioritise avoiding jank and jitter in the GUI over
starving background tasks.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h
Track the priority of each request and use it to determine the order in
which we submit requests to the hardware via execlists.
The priority of the request is determined by the user (eventually via
the context) but may be overridden at any time by the driver. When we set
the priority of the reques
The scheduler needs to know the dependencies of each request for the
lifetime of the request, as it may choose to reschedule the requests at
any time and must ensure the dependency tree is not broken. This is in
additional to using the fence to only allow execution after all
dependencies have been
When looking at freezes whilst working on execlists, knowing the order
of the pending requests in the driver is useful.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu
In order to support deferred scheduling, we need to differentiate
between when the request is ready to run (i.e. the submit fence is
signaled) and when the request is actually run (a new execute fence).
This is typically split between the request itself wanting to wait upon
others (for which we use
== Series Details ==
Series: drm/i915: Correct pipe fault reporting string
URL : https://patchwork.freedesktop.org/series/14478/
State : success
== Summary ==
Series 14478v1 drm/i915: Correct pipe fault reporting string
https://patchwork.freedesktop.org/api/1.0/series/14478/revisions/1/mbox/
On Wed, Oct 26, 2016 at 03:41:31PM +0200, Maarten Lankhorst wrote:
> This will allow us to find all allocations that may have changed,
What is the "this" you are referring to?
Ie. please don't treat the subject line as part of the commit message
itself, because it's confusing.
> not just the one
On Thu, Oct 27, 2016 at 01:48:32PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Newline somehow ended up in the middle of the line.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_
On Thu, Oct 27, 2016 at 01:48:32PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Newline somehow ended up in the middle of the line.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 del
From: Tvrtko Ursulin
Newline somehow ended up in the middle of the line.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9111cfdf217a..8
The watermark updates for SKL style watermarks are no longer done
in the plane callbacks, but are now called in a separate watermark
update function that's called during the same vblank evasion,
before the plane updates.
This also gets rid of the global skl_results, which was required for
keeping
On Thu, Oct 27, 2016 at 11:29:55AM +0100, Chris Wilson wrote:
> On Thu, Oct 27, 2016 at 01:13:59PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 27, 2016 at 08:43:44AM +0200, Daniel Vetter wrote:
> > > On Wed, Oct 26, 2016 at 12:17:25PM +0300, Ville Syrjälä wrote:
> > > > On Wed, Oct 26, 2016 at 08:1
On Tue, Oct 25, 2016 at 01:07:25PM +0300, Petri Latvala wrote:
> Am I understanding correctly that gem folks don't object to
> gem_storedw_loop being removed from BAT?
Interpreting silence as a yes.
Acked-by: Petri Latvala
Please push this.
--
Petri Latvala
__
Allow the driver to write watermarks during atomic evasion.
This will make it possible to write the watermarks in a cleaner
way on gen9+.
intel_atomic_state is not used here yet, but will be used when
we program all watermarks as a separate step during evasion.
This also writes linetime all the t
On Thu, Oct 27, 2016 at 01:13:59PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 27, 2016 at 08:43:44AM +0200, Daniel Vetter wrote:
> > On Wed, Oct 26, 2016 at 12:17:25PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 26, 2016 at 08:18:13AM +0200, Daniel Vetter wrote:
> > > > On Mon, Oct 24, 2016 at 10:
On Thu, Oct 27, 2016 at 10:38:38AM +0100, Emil Velikov wrote:
From: Emil Velikov
File is provided by the libdrm_intel package which is optional. Since we
already have a local copy of the file, we might as well use it ;-)
v2: Move the file alongside intel_bufmgr.h and use it in the
disable-inte
== Series Details ==
Series: Enable i915 perf stream for Haswell OA unit
URL : https://patchwork.freedesktop.org/series/14308/
State : failure
== Summary ==
Series 14308v1 Enable i915 perf stream for Haswell OA unit
https://patchwork.freedesktop.org/api/1.0/series/14308/revisions/1/mbox/
Test
On Thu, Oct 27, 2016 at 08:43:44AM +0200, Daniel Vetter wrote:
> On Wed, Oct 26, 2016 at 12:17:25PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 26, 2016 at 08:18:13AM +0200, Daniel Vetter wrote:
> > > On Mon, Oct 24, 2016 at 10:38:34AM +0100, Chris Wilson wrote:
> > > > On Mon, Oct 24, 2016 at 11:1
== Series Details ==
Series: DP audio fixes (rev5)
URL : https://patchwork.freedesktop.org/series/14314/
State : warning
== Summary ==
Series 14314v5 DP audio fixes
https://patchwork.freedesktop.org/api/1.0/series/14314/revisions/5/mbox/
Test gem_ctx_switch:
Subgroup basic-default:
From: Emil Velikov
File is provided by the libdrm_intel package which is optional. Since we
already have a local copy of the file, we might as well use it ;-)
v2: Move the file alongside intel_bufmgr.h and use it in the
disable-intel case.
Cc: Brian Starkey
Reported-by: Brian Starkey
Signed-o
On Wed, 2016-10-26 at 12:11 +0300, Ville Syrjälä wrote:
> On Tue, Oct 25, 2016 at 07:37:36PM -0700, Dhinakaran Pandiyan wrote:
> > Enabling DP audio stall fix is necessary to play audio over DP HBR2. So,
> > let's set this bit right before enabling the audio codec. Playing audio
> > without setting
On Thu, Oct 27, 2016 at 08:46:50AM +0100, Tvrtko Ursulin wrote:
>
> On 25/10/2016 13:45, ville.syrj...@linux.intel.com wrote:
> >From: Ville Syrjälä
> >
> >Starting from commit b63a16f6cd89 ("drm/i915: Compute display surface
> >offset in the plane check hook for SKL+") we've already rotated the
On Thu, Oct 27, 2016 at 03:03:27PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's new pull request to address recent build issues reported
> and with more cleanup and fixes. Passed VM regression tests.
>
> Thanks.
> --
>
> The following changes since commit 19e6393fb5366a89705a62b3276ce42e990d12c
On Thu, Oct 27, 2016 at 09:28:12AM +0200, Daniel Vetter wrote:
On Wed, Oct 26, 2016 at 05:48:39PM +0100, Emil Velikov wrote:
From: Emil Velikov
File is provided by the libdrm_intel package which is optional. Since we
already have a local copy of the file, we might as well use it ;-)
Cc: Brian
On 26/10/2016 08:46, Patchwork wrote:
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Rotated view does not need a
fence (rev3)
URL : https://patchwork.freedesktop.org/series/14340/
State : success
== Summary ==
Series 14340v3 Series without cover letter
https://patchw
This patch is now pushed, thanks.
--
Petri Latvala
On Wed, Oct 12, 2016 at 02:32:17PM +0100, Tvrtko Ursulin wrote:
>
> On 10/10/2016 15:31, Goel, Akash wrote:
> >
> >
> > On 10/10/2016 7:22 PM, Tvrtko Ursulin wrote:
> > >
> > > On 10/10/2016 11:59, akash.g...@intel.com wrote:
> > > > From:
Rebased on nightly, including recent review updates (CI wasn't happy picking up
the replies updating individual patches).
This also reverts back to pinning the context upfront when opening a stream for
a single context, instead of hooking into pinning and updating OACONTROL on the
fly.
Chris has
On Wed, 26 Oct 2016, Dhinakaran Pandiyan wrote:
> According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> enabled, port width x4, and link rate HBR2 (5.4 GHz)
>
> Having a lower cdclk triggers pipe underruns, which then lead to displays
> continuously cycling off and on. This is
On Fri, 2016-10-21 at 16:45 -0700, Manasi Navare wrote:
> This is required to return the index of link rate into
> common_rates array. This gets used to retry the link
> training at lower link rate.
>
> Cc: Jani Nikula
> Cc: Daniel Vetter
> Cc: Ville Syrjala
> Signed-off-by: Manasi Navare
> --
== Series Details ==
Series: drm: Release reference from blob lookup after replacing property (rev2)
URL : https://patchwork.freedesktop.org/series/14357/
State : warning
== Summary ==
Series 14357v2 drm: Release reference from blob lookup after replacing property
https://patchwork.freedesktop
== Series Details ==
Series: drm/i915/DMC/KBL: Load DMC on KBL using the no_stepping_info array
URL : https://patchwork.freedesktop.org/series/14311/
State : warning
== Summary ==
Series 14311v1 drm/i915/DMC/KBL: Load DMC on KBL using the no_stepping_info
array
https://patchwork.freedesktop.o
Comment mentioned use of intel_uncore_forcewake_irq{unlock, lock}
functions which are nonexistent (and never were).
The description was also incomplete and could cause confusion. Updated
comment is more elaborate on usage and caveats.
v2: mention __locked variant of intel_uncore_forcewake_{get,pu
Adds a static OA unit, MUX + B Counter configuration for basic render
metrics on Haswell. This is auto generated from an XML
description of metric sets, currently maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-perf-kernelgen.py
$ make -C gpu
Op 27-10-16 om 09:12 schreef Daniel Vetter:
> On Wed, Oct 26, 2016 at 03:41:29PM +0200, Maarten Lankhorst wrote:
>> Changes since v1:
>> - Remove plane->pipe checks, they're implied by the macros.
>> - Split unrelated changes to a separate commit.
>>
>> Signed-off-by: Maarten Lankhorst
> Drive-by
Tested with HuC version 1.07.1398 on SKL.
Reviewed-by: Carlos Santa
Tested-by: Carlos Santa
On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine
>
> Add debugfs entry for HuC loading status check.
>
> v2: rebase on-top of drm-intel-nightly.
> v3: rebased again.
> v
On Mon, Oct 24, 2016 at 02:24:01PM -0700, Carlos Santa wrote:
> On Thu, 2016-10-13 at 13:54 -0700, Jeff McGee wrote:
> > On Thu, Oct 13, 2016 at 10:42:42AM -0700, Jeff McGee wrote:
> > >
> > > On Mon, Oct 03, 2016 at 11:42:57AM -0700, Anusha Srivatsa wrote:
> > > >
> > > > From: Peter Antoine
>
On 27 October 2016 at 10:06, Chris Wilson wrote:
> On Thu, Oct 27, 2016 at 09:58:19AM +0200, Tomeu Vizoso wrote:
>> __drm_open_driver was changed to bail out on VGEM devices unless they
>> are explicitly asked for (DRIVER_VGEM). But with that change we lost
>> support for DRIVER_ANY.
>>
>> Signed-
Op 27-10-16 om 01:24 schreef Matt Roper:
> On Wed, Oct 26, 2016 at 03:41:37PM +0200, Maarten Lankhorst wrote:
>> The watermark updates for SKL style watermarks are no longer done
>> in the plane callbacks, but are now called in a separate watermark
>> update function that's called during the same v
Enabling DP audio stall fix is necessary to play audio over DP HBR2. So,
let's set this bit right before enabling the audio codec. Playing audio
without setting this bit results in pipe FIFO underruns.
This workaround is applicable only for audio sample rates up to 96kHz. For
frequencies above 96k
On Mon, Oct 24, 2016 at 03:08:48PM -0700, Manasi Navare wrote:
> On Mon, Oct 24, 2016 at 09:12:35AM +0200, Daniel Vetter wrote:
> > On Mon, Oct 24, 2016 at 9:00 AM, Manasi Navare
> > wrote:
> > >> I guess we just need to do some additional work on top to make sure the
> > >> vblank ioctl can't see
On Wed, 26 Oct 2016, Dhinakaran Pandiyan wrote:
> Enabling DP audio stall fix is necessary to play audio over DP HBR2. So,
> let's set this bit right before enabling the audio codec. Playing audio
> without setting this bit results in pipe FIFO underruns.
>
> This workaround is applicable only for
On Mon, Oct 24, 2016 at 03:52:09PM +0530, Archit Taneja wrote:
>
>
> On 10/24/2016 03:45 PM, Ville Syrjälä wrote:
> > On Mon, Oct 24, 2016 at 03:33:18PM +0530, Archit Taneja wrote:
> >> Hi Ville,
> >>
> >> On 10/22/2016 12:52 AM, ville.syrj...@linux.intel.com wrote:
> >>> From: Ville Syrjälä
> >
On Fri, Oct 21, 2016 at 03:44:54PM +0100, Daniel Stone wrote:
> The previous code would wait for fences on the framebuffer from the old
> plane state to complete, rather than the new, so you would see tearing
> everywhere. Fix this to wait on the new state before we make it active.
>
> Signed-off-
Currently we try to reduce the number of synchronisations (now the
number of requests we need to wait upon) by noting that if we have
earlier waited upon a request, all subsequent requests in the timeline
will be after the wait. This only applies to requests in this timeline,
as other timelines wil
From: Ville Syrjälä
Since the hardware can apparently do both X and Y reflection, we
can advertize also 180 degree rotation as thats just X+Y reflection.
v2: Drop the BIT()
Cc: Rob Clark
Cc: Jilai Wang
Cc: Archit Taneja
Signed-off-by: Ville Syrjälä
Reviewed-by: Rob Clark
---
drivers/gpu/d
On Fri, Oct 21, 2016 at 05:16:45PM +0300, Ander Conselvan De Oliveira wrote:
> On Wed, 2016-10-19 at 16:56 +, Patchwork wrote:
> > Test kms_force_connector_basic:
> > Subgroup force-load-detect:
> > incomplete -> PASS (fi-byt-j1900)
> > pass -
The command parser no longer whitelists or does anything special for the
OACONTROL register which is now considered owned by i915-perf.
As a follow up the plan is to at least check that attempting to write to
OACONTROL from userspace must not fail with an EINVAL error, otherwise
Mesa's graceful fa
On Wed, 2016-10-26 at 18:10 +0300, Ville Syrjälä wrote:
> On Wed, Oct 26, 2016 at 05:50:08PM +0300, Imre Deak wrote:
> > There's at least one LSPCON device that occasionally returns an unexpected
> > adaptor ID which leads to a failed detect. Print some debug info to help
> > debugging this and fut
On Mon, 2016-10-03 at 11:42 -0700, Anusha Srivatsa wrote:
> From: Peter Antoine
>
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased
Hi Tvrtko,
Along with this change I made following change in the kernel side. I was not
sure if this is a hack of a legitimate change. Could you please give me a
pointer about how to move fwd from here? Without this all Y-tiling tests would
fail.
--- a/drivers/gpu/drm/i915/intel_display.c
+++
On Wed, Oct 26, 2016 at 12:05:44AM +0100, Chris Wilson wrote:
> On Tue, Oct 25, 2016 at 12:19:29AM +0100, Robert Bragg wrote:
> > + /* So that we don't have to worry about updating the context ID
> > +* in OACONTOL on the fly we make sure to pin the context
> > +* upfront for the lifetime
== Series Details ==
Series: drm/i915/guc: WA to address the Ringbuffer coherency issue (rev2)
URL : https://patchwork.freedesktop.org/series/13807/
State : warning
== Summary ==
Series 13807v2 drm/i915/guc: WA to address the Ringbuffer coherency issue
https://patchwork.freedesktop.org/api/1.0
On Thu, Oct 27, 2016 at 08:46:50AM +0100, Tvrtko Ursulin wrote:
>
> On 25/10/2016 13:45, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Starting from commit b63a16f6cd89 ("drm/i915: Compute display surface
> > offset in the plane check hook for SKL+") we've already rotated
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