On Tue, Jun 07, 2016 at 11:18:47AM -0400, Zhi Wang wrote:
> GVT workload scheduler needs special host LRC contexts, the so called
> "shadow LRC context" to submit guest workload to host i915. During the
> guest workload submission, workload scheduler fills the shadow LRC
> context with the content
On Tue, 2016-06-07 at 21:24 +0300, Imre Deak wrote:
> So far we configured a static lane latency optimization during driver
> loading/resuming. The specification changed at one point and now this
> configuration depends on the lane count, so move the configuration
> to modeset time accordingly.
>
== Series Details ==
Series: drm/i915/bxt: Fix DDI PHY setup for low resolutions
URL : https://patchwork.freedesktop.org/series/8414/
State : success
== Summary ==
Series 8414v1 drm/i915/bxt: Fix DDI PHY setup for low resolutions
http://patchwork.freedesktop.org/api/1.0/series/8414/revisions/1
On Tue, Jun 07, 2016 at 02:52:18PM -, Patchwork wrote:
> == Series Details ==
>
> Series: gen9 workarounds v3
> URL : https://patchwork.freedesktop.org/series/8405/
> State : success
>
> == Summary ==
>
> Series 8405v1 gen9 workarounds v3
> http://patchwork.freedesktop.org/api/1.0/series/8
Acked-by: Sinclair Yeh
On Tue, Jun 07, 2016 at 12:49:30PM +0200, Maarten Lankhorst wrote:
> Change return value to int to propagate errors from gamma_set,
> and remove start parameter. Updates always use the full size,
> and some drivers even ignore the start parameter altogether.
>
> This is ne
On Tue, Jun 07, 2016 at 11:18:45AM -0400, Zhi Wang wrote:
> This patch introduces an approach to track the execlist context status
> change.
>
> GVT-g uses GVT context as the "shadow context". The content inside GVT
> context will be copied back to guest after the context is idle. And GVT-g
> has
Hi Dave,
As promised, piles of prep work all around:
- drm_atomic_state rework, prep for nonblocking commit helpers
- fence patches from Gustavo and Christian to prep for atomic fences and
some cool work in ttm/amdgpu from Christian
- drm event prep for both nonblocking commit and atomic fences
On Tue, Jun 07, 2016 at 02:23:34PM +0100, Tvrtko Ursulin wrote:
>
> On 07/06/16 11:54, Dave Gordon wrote:
> >On 07/06/16 09:43, Patchwork wrote:
> >>== Series Details ==
> >>
> >>Series: series starting with [1/3] drm/i915/guc: fix GuC
> >>loading/submission check
> >>URL : https://patchwork.fre
Hi Dave,
drm-intel-next-2016-06-06:
- some polish for the guc code (Dave Gordon)
- big refactoring of gen9 display clock handling code (Ville)
- refactoring work in the context code (Chris Wilson)
- give encoder/crtc/planes useful names for debug output (Ville)
- improvements to skl/kbl wm computa
On Tue, Jun 07, 2016 at 05:26:21PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Introduce a new top-level lock for the FB helper code. This will allow
> better locking granularity and avoid the need to abuse modeset locking
> for this purpose instead.
>
> Signed-off-by: Thierry Reding
On Tue, Jun 07, 2016 at 05:26:24PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> The FB helper core now supports deferred setup, so the driver's custom
> implementation can be removed.
>
> Signed-off-by: Thierry Reding
> ---
> drivers/gpu/drm/exynos/exynos_drm_drv.c | 8 ++--
>
On Tue, Jun 07, 2016 at 10:02:35AM +0300, Jani Nikula wrote:
> On Mon, 06 Jun 2016, Lyude Paul wrote:
> > On Mon, 2016-06-06 at 14:30 +0300, Ville Syrjälä wrote:
> >> On Thu, May 26, 2016 at 09:54:56AM +0200, Daniel Vetter wrote:
> >> >
> >> > Queued for -next, thanks for the patch.
> >> Looks li
There are two problems with the current way of enabling the DDI PHYs
during driver loading/resuming:
Relying on the HWs dynamic power gating may waste some power and part of
the PHY configuration is dependent on the mode specific DDI lane count.
To solve both of these issues split the PHY initializ
We can check the power state of the PHY data and common lanes as
reported by the PHY. Do this in case we need to debug problems where the
PHY gets stuck in an unexpected state.
Note that I only check these when the lanes are expected to be powered
on purpose, since it's not clear at what point the
So far we depended on the HW to dynamically power down unused PHYs and
so we enabled them manually once during driver loading/resuming. There
are indications however that we can achieve better power savings by
manual powering toggling. So make the PHY enabling/disabling to happen
on-demand whenever
These helpers will be needed by the next patch, so factor them out.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/
A follow-up patch moves the PHY enabling to the power well code where
enabling/disabling the PHYs will happen independently. Because of this
waiting for the GRC calibration in PHY1 asynchronously would need some
additional logic. Instead of adding that let's keep things simple for now
and wait sync
So far we configured a static lane latency optimization during driver
loading/resuming. The specification changed at one point and now this
configuration depends on the lane count, so move the configuration
to modeset time accordingly.
It's not clear when this lane configuration takes effect. The
Rename these remaining function prefixes to better align with the
corresponding SKL functions.
No functional change.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c| 13 ++---
drivers/gpu/drm/i915/intel_display.c| 28 ++--
drivers/gpu/dr
== Series Details ==
Series: drm/fb-helper: Deferred setup support
URL : https://patchwork.freedesktop.org/series/8410/
State : failure
== Summary ==
Applying: drm/fb-helper: Cleanup checkpatch warnings
Using index info to reconstruct a base tree...
M drivers/gpu/drm/drm_fb_helper.c
Fall
On Fri, Jun 03, 2016 at 12:17:43PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Apparently some CHV boards failed to hook up the port presence straps
> for HDMI ports as well (earlier we assumed this problem only affected
> eDP ports). So let's check the VBT in addition t
On Tue, Jun 07, 2016 at 05:19:19PM +0300, Mika Kuoppala wrote:
> Add this fbc related workaround for all gen9
>
> Cc: Ville Syrjälä
> Signed-off-by: Mika Kuoppala
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 4
> 2 files c
On Thu, May 19, 2016 at 06:09:11PM +0300, David Weinehall wrote:
> On Thu, May 19, 2016 at 01:23:53PM -, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915: only disable memory self-refresh on GMCH
> > URL : https://patchwork.freedesktop.org/series/7406/
> > State : failure
>
== Series Details ==
Series: Introduce the implementation of GVT context (rev5)
URL : https://patchwork.freedesktop.org/series/7208/
State : success
== Summary ==
Series 7208v5 Introduce the implementation of GVT context
http://patchwork.freedesktop.org/api/1.0/series/7208/revisions/5/mbox
f
From: Thierry Reding
Introduce a new top-level lock for the FB helper code. This will allow
better locking granularity and avoid the need to abuse modeset locking
for this purpose instead.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/drm_fb_helper.c | 27 ++-
inclu
From: Thierry Reding
Fix up a couple of checkpatch warnings, such as whitespace or coding
style issues.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/drm_fb_helper.c | 33 +++--
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_
From: Thierry Reding
The FB helper core now supports deferred setup, so the driver's custom
implementation can be removed.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --gi
> -Original Message-
> From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.com]
> Sent: Friday, June 03, 2016 12:40 PM
> To: Wang, Zhi A ; intel-gfx@lists.freedesktop.org;
> tvrtko.ursu...@linux.intel.com; Tian, Kevin ; Lv,
> Zhiyuan
> ; ch...@chris-wilson.co.uk
> Subject: Re: [PAT
From: Thierry Reding
The FB helper core now supports deferred setup, so the driver's custom
implementation can be removed.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/exynos/exynos_drm_drv.c | 8 ++--
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 2 --
2 files changed, 6 insertions(+
From: Thierry Reding
The FB helper core now supports deferred setup, so the driver's custom
implementation can be removed.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --g
From: Thierry Reding
This set of patches adds support for deferring FB helper setup, which is
useful to obtain a sane configuration even when no outputs are available
during probe.
One example is HDMI, where fbdev will currently fallback to a 1024x786
resolution if no monitor is connected, and w
From: Thierry Reding
FB helper code falls back to a 1024x768 mode if no outputs are connected
or don't report back any modes upon initialization. This can be annoying
because outputs that are added to FB helper later on can't be used with
FB helper if they don't support a matching mode.
The fall
From: Thierry Reding
Add a couple of temporary variables and use shorter names for existing
variables in drm_fb_helper_add_one_connector() for better readability.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/drm_fb_helper.c | 26 --
1 file changed, 16 insertions(+)
From: Thierry Reding
Move the modeset locking from drivers into FB helpers.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/drm_fb_helper.c| 59 +-
drivers/gpu/drm/i915/intel_dp_mst.c| 4 ---
drivers/gpu/drm/radeon/radeon_dp_mst.c | 7
3 fil
From: Thierry Reding
An unlocked version of the drm_fb_helper_add_one_connector() function
will be added in a subsequent patch. Reshuffle the code separately to
make the diff more readable later on.
Signed-off-by: Thierry Reding
---
drivers/gpu/drm/drm_fb_helper.c | 60
Currently the addressing mode bit in context descriptor is statically
generated from the configuration of system-wide PPGTT usage model.
GVT-g will load the PPGTT shadow page table by itself and probably one
guest is using a different addressing mode with i915 host. The addressing
mode bits of a L
GVT workload scheduler needs special host LRC contexts, the so called
"shadow LRC context" to submit guest workload to host i915. During the
guest workload submission, workload scheduler fills the shadow LRC
context with the content of guest LRC context: engine context is copied
without changes, ri
From: Bing Niu
This patch introduces host graphics memory partition when GVT-g
is enabled.
Under GVT-g, i915 host driver only owned limited graphics resources,
others are managed by GVT-g resource allocator and kept for other vGPUs.
v7:
- Add comments about low/high GM size for host. (Joonas)
This patch introduces an option for configuring the ring buffer size
of a LRC context after the context creation.
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/intel_lrc.c| 3 ++-
3 files cha
This patch introduces the support of LRC context single submission.
As GVT context may come from different guests, which require different
configuration of render registers. It can't be combined into a dual ELSP
submission combo.
Only GVT-g will create this kinds of GEM context currently.
v7:
-
This patch introduces an approach to track the execlist context status
change.
GVT-g uses GVT context as the "shadow context". The content inside GVT
context will be copied back to guest after the context is idle. And GVT-g
has to know the status of the execlist context.
This function is configur
As the PVINFO page definition is used by both GVT-g guest (vGPU) and GVT-g
host (GVT-g kernel device model), factor it out for better code structure.
v7:
- Split the "offsetof" modification into a dedicated patch. (Joonas)
v3:
- Use offsetof to calculate the member offset of PVINFO structure (Joo
This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.
v7:
- Refine the URL link in Kconfig. (Joonas)
- Refine the introduction of GVT-g host support in Kconfig. (Joonas)
- Remove the macro GVT_ALIGN(), use round_down() instead
v5:
- Let functions take struct drm_i915_private *. (Tvrtko)
- Fold vGPU related active check into the inner functions. (Kevin)
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ---
drivers/gpu/drm/i915/i915_vgpu.c| 13 +
drivers/gpu/drm/i915/i915_vgp
To get the offset of the members in PVINFO page, offsetof() looks much
better than the tricky approach in current code.
v7:
- Move "offsetof()" modification into a dedicated patch. (Joonas)
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_pvinfo.h | 2 +-
1 file changed, 1 insertion(+), 1
This function needs to be changed to have a proper goto teardown path.
Destructors/fini functions are only expected to be called after a
successful initialization, so calling it at random phase in init function
is bad. (Joonas)
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_vgpu.c | 7 +++
This patchset introduces the implementation of GVT context. GVT
context is a special GEM context used by GVT-g. GVT-g uses it as the shadow
context.It doesn't have a drm client nor a PPGTT. And it requires a larger
ring buffer with several special features need by GVT-g workload scheduler
like cont
== Series Details ==
Series: gen9 workarounds v3
URL : https://patchwork.freedesktop.org/series/8405/
State : success
== Summary ==
Series 8405v1 gen9 workarounds v3
http://patchwork.freedesktop.org/api/1.0/series/8405/revisions/1/mbox
fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0
On Tue, Jun 07, 2016 at 01:47:56PM +0200, Boris Brezillon wrote:
> Adapt drm_pick_crtcs() and update_connector_routing() to fallback to
> drm_atomic_helper_best_encoder() if funcs->best_encoder() is NULL so
> that DRM drivers can leave this hook unassigned if they know they want
> to use drm_atomic
We need this for kbl a0 boards. Note that this should be also
for bxt A0 but we omit that on purpose as bxt A0's are
out of fashion already.
References: HSD#1912158, HSD#4393097
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 6 --
1 file
According to bspec this prevents screen corruption when fbc is
used.
v2: This workaround has a name, use it (Ville)
v3: remove bogus gen check on ilk/vlv wm path (Ville)
References: HSD#213, HSD#2137270, BSID#562
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
Reviewed-by:
Make sure that we never enable skip caching on gen9 by
accident.
References: HSD#2134698
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_mocs.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/
There is ambiguity in the documentation between D0 and E0.
Extend this workaround to E0.
References: BSID#779
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i9
Add this workaround for both bxt and kbl up to until
rev B0.
References: HSD#2136703
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++
2 files changed, 11 insertions(+)
diff --git
Set bit 8 in 0x43224 to prevent screen corruption and system
hangs on high memory bandwidth conditions. The same wa also suggest
setting bit 31 on ARB_CTL. According to another workaround we gain
better idle power savings when FBC is enabled.
v2: use correct workaround name
v3: split out overlappi
We need to disable clock gating in this unit to work around
hardware issue causing possible corruption/hang.
v2: name the bit (Ville)
v3: leave the fix enabled for 2227050 and set correct bit (Matthew)
v4: Split out the skl part in separate commit for easier backport
References: HSD#2227156, HSD#
Bspec states that we need to turn off dynamic credit
sharing on kbl revid a0 and b0. This happens by writing bit 28
on 0x4ab8.
References: HSD#2225601, HSD#2226938, HSD#2225763
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gp
For now If we want to achieve that, we have to add a member in struct
i915_gem_request like your code. :(
/* Assume in all host GEM request, req->vgpu == NULL*/
If (req0->vgpu = req1->vgpu)
combine!
> -Original Message-
> From: Joonas Lahtinen [mailto:joonas.lahti...@linux.intel.
Add this fbc related workaround for all gen9
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
On 06/07/2016 04:07 PM, Maarten Lankhorst wrote:
Op 07-06-16 om 14:03 schreef Patchwork:
== Series Details ==
Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
URL : https://patchwork.freedesktop.org/series/8164/
State : success
...
ro-snb-i7-2620M failed to connect after r
According to bspec we need to disable gam unit clock gating on
on kbl revids A0 and B0.
References: HSD#2226858, HSD#1944358
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 5 +
2 files changed, 6 insertions
Hi,
Reordered and rebased series. I singled out major skl one to
the start of series for easier backporting.
Only 27/27 is missing r-b tag.
Thank you for Matthew and Ville for reviews.
-Mika
Mika Kuoppala (27):
drm/i915/skl: Add WaDisableGafsUnitClkGating
drm/i915/kbl: Init gen9 workaround
The bspec states that these must be set in CONFIG0 for all gen9.
v2: rebase
v3: fix spacing (Matthew)
References: HSD#2134995
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 24 ++--
2 fi
This workaround for bdw and chv, is also needed for kbl A0.
References: HSD#1911519, BSID#569
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_lrc.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/driv
Add this workaround until upto kbl revid B0.
References: HSD#1802092
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_pm.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/d
Bspec states that we need to set nuke on modify all to prevent
screen corruption with fbc on skl and kbl.
v2: proper workaround name
References: HSD#2227109, HSDES#1404569388
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
d
Add REVID macro for kbl to limit wa applicability to particular
revision range.
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
Add this workaround for A0 and B0 revisions
References: HSD#2226935
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_lrc.c | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lr
We need to disable clock gating in this unit to work around
hardware issue causing possible corruption/hang.
v2: name the bit (Ville)
v3: leave the fix enabled for 2227050 and set correct bit (Matthew)
References: HSD#2227156, HSD#2227050
Cc: Ville Syrjälä
Cc: Matthew Auld
Reviewed-by: Matthew
According to bspec this workaround helps to reduce lag and improve
performance on edp.
Documentation suggests this for bdw and all gen9. However evidence
shows that this register is missing on gen9 and causing unclaimed mmio
access if we access it. So apply to bdw only where the reg
exists and can
This workaround is for fbc working with rc6 on skylake. Bspec
states that setting this bit needs to be coordinated with uncore
but offers no further details.
v2: rebase
References: HSD#4712857
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
d
Add this workaround for kbl revid A0 only.
v2: rebase
v3: carve out a non related workaround (Chris)
References: HSD#1911714
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --g
Past evidence with system hangs and hsds tie
WaForceEnableNonCoherent and WaDisableHDCInvalidation to
WaForceContextSaveRestoreNonCoherent. Documentation
states that WaForceContextSaveRestoreNonCoherent would
not be needed on skl past E0 but evidence proved otherwise. See
commit <510650e8b2ab> ("dr
Workaround for display underrun issues with Y & Yf Tiling.
Set this on all gen9 as stated by bspec.
v2: proper workaround name
References: HSD#2136383, BSID#857
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c |
Extend the scope of this workaround, already used in skl,
to also take effect in kbl.
v2: Fix KBL_REVID_E0 (Matthew)
References: HSD#2132677
Cc: Matthew Auld
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel
This is needed for all kbl revision.
v2: Don't add revid checks to generic gen9 init (Arun)
References: HSD#2135593
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i
We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.
v2: Don't add revid checks to gen9 init workarounds (Arun)
References: HSD#2126660
Cc: Arun Siluvery
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew
The revision id range for this workaround has changed. So apply
it to all revids on all gen9.
References: HSD#2134449
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git
Kabylake is part of gen9 family so init the generic gen9
workarounds for it.
v2: rebase
Signed-off-by: Mika Kuoppala
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++---
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/dri
== Series Details ==
Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
URL : https://patchwork.freedesktop.org/series/8164/
State : failure
== Summary ==
Series 8164v2 drm/atomic: Provide default ->best_encoder() behavior
http://patchwork.freedesktop.org/api/1.0/series/8164/
On 07/06/16 11:54, Dave Gordon wrote:
On 07/06/16 09:43, Patchwork wrote:
== Series Details ==
Series: series starting with [1/3] drm/i915/guc: fix GuC
loading/submission check
URL : https://patchwork.freedesktop.org/series/8380/
State : failure
== Summary ==
Series 8380v1 Series without c
Op 07-06-16 om 14:03 schreef Patchwork:
> == Series Details ==
>
> Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
> URL : https://patchwork.freedesktop.org/series/8164/
> State : success
>
> == Summary ==
>
> Series 8164v2 drm/atomic: Provide default ->best_encoder() behavio
== Series Details ==
Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
URL : https://patchwork.freedesktop.org/series/8164/
State : success
== Summary ==
Series 8164v2 drm/atomic: Provide default ->best_encoder() behavior
http://patchwork.freedesktop.org/api/1.0/series/8164/
On 03/06/16 17:08, Chris Wilson wrote:
Since the tests can and do explicitly check debugfs/i915_ring_missed_irqs
for the handling of a "missed interrupt", adding it to the dmesg at INFO
is just noise. When it happens for real, we still class it as an ERROR.
Signed-off-by: Chris Wilson
---
dr
On 03/06/16 17:08, Chris Wilson wrote:
Borrow the idea from intel_lrc.c to precompute the mask of interrupts we
wish to always enable to avoid having lots of conditionals inside the
interrupt enabling.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 +++--
Op 01-06-16 om 19:07 schreef john.c.harri...@intel.com:
> From: John Harrison
>
> The notify function can be called many times without the seqno
> changing. Some are to prevent races due to the requirement of not
> enabling interrupts until requested. However, when interrupts are
> enabled the IRQ
On 03/06/16 17:08, Chris Wilson wrote:
With only a single callsite for intel_engine_cs->irq_get and ->irq_put,
we can reduce the code size by moving the common preamble into the
caller, and we can also eliminate the reference counting.
For completeness, as we are no longer doing reference count
On 03/06/16 17:08, Chris Wilson wrote:
Under the assumption that enabling signaling will be a frequent
operation, lets preallocate our attachments for signaling inside the
request struct (and so benefiting from the slab cache).
Oh you did this part which I suggested in the previous patch. :)
On 07/06/16 13:02, Maarten Lankhorst wrote:
Op 02-06-16 om 15:25 schreef Tvrtko Ursulin:
[snip]
+return;
+
+if (!fence_locked)
+spin_lock_irqsave(&engine->fence_lock, flags);
Not called from hard irq context so can be just spin_lock_irq.
But if you agree to go with the
Op 01-06-16 om 19:07 schreef john.c.harri...@intel.com:
> From: John Harrison
>
> Added the '_complete' trace event which occurs when a fence/request is
> signaled as complete. Also moved the notify event from the IRQ handler
> code to inside the notify function itself.
>
> v3: Added the current r
On 06/06/2016 18:30, Tvrtko Ursulin wrote:
On 03/06/16 17:08, Chris Wilson wrote:
Currently __i915_wait_request uses a per-engine wait_queue_t for the dual
purpose of waking after the GPU advances or for waking after an error.
In the future, we may add even more wake sources and require greater
On 07/06/16 12:42, Maarten Lankhorst wrote:
Op 02-06-16 om 13:07 schreef Tvrtko Ursulin:
[snip]
+static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
+ bool lazy_coherency)
+{
+return fence_is_signaled(&req->fence);
+}
I would squash
Op 01-06-16 om 19:07 schreef john.c.harri...@intel.com:
> From: John Harrison
>
> The change to the implementation of i915_gem_request_completed() means
> that the lazy coherency flag is no longer used. This can now be
> removed to simplify the interface.
>
> v6: Updated to newer nightly and resol
On 03/06/16 17:08, Chris Wilson wrote:
If we convert the tracing over from direct use of ring->irq_get() and
over to the breadcrumb infrastructure, we only have a single user of the
ring->irq_get and so we will be able to simplify the driver routines
(eliminating the redundant validation and irq
== Series Details ==
Series: drm/atomic: Provide default ->best_encoder() behavior (rev2)
URL : https://patchwork.freedesktop.org/series/8164/
State : success
== Summary ==
Series 8164v2 drm/atomic: Provide default ->best_encoder() behavior
http://patchwork.freedesktop.org/api/1.0/series/8164/
Op 02-06-16 om 15:25 schreef Tvrtko Ursulin:
>
> On 01/06/16 18:07, john.c.harri...@intel.com wrote:
>> From: John Harrison
>>
>> The intended usage model for struct fence is that the signalled status
>> should be set on demand rather than polled. That is, there should not
>> be a need for a 'sign
We have a 1:1 relationship between connectors and encoders, and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder(),
and let the core call drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/bridge/analogix-anx78xx.c | 8 --
We have a 1:1 relationship between connectors and encoders, and the driver
is relying on the atomic helpers: we can drop the custom ->best_encoder(),
and let the core call drm_atomic_helper_best_encoder() for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/bridge/parade-ps8622.c | 10
We have a 1:1 relationship between connectors and encoders and the
driver is relying on the atomic helpers: we can drop the custom
->best_encoder(), and let the core call drm_atomic_helper_best_encoder()
for us.
Signed-off-by: Boris Brezillon
---
drivers/gpu/drm/arc/arcpgu_hdmi.c | 18 --
We have a 1:1 relationship between connectors and encoders, which means
we can rely on the drm_atomic_helper_best_encoder() behavior.
We still have to explicitly assign ->best_encoder() to
drm_atomic_helper_best_encoder(), because the automated fallback to
drm_atomic_helper_best_encoder() when ->b
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