[Intel-gfx] ✗ Ro.CI.BAT: warning for Add USB typeC based DP support for BXT platform (rev6)

== Series Details == Series: Add USB typeC based DP support for BXT platform (rev6) URL : https://patchwork.freedesktop.org/series/1731/ State : warning == Summary == Series 1731v6 Add USB typeC based DP support for BXT platform http://patchwork.freedesktop.org/api/1.0/series/1731/revisions/6/

[Intel-gfx] [PATCH 2/5] drm/i915: Remove ddi_pll_sel from intel_crtc_state

From: Ander Conselvan de Oliveira The value of ddi_pll_sel is derived from the selection of shared dpll, so just calculate the final value when necessary. Reviewed-by: Durgadoss R Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_ddi.c | 33 ++

[Intel-gfx] [PATCHv5 5/5] drm/i915/dp: Enable Upfront link training for typeC DP support on BXT

To support USB type C alternate DP mode, the display driver needs to know the number of lanes required by the DP panel as well as number of lanes that can be supported by the type-C cable. Sometimes, the type-C cable may limit the bandwidth even if Panel can support more lanes. To address these sce

[Intel-gfx] [PATCH 1/5] drm/i915: Don't pass crtc_state to intel_dp_set_link_params()

From: Ander Conselvan de Oliveira Decouple intel_dp_set_link_params() from struct intel_crtc_state. This will be useful for implementing DP upfront link training. Reviewed-by: Durgadoss R Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_ddi.c| 3 ++- drivers/gpu/

[Intel-gfx] [PATCH 3/5] drm/i915: Split intel_ddi_pre_enable() into DP and HDMI versions

From: Ander Conselvan de Oliveira Split intel_ddi_pre_enable() into encoder type specific versions that don't depend on crtc_state. The necessary parameters are passed as function arguments. This split will be necessary for implementing DP upfront link training. Reviewed-by: Durgadoss R Signed-

[Intel-gfx] [PATCHv5 0/5] Add USB typeC based DP support for BXT platform

This patch series adds upfront link training support to enable USB type C based DP on BXT platform. To support USB type C alternate DP mode, the display driver needs to know the number of lanes required by the DP panel as well as number of lanes that can be supported by the type-C cable. Sometimes

[Intel-gfx] [PATCHv2 4/5] drm/i915: Split bxt_ddi_pll_select()

Split out of bxt_ddi_pll_select() the logic that calculates the pll dividers and dpll_hw_state into a new function that doesn't depend on crtc state. This will be used for enabling the port pll when doing upfront link training. v2: * Refactored code so that bxt_clk_div need not be exported (Durga)

[Intel-gfx] ✗ Ro.CI.BAT: failure for Introduce the implementation of GVT context

== Series Details == Series: Introduce the implementation of GVT context URL : https://patchwork.freedesktop.org/series/7208/ State : failure == Summary == Series 7208v1 Introduce the implementation of GVT context http://patchwork.freedesktop.org/api/1.0/series/7208/revisions/1/mbox Test core

[Intel-gfx] [PATCH 08/15] drm/i915: Introduce an option for skipping engine context initialization

GVT-g will copy guest context into GVT LRC context before using it, so engine context initialization is not necessary. This patch introduces an option, and caller could configure it to choose if the engine context initialization should be skipped. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i91

[Intel-gfx] [PATCH 11/15] drm/i915: Introduce execlist context status change notification

This patch introduces an approach to track the execlist context status change. GVT-g uses GVT context as the "shadow context". The content inside GVT context will be copied back to guest after the context is idle. So GVT-g has to know the status of the execlist context. This function is configura

[Intel-gfx] [PATCH 14/15] drm/i915: Factor out and expose i915_steal_fence()

Factor out and expose fence stealing functionality for GVT-g. GVT-g will use i915_find_fence_reg() to find a free/unpin fence register and use i915_steal_fence() to steal it. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_fence.c | 39

[Intel-gfx] [PATCH 13/15] drm/i915: Introduce GVT context creation API

GVT workload scheduler needs special host LRC contexts, the so called "shadow LRC context" to submit guest workload to host i915. During the guest workload submission, GVT fills the shadow LRC context with the content of guest LRC context: engine context is copied without changes, ring context is m

[Intel-gfx] [PATCH 07/15] drm/i915: Populate context PDPs if it has a PPGTT

As we allow contexts without PPGTT to be created, we should check if a context has a PPGTT before populating PDPs from it. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/intel_lrc.c | 29 - 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/

[Intel-gfx] [PATCH 05/15] drm/i915: Set ctx->ppgtt for aliasing PPGTT in context creation

Currently ctx->ppgtt would only be initialized when full PPGTT is used. For aliasing PPGTT mode, ctx->ppgtt will be set when LRC context is populated. This patch moves the assignment into i915_gem_create_context() for better code structure. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 02/15] drm/i915/gvt: Fold vGPU active check into inner functions

Fold vGPU related active check into the inner functions. (Kevin) Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 11 --- drivers/gpu/drm/i915/i915_vgpu.c| 10 -- drivers/gpu/drm/i915/i915_vgpu.h| 2 +- 3 files changed, 13 insertions(+), 10 deletions(-)

[Intel-gfx] [PATCH 09/15] drm/i915: Make ring buffer size configurable

This patch introduces an option for configuring ring buffer size during context creation. If no ring buffer size is specified, the default size (4 * PAGE_SIZE) will be used. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 8 ++-- 2 files

[Intel-gfx] [PATCH 01/15] drm/i915: Factor out i915_pvinfo.h

As the PVINFO page definition is used by both GVT-g guest (vGPU) and GVT-g host (GVT-g kernel device model), factor it out for better code structure. v3: Take Joonas's comments: - Use offsetof to calculate the member offset of PVINFO structure Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 06/15] drm/i915: Allow the caller to create a intel_context without PPGTT

GVT context will use its own shadow PPGTT, and it doesn't need a i915_hw_ppgtt. This patch adds a "has_ppgtt" param to i915_gem_context(), which allows the caller to create a context without PPGTT Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_gem_context.c | 34 ++---

[Intel-gfx] [PATCH 00/15] Introduce the implementation of GVT context

Mostly this patchset introduces the implementation of GVT context. GVT context is a special GEM context used by GVT-g. GVT-g use it as the shadow context.It doesn't have a drm client nor a PPGTT. And it has a larger ring buffer with several special features need by GVT-g workload scheduler like con

[Intel-gfx] [PATCH 03/15] drm/i915: gvt: Introduce the basic architecture of GVT-g

This patch introduces the very basic framework of GVT-g device model, includes basic prototypes, definitions, initialization. v3: Take Joonas' comments: - Change file name i915_gvt.* to intel_gvt.* - Move GVT kernel parameter into intel_gvt.c - Remove redundant debug macros - Change error handling

[Intel-gfx] [PATCH 10/15] drm/i915: Generate addressing mode bit from flag in context.

Previously the addressing mode bit in context descriptor is generated from context PPGTT. As we allow context could be used without PPGTT, and we still need to know the addressing mode during context submission, a flag is introduced. And the addressing mode bit will be generated from this flag. S

[Intel-gfx] [PATCH 15/15] drm/i915: Expose i915_find_fence_reg()

Expose i915_find_fence_reg() for GVT-g to allocate the fence registers for vGPUs. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_fence.c | 10 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 12/15] drm/i915: Support context single submission

This patch introduces the support of context signle submission. As GVT context may come from different guests, which requires different configuration of render registers. It can't be combined in a dual ELSP submission combo. We make this function as a context feature in context creation service. O

[Intel-gfx] [PATCH 04/15] drm/i915: Introduce host graphics memory partition for GVT-g

From: Bing Niu This patch introduces host graphics memory partition when GVT-g is enabled. Under GVT-g, i915 host driver only owned limited graphics resources, others are managed by GVT-g resource allocator and kept for other vGPUs. v3: - Remove fence partition, will use i915 fence stealing in