== Series Details ==
Series: Pipe level color management (rev10)
URL : https://patchwork.freedesktop.org/series/2720/
State : failure
== Summary ==
Series 2720v10 Pipe level color management
http://patchwork.freedesktop.org/api/1.0/series/2720/revisions/10/mbox/
Test drv_hangman:
Subg
On 26 February 2016 at 15:43, Lionel Landwerlin
wrote:
> On 26/02/16 00:36, Emil Velikov wrote:
>>
>> Hi Lionel,
>>
>> A bunch of suggestions - feel free to take or ignore them :-)
>>
>> On 25 February 2016 at 10:58, Lionel Landwerlin
>> wrote:
> I'm not sure it matters as the drm_crtc_state you
On Wed, Feb 24, 2016 at 03:35:22PM +0100, Takashi Iwai wrote:
> The recent commit [0bdf5a05647a: drm/i915: Add reverse mapping between
> port and intel_encoder] introduced a reverse mapping to retrieve
> intel_dig_port object from the port number. The code assumed that the
> port vs intel_dig_port
On Fri, Feb 26, 2016 at 04:58:32PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Assorted changes in the areas of code cleanup, reduction of
> invariant conditional in the interrupt handler and lock
> contention and MMIO access optimisation.
>
> * Remove needless initialization.
> *
Sorry, Cc to Jani was missing mistakenly.
Please check this. It's a regression in 4.5-rc.
thanks,
Takashi
On Wed, 24 Feb 2016 15:35:22 +0100,
Takashi Iwai wrote:
>
> The recent commit [0bdf5a05647a: drm/i915: Add reverse mapping between
> port and intel_encoder] introduced a reverse mapping
We already pass the crtc id, so use the id to retrieve the index.
We'll change the way we pass the crtc id in the next commits, so we'll
have to call a function to calculate the index based on the id at that
point. Do the change now in order to avoid big commits later.
Signed-off-by: Paulo Zanoni
We're going to make our search for connnectors a little more
complicated, so extract the function since we're going to call it a
few more times.
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 70 ++--
1 file changed, 38 insertions(+), 32 de
All the tests I wrote always assumed that every connector supported
CRTC 0. This is not the case for BSW and possibly others, so fix the
tests before the CI reports more failures.
Signed-off-by: Paulo Zanoni
---
lib/igt_kms.c| 32
lib/igt_kms.
Instead of just giving preference to an eDP primary connector, give
preference to one that's eDP and supports pipe A, then try lesser
optimal combinations later.
We could try to make our test suite use different sets of connectors
when testing FBC and PSR, but that would require some rework, and w
Move it from pm_rpm.c to lib/igt_kms and remove the hardcoded version
from kms_frontbuffer_tracking. I'm also planning to add other callers.
Signed-off-by: Paulo Zanoni
---
lib/igt_kms.c| 18 ++
lib/igt_kms.h| 1 +
tests/kms_frontbuffer_tr
On Mon, Feb 22, 2016 at 6:33 AM, Imre Deak wrote:
> On to, 2016-02-18 at 08:56 -0800, Rodrigo Vivi wrote:
>> Imre, Patrik, do you know if I'm missing something or what I'm doing
>> wrong with this power domain handler for vblanks to avoid DC states
>> when we need a reliable frame counter in place
== Series Details ==
Series: drm/i915: Execlists small cleanups and micro-optimisations (rev2)
URL : https://patchwork.freedesktop.org/series/3853/
State : failure
== Summary ==
Series 3853v2 drm/i915: Execlists small cleanups and micro-optimisations
http://patchwork.freedesktop.org/api/1.0/se
== Series Details ==
Series: Capture more useful details in error state (rev3)
URL : https://patchwork.freedesktop.org/series/2906/
State : failure
== Summary ==
Series 2906v3 Capture more useful details in error state
http://patchwork.freedesktop.org/api/1.0/series/2906/revisions/3/mbox/
Tes
On Fri, Feb 26, 2016 at 05:00:21PM +, Daniel Stone wrote:
> Hi,
>
> On Fri, 2016-02-26 at 08:58 -0800, Matt Roper wrote:
> > Local variable num_connectors is never initialized before being
> > auto-incremented in the loop. If we wind up with a non-zero garbage
> > value, it will lead us to tr
On 02/26/2016 07:55 AM, John Harrison wrote:
> On 23/02/2016 20:42, Jesse Barnes wrote:
>> On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:
>>> From: John Harrison
>>>
>>> Added trace points to the scheduler to track all the various events,
>>> node state transitions and other interesting
This series introduces pipe level color management through a set of properties
attached to the CRTC. It also provides an implementation for some Intel
platforms.
This series is based of a previous set of patches by Shashank Sharma.
Cheers,
Lionel
v9: Rebase on nightly
v10: Mask GAMMA_MODE regi
Patch based on a previous series by Shashank Sharma.
v2: Update contributors
v3: Refactor degamma/gamma LUTs load into a single function
v4: Remove unused variable
Signed-off-by: Shashank Sharma
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
Signed-off-by: Lionel Landwerlin
Rev
Patch based on a previous series by Shashank Sharma.
v2: Do not read GAMMA_MODE register to figure what mode we're in
v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
Add documentation on how the Broadcast RGB property is affected by CTM
v4: Update contributors
v5: Refactor degamma/
Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.
v2: Read GAMMA_MODE register value at init (Matt Roper's comment)
v3: Read GAMMA_MODE register in intel_modeset_readout_hw_state along
with other registers (Matt Roper's comment).
v4: Mask GAMMA_MODE
The moves a couple of functions programming the gamma LUT and CSC
units into their own file.
On generations prior to Haswell there is only a gamma LUT. From
haswell on there is also a new enhanced color correction unit that
isn't used yet. This is why we need to set the GAMMA_MODE register,
either
Patch based on a previous series by Shashank Sharma.
This introduces optional properties to enable color correction at the
pipe level. It relies on 3 transformations applied to every pixels
displayed. First a lookup into a degamma table, then a multiplication
of the rgb components by a 3x3 matrix
Hi,
On Fri, 2016-02-26 at 08:58 -0800, Matt Roper wrote:
> Local variable num_connectors is never initialized before being
> auto-incremented in the loop. If we wind up with a non-zero garbage
> value, it will lead us to try to write to an out-of-bounds array
> index.
> We should probably initial
From: Tvrtko Ursulin
Assorted changes in the areas of code cleanup, reduction of
invariant conditional in the interrupt handler and lock
contention and MMIO access optimisation.
* Remove needless initialization.
* Improve cache locality by reorganizing code and/or using
branch hints to keep
On Thursday 18 February 2016 02:00 AM, Jani Nikula wrote:
On Mon, 15 Feb 2016, Deepak M wrote:
The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.
v2: Fixing compilation warning.
v3: Retained the
Local variable num_connectors is never initialized before being
auto-incremented in the loop. If we wind up with a non-zero garbage
value, it will lead us to try to write to an out-of-bounds array index.
We should probably initialize it to zero before use.
However on closer inspection, the plane_
== Series Details ==
Series: Capture more useful details in error state (rev3)
URL : https://patchwork.freedesktop.org/series/2906/
State : warning
== Summary ==
Series 2906v3 Capture more useful details in error state
http://patchwork.freedesktop.org/api/1.0/series/2906/revisions/3/mbox/
Tes
On Fri, Feb 26, 2016 at 03:37:35PM +, Tvrtko Ursulin wrote:
> - if (ring->disable_lite_restore_wa) {
> - /* Prevent a ctx to preempt itself */
> - if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
> - (submit_contexts != 0))
> - execli
== Series Details ==
Series: drm/i915: Execlists small cleanups and micro-optimisations
URL : https://patchwork.freedesktop.org/series/3853/
State : failure
== Summary ==
Series 3853v1 drm/i915: Execlists small cleanups and micro-optimisations
http://patchwork.freedesktop.org/api/1.0/series/38
From Gen8 onwards we apply ctx workarounds using special batch buffers that
execute during save/restore, good to have them in error state.
v2: use wa_ctx->size and print only size values (Mika)
v3: simplify conditions when recording and freeing object (Chris)
Cc: Chris Wilson
Cc: Mika Kuoppala
On 23/02/2016 20:42, Jesse Barnes wrote:
On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:
From: John Harrison
Added trace points to the scheduler to track all the various events,
node state transitions and other interesting things that occur.
v2: Updated for new request completion tra
On 26/02/16 00:36, Emil Velikov wrote:
Hi Lionel,
A bunch of suggestions - feel free to take or ignore them :-)
On 25 February 2016 at 10:58, Lionel Landwerlin
wrote:
Patch based on a previous series by Shashank Sharma.
This introduces optional properties to enable color correction at the
pi
On ti, 2016-02-23 at 16:54 +, Chris Wilson wrote:
> On Tue, Feb 23, 2016 at 05:09:29PM +0200, Imre Deak wrote:
> > On ti, 2016-02-23 at 14:55 +, Chris Wilson wrote:
> > > On Tue, Feb 23, 2016 at 04:47:17PM +0200, Imre Deak wrote:
> > [...]
> > > How's the separation of struct_mutex from rpm
From: Tvrtko Ursulin
Assorted changes in the areas of code cleanup, reduction of
invariant conditional in the interrupt handler and lock
contention and MMIO access optimisation.
* Remove needless initialization.
* Improve cache locality by reorganizing code and/or using
branch hints to keep
On Fri, Feb 26, 2016 at 04:53:03PM +0200, Mika Kuoppala wrote:
> Arun Siluvery writes:
>
> > From Gen8 onwards we apply ctx workarounds using special batch buffers that
> > execute during save/restore, good to have them in error state.
> >
> > v2: use wa_ctx->size and print only size values (Mika
Arun Siluvery writes:
> From Gen8 onwards we apply ctx workarounds using special batch buffers that
> execute during save/restore, good to have them in error state.
>
> v2: use wa_ctx->size and print only size values (Mika)
>
> Signed-off-by: Arun Siluvery
Reviewed-by: Mika Kuoppala
> ---
>
== Series Details ==
Series: Shared pll improvements
URL : https://patchwork.freedesktop.org/series/3850/
State : failure
== Summary ==
Series 3850v1 Shared pll improvements
http://patchwork.freedesktop.org/api/1.0/series/3850/revisions/1/mbox/
Test kms_flip:
Subgroup basic-flip-vs-dp
On 26/02/2016 09:13, Joonas Lahtinen wrote:
Hi,
The below answers are reasonable. So v6 should be the version.
Are you planning on looking at the other patches first or are you going
to wait until v6 is posted?
Thanks,
John.
___
Intel-gfx mailing
On pe, 2016-02-26 at 00:20 +0200, Imre Deak wrote:
> On Thu, 2016-02-25 at 21:10 +, Chris Wilson wrote:
> > commit 09731280028ce03e6a27e1998137f1775a2839f3
> > Author: Imre Deak
> > Date: Wed Feb 17 14:17:42 2016 +0200
> >
> > drm/i915: Add helper to get a display power ref if it was
>
Move the declarations related to shared dplls from i915_drv.h to their
own header file.
The code that became the shared dpll infrastructre was first introcude
in commit ee7b9f93fd96 ("drm/i915: manage PCH PLLs separately from
pipes"), hence the 2012-2016 copyright years in the new header file.
Si
The function intel_get_shared_dpll() had a more or less generic
implementation with some platform specific checks to handle smaller
differences between platforms. However, the minimalist approach forces
bigger differences between platforms to be implemented outside of the
shared dpll code (see the
Manage the LCPLLs used with DisplayPort, so that all the HSW/BDW DPLLs
are managed by the shared dpll code.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c | 18
drivers/gpu/drm/i915/intel_display.c | 35
drivers/gpu/drm/i915/intel
Move shared dpll function prototype together with other shared dpll
definitions.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dpll_mgr.h | 30 ++
drivers/gpu/drm/i915/intel_drv.h | 28
2 files changed, 30
Include DPLL0 in the managed dplls for SKL/KBL. While it has to be kept
enabled because of it driving CDCLK, it is better to special case that
inside the DPLL code than in the higher level.
Signed-off-by: Ander Conselvan de Oliveira
---
I wasn't able to test this patch. Would really appreciate
Use a table to store the per-platform shared dpll information in one
place. This way, there is no need for platform specific init funtions.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 16 +--
drivers/gpu/drm/i915/intel_dpll_mgr.c | 189 +++
Create the new file intel_dpll_mgr.c and move the shared dpll code to
it. Follow up patches that reorganize pll handling will move more code
there and tweak the interface.
No functional changes.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/Makefile | 1 +
drive
Make the code neater by splitting the code for platforms with fixed PLL
to their own functions and splitting the logic for finding a shareable
or unused pll from the logic for setting it up.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 109 +
Hi,
This patch series attempts to improve the shared pll interfaces. The
idea is to hide the details of which PLL to use behind the call to
intel_get_shared_dpll(), instead of having the weird mix currently
used with DDI platforms. I plan to keep working on the interfaces to
make it usuable by oth
No functional changes.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c | 472 --
drivers/gpu/drm/i915/intel_dpll_mgr.c | 472 ++
drivers/gpu/drm/i915/intel_drv.h | 1 -
3 files changed, 4
Move the code for selecting plls for SKL/KLB into the shared dpll code,
so that the platform specific details are hidden behind that interface.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c | 301 +
drivers/gpu/drm/i915/inte
Change the type of intel_crtc_state->shared_dpll to be a pointer to a
shared dpll. With this there is no need to first convert the id stored
in the crtc state to a pointer in order to use it. It does introduce a
bit of hassle on doing the opposite.
The long term objective is to hide details about
Move the code for selecting and configuring HSW/BDW DDI PLLs into the
shared dpll infrastructure. With this most of the PLL selection logic
for those platforms is in one place. DisplayPort is handled separately,
but that should be fixed on a follow up patch. It also allows a small
clean up of the S
Move the code for configurating BXT plls into the shared dpll code, so
that the platform specific details are hidden behind that interface.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c | 141 +-
drivers/gpu/drm/i915/intel_d
Hi,
On pe, 2016-02-26 at 13:21 +0800, Zhi Wang wrote:
>
> On 02/24/16 15:42, Tian, Kevin wrote:
> >
> > >
> > > From: Wang, Zhi A
> > > Sent: Tuesday, February 23, 2016 9:23 PM
> > > >
> > > > >
> > > > > --- a/drivers/gpu/drm/i915/gvt/gvt.c
> > > > > +++ b/drivers/gpu/drm/i915/gvt/gvt.c
> >
On 26/02/16 13:13, Tvrtko Ursulin wrote:
On 26/02/16 12:28, Patchwork wrote:
== Series Details ==
Series: drm/i915: Execlists cannot pin a context without the object
URL : https://patchwork.freedesktop.org/series/3845/
State : failure
== Summary ==
Series 3845v1 drm/i915: Execlists canno
On 26/02/16 12:10, Tvrtko Ursulin wrote:
On 26/02/16 11:27, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915: Rename vma->*_list to
*_link for consistency
URL : https://patchwork.freedesktop.org/series/3844/
State : failure
== Summary ==
Series 3844v1 Ser
Hi,
On to, 2016-02-25 at 15:02 +, Wang, Zhi A wrote:
>
> -Original Message-
> From: Tian, Kevin
> Sent: Wednesday, February 24, 2016 4:50 PM
> To: Wang, Zhi A; intel-gfx@lists.freedesktop.org; igv...@lists.01.org
> Cc: Lv, Zhiyuan; Niu, Bing; Song, Jike; daniel.vet...@ffwll.ch;
> Co
On 26/02/16 12:28, Patchwork wrote:
== Series Details ==
Series: drm/i915: Execlists cannot pin a context without the object
URL : https://patchwork.freedesktop.org/series/3845/
State : failure
== Summary ==
Series 3845v1 drm/i915: Execlists cannot pin a context without the object
http://p
This could happen when the selected pipe cannot be used with the connected
port due do HW constrains.
v2: Apply review comment (Marius)
bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86763
Signed-off-by: Gabriel Feceoru
---
tests/kms_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1
== Series Details ==
Series: drm/i915: Execlists cannot pin a context without the object
URL : https://patchwork.freedesktop.org/series/3845/
State : failure
== Summary ==
Series 3845v1 drm/i915: Execlists cannot pin a context without the object
http://patchwork.freedesktop.org/api/1.0/series/
On 26/02/16 11:27, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915: Rename vma->*_list to *_link for
consistency
URL : https://patchwork.freedesktop.org/series/3844/
State : failure
== Summary ==
Series 3844v1 Series without cover letter
http://patchwork.
== Series Details ==
Series: series starting with [1/2] drm/i915: Rename vma->*_list to *_link for
consistency
URL : https://patchwork.freedesktop.org/series/3844/
State : failure
== Summary ==
Series 3844v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/3844/revi
On 23/02/16 13:08, Michel Thierry wrote:
On Tue, Feb 23, 2016 at 11:21 AM, Patchwork
wrote:
== Series Details ==
Series: drm/i915/gen9: Set value of Indirect Context Offset based on gen
version (rev4)
URL : https://patchwork.freedesktop.org/series/3629/
State : warning
== Summary ==
Serie
On 25/02/16 14:22, Michel Thierry wrote:
On Thu, Feb 25, 2016 at 11:10 AM, Patchwork
wrote:
== Series Details ==
Series: drm/i915/lrc: Only set RS ctx enable in ctx control reg if there
is a RS (rev2)
URL : https://patchwork.freedesktop.org/series/3725/
State : failure
== Summary ==
Serie
From: Chris Wilson
Given that the intel_lr_context_pin cannot succeed without the object,
we cannot reach intel_lr_context_unpin() without first allocating that
object - so we can remove the redundant test.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel
== Series Details ==
Series: drm/i915: Adaptive backoff delay on link training
URL : https://patchwork.freedesktop.org/series/3843/
State : failure
== Summary ==
Series 3843v1 drm/i915: Adaptive backoff delay on link training
http://patchwork.freedesktop.org/api/1.0/series/3843/revisions/1/mbo
On Cherryview PIPE_C can only be connected to PORT_D (bspec).
The driver properly reports the crtc_mask for the encoder, however the
mismatch between pipe and port is not reported back to the test.
Add support for detecting this case so the test can be skipped.
v2: Apply review comments (Marius)
From: Chris Wilson
The multiple levels of indirect do nothing but hinder the compiler and
the pointer chasing turns to be quite painful but painless to fix.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
Reviewed-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_debugfs.c| 13 ++
From: Chris Wilson
Elsewhere we have adopted the convention of using '_link' to denote
elements in the list (and '_list' for the actual list_head itself), and
that the name should indicate which list the link belongs to (and
preferrably not just where the link is being stored).
s/vma_link/obj_li
On Fri, 2016-02-26 at 07:00 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Balance assert_rpm_wakelock_held() for
> !IS_ENABLED(CONFIG_PM)
> URL : https://patchwork.freedesktop.org/series/3827/
> State : failure
>
> == Summary ==
>
> Series 3827v1 drm/i915: Balance assert
If the panel don't give us the information how long to wait
before starting a new link training phase, it is not productive
to poke it at 100us or 400us intervals and then give up if it
fails to respond in time. Instead gradually increase the training
delay so that we reach the slower kind and get
On ti, 2016-02-23 at 20:58 +1000, Adam Nielsen wrote:
> >
> > Can you attach a full dmesg from boot until the problem appears?
> Attached, thanks for your reply.
>
> You can ignore the problem at T=1032000, that was a broken floppy disk
> in a USB floppy drive. The first possibly-GPU-related pro
daniele.ceraolospu...@intel.com writes:
> From: Daniele Ceraolo Spurio
>
> The hangcheck logic will not flag an hang if acthd keeps increasing.
> However, if a malformed batch jumps to an invalid offset in the ppgtt it
> can potentially continue executing through the whole address space
> without
Hi,
The below answers are reasonable. So v6 should be the version.
Regards, Joonas
On pe, 2016-02-19 at 17:03 +, John Harrison wrote:
> On 19/02/2016 13:03, Joonas Lahtinen wrote:
> >
> > Hi,
> >
> > Now the code is in reviewable chunks, excellent!
> >
> > I've added my comments below. A
Hello everybody,
I am running a Lenovo Thinkpad X250 with this graphics controller:
00:02.0 VGA compatible controller: Intel Corporation Broadwell-U Integrated
Graphics (rev 09)
Everything works just fine when using the integrated display.
The notebook is connected to a docking station with two
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