WW08 Regression report.
There was no new regressions last week.
Previous regressions
+---+---+++
| BugId | Summary | Created on | Bisect |
+---+---
Hi Lionel,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20160219]
[cannot apply to v4.5-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Lionel
Hi all,
We have a duplicated patch on drm-intel-nightly
commits d7006964d and cc1de6e80q
causing:
drivers/gpu/drm//amd/amdgpu/amdgpu_ttm.c:818:6: error: redefinition of
‘amdgpu_ttm_tt_affect_userptr’
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
^
drivers/gpu
On Fri, Feb 19, 2016 at 04:24:34PM -0500, Rafael Antognolli wrote:
> This new test makes some basic testing on the proposed drm_dp_aux_dev
> interface. If the feature is enabled and the drm_dp_aux_dev class is
> present, it will check for available DP aux channels and test them for:
> - basic
This new test makes some basic testing on the proposed drm_dp_aux_dev
interface. If the feature is enabled and the drm_dp_aux_dev class is
present, it will check for available DP aux channels and test them for:
- basic seek to 0 and read 1 byte
- seek to the last address and read, t
Em Qua, 2016-02-17 às 08:40 +, Patchwork escreveu:
> == Summary ==
>
> Series 3500v1 drm/i915/fbc: enable FBC by default on HSW and BDW
> http://patchwork.freedesktop.org/api/1.0/series/3500/revisions/1/mbox
> /
>
> Test pm_rpm:
> Subgroup basic-pci-d3-state:
> pass
On 02/19/2016 11:53 AM, Ville Syrjälä wrote:
> On Fri, Feb 19, 2016 at 11:28:05AM -0800, Jesse Barnes wrote:
>> On 02/18/2016 06:26 AM, john.c.harri...@intel.com wrote:
>>> From: John Harrison
>>>
>>> MMIO flips are the preferred mechanism now but more importantly, pipe
>>> based flips cause issue
* Tore Anderson
> * Ville Syrjälä
>
> > Could you test the following hack while using a 1920x1080 mode with
> > 148.5 MHz dotclock, and see if there's any improvement?
>
> I think it might be an improvement, that is, the blanking/flickers
> seems to occur less often than it did with 8ed1804, b
On Fri, Feb 19, 2016 at 11:28:05AM -0800, Jesse Barnes wrote:
> On 02/18/2016 06:26 AM, john.c.harri...@intel.com wrote:
> > From: John Harrison
> >
> > MMIO flips are the preferred mechanism now but more importantly, pipe
> > based flips cause issues for the scheduler. Specifically, submitting
>
On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> GPU page faults can now require scheduler operation in order to
> complete. For example, in order to free up sufficient memory to handle
> the fault the handler must wait for a batch buffer to complete that
> has n
On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The scheduler keeps its own lock on various DRM objects in order to
> guarantee safe access long after the original execbuff IOCTL has
execbuf is getting bigger, but I'm not sure if it qualifies as "buff" yet.
I
On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The scheduler needs to track interdependencies between batch buffers.
> These are calculated by analysing the object lists of the buffers and
> looking for commonality. The scheduler also needs to keep those
> buff
On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Updated the execbuffer() code to pass the packaged up batch buffer
> information to the scheduler rather than calling execbuffer_final()
> directly. The scheduler queue() code is currently a stub which simply
> cha
On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Ring space is reserved when constructing a request to ensure that the
> subsequent 'add_request()' call cannot fail due to waiting for space
> on a busy or broken GPU. However, the scheduler jumps in to the middle
On 02/18/2016 06:26 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> MMIO flips are the preferred mechanism now but more importantly, pipe
> based flips cause issues for the scheduler. Specifically, submitting
> work to the rings around the side of the scheduler could cause that
> w
On Fri, Feb 19, 2016 at 08:20:27AM -, Patchwork wrote:
> == Summary ==
>
> Series 3599v1 drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when
> power well is down
> http://patchwork.freedesktop.org/api/1.0/series/3599/revisions/1/mbox/
>
> Test core_auth:
> Subgroup basic-a
On 02/18/2016 06:26 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Hardware sempahores require seqno values to be continuously
> incrementing. However, the scheduler's reordering of batch buffers
> means that the seqno values going through the hardware could be out of
> order. Thu
On 02/18/2016 06:26 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> A major point of the GPU scheduler is that it re-orders batch buffers
> after they have been submitted to the driver. This leads to requests
> completing out of order. In turn, this means that the retire
> processi
From: Ville Syrjälä
for_each_pipe_masked() can be used to iterate over the pipes
included in the user provided pipe mask. Removes a few lines of
duplicated code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_irq.c | 27 +---
From: Ville Syrjälä
Starting from BDW the DE_PIPE interrupts for pipe B and C belong to the
relevant display power well. So we should make sure we've finished
processing them before turning off the power well.
The pipe interrupts shouldn't really happen at this point anymore since
we've already
LGTM.
Reviewed-by: Alex Dai
Thanks,
Alex
On 02/03/2016 04:56 AM, Dave Gordon wrote:
Split the function of "enable_guc_submission" into two separate options.
The new one "enable_guc_loading" controls only the *fetching and loading*
of the GuC firmware image. The existing one is redefined to co
On 19/02/2016 13:03, Joonas Lahtinen wrote:
Hi,
Now the code is in reviewable chunks, excellent!
I've added my comments below. A few repeats from last round, but now
with more questions about the logic itself.
On to, 2016-02-18 at 14:26 +, john.c.harri...@intel.com wrote:
From: John Harri
From: Ville Syrjälä
After we've told the irq code we don't want to handle display irqs
anymore, we must make sure any display irq handling already
kicked off has finished before we actually turn off the power well.
I wouldn't expect PIPESTAT based interrupts to occur anymore since
vblanks/page f
On Fri, Feb 19, 2016 at 05:37:49PM +0200, Imre Deak wrote:
> On to, 2016-02-18 at 21:54 +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > PIPESTAT registers live in the display power well on VLV/CHV, so we
> > shouldn't access them when things are powered down. Let's che
This test enables testing of :
* degamma LUTs
* csc matrix
* gamma LUTs
* legacy gamma LUTs
v2: turn assert into require to skip on platform not supporting color
management
v3: add invalid blob ids tests
v4: Try to match CRC results against several values around the
This is a helper to draw a gradient between 2 colors.
Signed-off-by: Lionel Landwerlin
---
lib/igt_fb.c | 34 ++
lib/igt_fb.h | 3 +++
lib/igt_kms.c | 2 +-
3 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 5f2313
Signed-off-by: Lionel Landwerlin
---
lib/igt_debugfs.c | 17 +
lib/igt_debugfs.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index c291ef3..a32ed78 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -252,6 +252,23 @@ bool ig
v2: Rename CTM_MATRIX property to CTM
Signed-off-by: Lionel Landwerlin
---
lib/igt_kms.c | 74 +++
lib/igt_kms.h | 17 +-
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index dd4ca45
Signed-off-by: Lionel Landwerlin
---
lib/igt_kms.c | 1 +
lib/igt_kms.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 90c8da7..dd4ca45 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1047,6 +1047,7 @@ void igt_display_init(igt_display_t *display, int
Hi,
This series enables testing pipe level color management using kernel patches
from this serie :
https://patchwork.freedesktop.org/series/2720/
Most of the tests use pipe CRCs to check the results by comparing the output
with the expected output drawn using cairo.
Cheers,
Lionel
Lionel Land
Patch based on a previous series by Shashank Sharma.
This introduces optional properties to enable color correction at the
pipe level. It relies on 3 transformations applied to every pixels
displayed. First a lookup into a degamma table, then a multiplication
of the rgb components by a 3x3 matrix
Patch based on a previous series by Shashank Sharma.
v2: Update contributors
v3: Refactor degamma/gamma LUTs load into a single function
Signed-off-by: Shashank Sharma
Signed-off-by: Lionel Landwerlin
Signed-off-by: Kumar, Kiran S
Signed-off-by: Kausal Malladi
---
drivers/gpu/drm/i915/i915_
This series introduces pipe level color management through a set of properties
attached to the CRTC. It also provides an implementation for some Intel
platforms.
This series is based of a previous set of patches by Shashank Sharma.
Cheers,
Lionel
Lionel Landwerlin (5):
drm/i915: Extract out g
Patch based on a previous series by Shashank Sharma.
v2: Do not read GAMMA_MODE register to figure what mode we're in
v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0
Add documentation on how the Broadcast RGB property is affected by CTM
v4: Update contributors
v5: Refactor degamma/
Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/intel_color.c | 7 +--
drivers/gpu/drm/i915/intel_drv.h | 3 +++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
The moves a couple of functions programming the gamma LUT and CSC
units into their own file.
On generations prior to Haswell there is only a gamma LUT. From
haswell on there is also a new enhanced color correction unit that
isn't used yet. This is why we need to set the GAMMA_MODE register,
either
On to, 2016-02-18 at 21:54 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> PIPESTAT registers live in the display power well on VLV/CHV, so we
> shouldn't access them when things are powered down. Let's check
> whether the display interrupts are on or off before accessing th
On Tue, 16 Feb 2016, Daniel Vetter wrote:
> On Tue, Feb 16, 2016 at 01:18:12PM +0200, Jani Nikula wrote:
>> We've given write permissions to dynamically change some module
>> parameters through /sys/module/i915/parameters although they only
>> support setting on module load. Fix the permissions.
>
On 19/02/2016 14:58, Michel Thierry wrote:
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
v2: Move it into a function (Arun), use MISSING_CASE (Chris)
Cc: Arun Siluvery
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c |
Hi Gurus:
Would you mind to shed some lights about this patchset? :) Thanks. Would
greatly appreciate for comments and ideas so that I could refactor and improve
it as much as possible. :)
Thanks,
Zhi.
-Original Message-
From: Wang, Zhi A
Sent: Thursday, February 18, 2016 7:42 PM
T
On Thu, Feb 11, 2016 at 02:10:19PM +, Tvrtko Ursulin wrote:
>
> On 11/02/16 13:29, Chris Wilson wrote:
> >On Thu, Feb 11, 2016 at 01:20:46PM +, Tvrtko Ursulin wrote:
> >>
> >>
> >>On 11/01/16 10:45, Chris Wilson wrote:
> >>>By tracking the iomapping on the VMA itself, we can share that are
Okay, so I screwed up the conflict resolution in our integration
tree. Nothing to worry about here, as long as whoever does the
merge/backmerge with the real trees doesn't do the same mistake.
BR,
Jani.
On Fri, 19 Feb 2016, kbuild test robot wrote:
> tree: git://anongit.freedesktop.org/drm-i
On Fri, Feb 19, 2016 at 02:52:18PM +, Tvrtko Ursulin wrote:
>
> On 19/02/16 14:34, Chris Wilson wrote:
> >On Fri, Feb 19, 2016 at 02:10:44PM +, Tvrtko Ursulin wrote:
> >>On 19/02/16 12:29, Chris Wilson wrote:
> >>>Exactly, we want the iomap/vmap caching thingy first :) But the
> >>>retired
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
v2: Move it into a function (Arun), use MISSING_CASE (Chris)
Cc: Arun Siluvery
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 26 --
1 file changed
On ke, 2016-02-17 at 21:41 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> LPT/WPT-H are limited to max 180 MHz CRT dotclock. Most other
> platforms
> have a limit of 350 MHz. Supposedly gen3 and gen4 go up to 400 MHz.
>
> VLV is a bit special since the docs are poor. Suppo
tree: git://anongit.freedesktop.org/drm-intel drm-intel-nightly
head: e7d04bf9d65001191a0b64e322bffa713280d132
commit: a77c4b431c465402d508e1c53a55ab9a11c2471f [2/7] Merge remote-tracking
branch 'drm-upstream/drm-next' into drm-intel-nightly
config: i386-allmodconfig (attached as .config)
repr
On 19/02/16 14:34, Chris Wilson wrote:
On Fri, Feb 19, 2016 at 02:10:44PM +, Tvrtko Ursulin wrote:
On 19/02/16 12:29, Chris Wilson wrote:
Exactly, we want the iomap/vmap caching thingy first :) But the
retired work queue disappears as a fallout of your previous-context idea
anyway plus the
On Fri, Feb 19, 2016 at 02:10:44PM +, Tvrtko Ursulin wrote:
>
> On 19/02/16 12:29, Chris Wilson wrote:
> >On Fri, Feb 19, 2016 at 12:08:14PM +, Tvrtko Ursulin wrote:
> >>
> >>Hi,
> >>
> >>On 11/01/16 10:44, Chris Wilson wrote:
> >>>[ 196.988204] clocksource: timekeeping watchdog: Marking
On Fri, Feb 19, 2016 at 02:10:44PM +, Tvrtko Ursulin wrote:
> On 19/02/16 12:29, Chris Wilson wrote:
> >Exactly, we want the iomap/vmap caching thingy first :) But the
> >retired work queue disappears as a fallout of your previous-context idea
> >anyway plus the fix to avoid the struct_mutex wh
On Thu, 18 Feb 2016, Jani Nikula wrote:
> The bash completion package makes life a whole lot easier than using the
> builtin bash completion features. It's quite likely anyone using
> completion in bash already has it installed.
I boldly went ahead and pushed the lot. Please scream if
https://xkc
On Fri, Feb 19, 2016 at 02:05:11PM +, Michel Thierry wrote:
> The cache line offset for the Indirect CS context (0x21C8) varies from gen
> to gen.
>
> Cc: Arun Siluvery
> Signed-off-by: Michel Thierry
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
> 1 file changed, 19
On Fri, Feb 19, 2016 at 04:09:03PM +0200, Mika Kuoppala wrote:
> If we have runaway head moving out of allocated address space,
> that space is mapped to point into scratch page. The content of scratch
> page is is zero (MI_NOOP). This leads to actual head proceeding
> unhindered towards the end of
On ke, 2016-02-17 at 21:41 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Rather than assume the VGA dotclock is really the FDI based thing,
> let's read out the real thing via iclkip, and after readout it'll
> get to compare it with the FDI based number to make sure they'r
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, February 19, 2016 7:38 PM
> To: Deepak, M
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Get the i2c bus number from the
> ACPI
>
> On Fri, Feb 19, 2016
On 19/02/16 12:29, Chris Wilson wrote:
On Fri, Feb 19, 2016 at 12:08:14PM +, Tvrtko Ursulin wrote:
Hi,
On 11/01/16 10:44, Chris Wilson wrote:
[ 196.988204] clocksource: timekeeping watchdog: Marking clocksource 'tsc' as
unstable because the skew is too large:
[ 196.988512] clocksource
If we have runaway head moving out of allocated address space,
that space is mapped to point into scratch page. The content of scratch
page is is zero (MI_NOOP). This leads to actual head proceeding
unhindered towards the end of the address space and with with 64 bit
vmas it is a long walk.
We cou
On Fri, Feb 19, 2016 at 07:25:57PM +0530, Deepak M wrote:
> Currently for executing the i2c MIPI sequence, we are
> relaying on the i2c bus bunmber which is specified in the
> VBT.
>
> Signed-off-by: Deepak M
> ---
> drivers/gpu/drm/i915/i915_dma.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
Cc: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/d
This patch reads the i2c bus number from the _CRS table of the display module
of the ACPI, which will be updated by the BIOS with the i2c info which is used
for this module.
> -Original Message-
> From: Deepak, M
> Sent: Friday, February 19, 2016 7:26 PM
> To: intel-gfx@lists.freedesktop
On ke, 2016-02-17 at 21:41 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The reason for spcial casing 20MHz in the iclkip calculations is that
> it would overflow the 7 bit divisor value. Let's rewrite the special
> case to check for just that, and bump up auxdiv when need
On Fri, 19 Feb 2016, Deepak M wrote:
> From: Gaurav K Singh
>
> New sequences are added in the mipi sequence block of the
> VBT from version 3 onwards. The sequences are added to
> make the code more generic as the panel related info
> are placed in the VBT.
>
> Cc: Jani Nikula
> Signed-off-by:
Currently for executing the i2c MIPI sequence, we are
relaying on the i2c bus bunmber which is specified in the
VBT.
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i915_dma.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/intel_acpi.c | 49 ++
Em Qua, 2016-02-17 às 21:41 +0200, ville.syrj...@linux.intel.com
escreveu:
> From: Ville Syrjälä
>
> The reason for spcial casing 20MHz in the iclkip calculations is that
> it would overflow the 7 bit divisor value. Let's rewrite the special
> case to check for just that, and bump up auxdiv when
On Fri, 19 Feb 2016, Deepak M wrote:
> Currently there are few pair of functions which
> are called during the panel enable/disable sequence.
> To improve the granularity, adding few more wrapper
> functions so that the functions are more specific
> on what they are doing.
I want to see where all
The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.
v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
v3 by Jani
- rebase on previous patches
- d
Chris Wilson writes:
> Rather than call a function to compute the matching cachelines and
> clflush them, just call the clflush *instruction* directly. We also know
> that we can use the unpatched plain clflush rather than the clflushopt
> alternative.
>
> Signed-off-by: Chris Wilson
> Cc: Mika
On Fri, 19 Feb 2016, "Deepak, M" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Friday, February 19, 2016 6:51 PM
>> To: Deepak, M ; intel-gfx@lists.freedesktop.org
>> Cc: Deepak, M
>> Subject: Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio
>> sequence supp
On Fri, 19 Feb 2016, Deepak M wrote:
> From: Uma Shankar
>
> Added the BXT GPIO pin configuration and programming logic for
> backlight and panel control.
>
> Cc: Jani Nikula
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 46
> ++
> -Original Message-
> From: Nikula, Jani
> Sent: Friday, February 19, 2016 6:51 PM
> To: Deepak, M ; intel-gfx@lists.freedesktop.org
> Cc: Deepak, M
> Subject: Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio
> sequence support and gpio table
>
> On Fri, 19 Feb 2016, D
On Fri, 19 Feb 2016, Deepak M wrote:
> From: Yogesh Mohan Marimuthu
>
> The GPIO configuration and register offsets are different from
> baytrail for cherrytrail. Port the gpio programming accordingly
> for cherrytrail in this patch.
>
> Cc: Jani Nikula
> Signed-off-by: Yogesh Mohan Marimuthu
>
On Fri, Feb 19, 2016 at 02:34:52PM +0200, Gabriel Feceoru wrote:
> On Cherryview PIPE_C can only be connected to PORT_D (bspec).
> The driver properly reports the crtc_mask for the encoder, however the
> mismatch between pipe and port is not reported back to the test.
>
> Add support for detecting
On Fri, 19 Feb 2016, Deepak M wrote:
> The generic gpio is sequence is parsed from the VBT and the
> GPIO table is updated with the North core, South core and
> SUS core elements.
>
> v2: Move changes in sideband.c file to new patch(Jani), rebase
> v3: Moved the Macro`s to intel_dsi_panel_vbt.c (J
On Fri, 19 Feb 2016, Mika Kahola wrote:
> On Fri, 2016-02-19 at 10:50 +0200, Jani Nikula wrote:
>> On Thu, 11 Feb 2016, Ramalingam C wrote:
>> > From: Deepak M
>> >
>> > The bpp value which is used while calulating the txbyteclkhs values
>> > should be wrt the pixel format value. Currently bpp i
Hi,
Now the code is in reviewable chunks, excellent!
I've added my comments below. A few repeats from last round, but now
with more questions about the logic itself.
On to, 2016-02-18 at 14:26 +, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Initial creation of scheduler sourc
On Fri, Feb 19, 2016 at 12:47:21PM +, Ben Duckworth wrote:
>
>
> On 28/01/2016 12:18, Chris Wilson wrote:
> >ringfill generates a few very common errors when submitting requests,
> >and historically these have been where we have had many implementation
> >bugs, repeated over and over again.
>
On Fri, 2016-02-19 at 10:50 +0200, Jani Nikula wrote:
> On Thu, 11 Feb 2016, Ramalingam C wrote:
> > From: Deepak M
> >
> > The bpp value which is used while calulating the txbyteclkhs values
> > should be wrt the pixel format value. Currently bpp is coming
> > from pipe config to calculate txbyt
On 28/01/2016 12:18, Chris Wilson wrote:
ringfill generates a few very common errors when submitting requests,
and historically these have been where we have had many implementation
bugs, repeated over and over again.
Signed-off-by: Chris Wilson
---
tests/gem_ringfill.c | 21 +--
On Fri, Feb 19, 2016 at 12:08:14PM +, Tvrtko Ursulin wrote:
>
> Hi,
>
> On 11/01/16 10:44, Chris Wilson wrote:
> >[ 196.988204] clocksource: timekeeping watchdog: Marking clocksource 'tsc'
> >as unstable because the skew is too large:
> >[ 196.988512] clocksource: 're
On 15/02/16 09:47, Daniel Vetter wrote:
On Thu, Feb 11, 2016 at 01:01:34PM +, Tvrtko Ursulin wrote:
On 29/01/16 16:49, Chris Wilson wrote:
As we add the VMA to the request early, it may be cancelled during
execbuf reservation. This will leave the context object pointing to a
I don't get
This could happen when the selected pipe cannot be used with the connected
port due do HW constrains.
bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86763
Signed-off-by: Gabriel Feceoru
---
tests/kms_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/kms
On Cherryview PIPE_C can only be connected to PORT_D (bspec).
The driver properly reports the crtc_mask for the encoder, however the
mismatch between pipe and port is not reported back to the test.
Add support for detecting this case so the test can be skipped.
Signed-off-by: Gabriel Feceoru
---
When no display is connected all kms_plane subtests pass although
no testing is done.
Change it by reporting the subtests as skipped.
Signed-off-by: Gabriel Feceoru
---
tests/kms_plane.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/tests/kms_plane.c b/test
On BSW all pipeA and pipeB kms_plane subtests fail.
The root cause is a HW limitation in Cherryview - PipeC is directly connected
to PortD.
Also, if no monitor is connected, all subtests pass although the test functions
are not called.
Fixed these issues by making these tests skipped.
bugzilla:
Hi,
On 11/01/16 10:44, Chris Wilson wrote:
[ 196.988204] clocksource: timekeeping watchdog: Marking clocksource 'tsc' as
unstable because the skew is too large:
[ 196.988512] clocksource: 'refined-jiffies' wd_now:
9b48 wd_last: 9acb mask:
[ 196.988559
On Tue, Feb 16, 2016 at 02:58:56PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > Rather than call a function to compute the matching cachelines and
> > clflush them, just call the clflush *instruction* directly. We also know
> > that we can use the unpatched plain clflush rather than t
From: Gaurav K Singh
New sequences are added in the mipi sequence block of the
VBT from version 3 onwards. The sequences are added to
make the code more generic as the panel related info
are placed in the VBT.
Cc: Jani Nikula
Signed-off-by: Gaurav K Singh
Signed-off-by: Shobhit Kumar
Signed-o
Currently there are few pair of functions which
are called during the panel enable/disable sequence.
To improve the granularity, adding few more wrapper
functions so that the functions are more specific
on what they are doing.
Cc: Jani Nikula
Signed-off-by: Deepak M
Signed-off-by: Gaurav K Singh
The generic gpio is sequence is parsed from the VBT and the
GPIO table is updated with the North core, South core and
SUS core elements.
v2: Move changes in sideband.c file to new patch(Jani), rebase
v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
v3 by Jani
- rebase on previous patches
- d
From: Uma Shankar
Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.
Cc: Jani Nikula
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 46 ++
1 file changed, 46 insertions(+)
diff --git a/drivers/g
From: Yogesh Mohan Marimuthu
The GPIO configuration and register offsets are different from
baytrail for cherrytrail. Port the gpio programming accordingly
for cherrytrail in this patch.
Cc: Jani Nikula
Signed-off-by: Yogesh Mohan Marimuthu
Signed-off-by: Deepak M
---
drivers/gpu/drm/i915/i9
On 18/02/16 18:31, yu@intel.com wrote:
From: Alex Dai
GuC client object is always pinned during its life cycle. We cache
the vmap of client object, which includes guc_process_desc, doorbell
and work queue. By doing so, we can simplify the code where driver
communicate with GuC.
As a resu
On 18/02/16 18:31, yu@intel.com wrote:
From: Alex Dai
There are several places inside driver where a GEM object is mapped to
kernel virtual space. The mapping is either done for the whole object
or certain page range of it.
This patch introduces a function i915_gem_object_vmap to do such
On 19/02/16 06:51, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface. This will cover objects backed by stolen memory as well
as oth
On 19/02/16 06:51, ankitprasad.r.sha...@intel.com wrote:
From: Ankitprasad Sharma
The BIOS RapidStartTechnology may corrupt the stolen memory across S3
suspend due to unalarmed hibernation, in which case we will not be able
to preserve the User data stored in the stolen region. Hence this pat
On Fri, 2016-02-19 at 12:26 +0200, Mika Kuoppala wrote:
> Cores need to be included into the debug mask. We don't exactly
> know what it does but the spec says it must be enabled. So obey.
>
> v2: Cores should be only set for BXT (Imre, Art)
>
> Cc: Imre Deak
> Cc: Runyan, Arthur J
> Signed-off
Add the ability to specify a substring of the subtest using --run-subtests.
This allows 'string' to be used as an abbreviation of the wildcard expression
'*string*' when defining which subtests should run.
Signed-off-by: Derek Morton
---
lib/igt_core.c | 5 +++--
1 file changed, 3 insertions(+)
Cores need to be included into the debug mask. We don't exactly
know what it does but the spec says it must be enabled. So obey.
v2: Cores should be only set for BXT (Imre, Art)
Cc: Imre Deak
Cc: Runyan, Arthur J
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
On 19/02/16 06:51, ankitprasad.r.sha...@intel.com wrote:
From: Chris Wilson
Introduced a new vm specfic callback insert_page() to program a single pte in
ggtt or ppgtt. This allows us to map a single page in to the mappable aperture
space. This can be iterated over to access the whole object
Hi,
Adding Daniel as CC to comment below.
On to, 2016-02-18 at 14:22 +, John Harrison wrote:
> On 20/01/2016 13:18, Joonas Lahtinen wrote:
> > On Mon, 2016-01-11 at 18:42 +, john.c.harri...@intel.com wrote:
> > > From: John Harrison
> > >
> > >
> > > + this = node->s
From: Mayuresh Gharpure
Co-Author : Marius Vlad
Co-Author : Pratik Vishwakarma
So far we have had only two commit styles, COMMIT_LEGACY
and COMMIT_UNIVERSAL. This patch adds another commit style
COMMIT_ATOMIC which makes use of drmModeAtomicCommit()
v2: (Marius)
i)Set CRTC_ID to zero
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