On Monday 15 February 2016 18:07:47 Daniel Vetter wrote:
> On Mon, Feb 08, 2016 at 05:08:03PM +0200, Jani Nikula wrote:
> > On Mon, 08 Feb 2016, Imre Deak wrote:
> > >> > Thanks for the patch, I pushed it to -dinq.
> > >>
> > >> The rule is, we should wait for the CI results before pushing.
> > >
== Summary ==
Series 3296v1 drm/i915: Hide GEM shutdown in i915_gem_fini
2016-02-11T15:39:33.521840
http://patchwork.freedesktop.org/api/1.0/series/3296/revisions/1/mbox/
Applying: drm/i915: Hide GEM shutdown in i915_gem_fini
Repository lacks necessary blobs to fall back on 3-way merge.
Cannot fa
From: Sourab Gupta
This patch introduces flags and adds support for having pid output with
the OA reports generated through the RCS commands.
When the stream is opened with pid sample type, the pid information is also
captured through the command stream samples and forwarded along with the
OA re
From: Sourab Gupta
This patch exposes a new sample source field to userspace. This field can
be populated to specify the origin of the OA report.
For e.g. for internally triggerred reports (non MI_RPC reports), the RPT_ID
field has bitfields for specifying the origin such as timer, or render ctx
From: Sourab Gupta
This patch extends the i915 perf framework to handle the perf sample
collection for any given gpu engine. Particularly, the support
for collecting timestamp sample type is added, which can be requested for
any engine.
The thing to note is that, still only a single stream insta
From: Sourab Gupta
This patch introduces a framework to enable OA counter reports associated
with Render command stream. We can then associate the reports captured
through this mechanism with their corresponding context id's. This can be
further extended to associate any other metadata informatio
From: Sourab Gupta
This patch enables userspace to specify tags (per workload), provided via
execbuffer ioctl, which could be added to OA reports, to help associate
reports with the corresponding workloads.
There may be multiple stages within a single context, from a userspace
perspective. An ab
From: Sourab Gupta
This patch adds support for capturing MMIO register values through
i915 perf interface.
The userspace can request upto 8 MMIO register values to be dumped.
The addresses of these registers can be passed through the corresponding
property 'value' field while opening the stream.
From: Sourab Gupta
This patch adds support for opening multiple concurrent perf streams for
different gpu engines, while having the restriction to open only a single
stream open for a particular gpu engine.
This enables userspace client to open multiple streams, one per engine,
at any time to cap
From: Sourab Gupta
This patch adds a new ctx getparam ioctl parameter, which can be used to
retrieve ctx global_id for any particular ctx by userspace.
This can be used by userspace to map the i915 perf samples with their
particular ctx's, since those would be having ctx global_id's.
Otherwise t
From: Sourab Gupta
The current context user handles are specific to drm file instance.
There are some usecases, which may require a global id for the contexts.
For e.g. a system level GPU profiler tool may lean upon the global context
ids to associate the performance snapshots with individual con
From: Robert Bragg
The newly added intel_context::global_id is suitable (a globally unique
20 bit ID) for giving to the hardware as a unique context identifier.
Compared to using the pinned address of a logical ring context these IDs
are constant for the lifetime of a context whereas a context c
From: Sourab Gupta
This series adds framework for collection of gpu performance metrics
associated with the command stream of a particular engine. These metrics
include OA reports, timestamps, mmio metrics, etc. These metrics are
are collected around batchbuffer boundaries.
This work utilizes th
From: Robert Bragg
This will allow the ID to be given to the HW as the unique context
identifier that's written, for example, to the context status buffer
on preemption and included in reports written by the OA unit.
Cc: Sourab Gupta
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/i915_g
Hi:
Thanks Kevin! See my comments below.
On 02/16/16 11:11, Tian, Kevin wrote:
From: Wang, Zhi A
Sent: Tuesday, February 16, 2016 12:04 AM
The better design idea is to reuse the data structures and helper
functions, but have new top-level entry functions for creating e.g. a
xengt lrc contex
> From: Wang, Zhi A
> Sent: Tuesday, February 16, 2016 12:04 AM
>
> The better design idea is to reuse the data structures and helper
> functions, but have new top-level entry functions for creating e.g. a
> xengt lrc context. So e.g. have a lrc init function for xengt which
> takes the setup stuf
On Mon, Feb 15, 2016 at 11:07:23PM +0100, Daniel Vetter wrote:
> On Mon, Feb 15, 2016 at 02:11:24PM +0800, Zhi Wang wrote:
> > From SKL, i915 will try to load DMC firmware when system is starting up. You
> > can find it from 01.org. Personally, it looks without the firmware, the
> > system is also
On 2/15/2016 6:46 PM, Ville Syrjälä wrote:
On Fri, Feb 12, 2016 at 06:06:10PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level a
On 2/12/2016 7:38 PM, Ville Syrjälä wrote:
On Fri, Feb 12, 2016 at 06:39:44PM +0530, Shubhangi Shrivastava wrote:
This patch sets the invert bit for hpd detection for each port
based on VBT configuration. Since each AOB can be designed to
depend on invert bit or not, it is expected if an AOB r
On 2/12/2016 8:36 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Bspec tells us that we can allow cdclk up to 540Mhz on BDW ULX, or
up to 675 MHz on ULT, bu only if extra cooling is provided. There
don't seem to be any strap or VBT bits to tells us this however.
But I did spot
Pretty clear. Thanks for the ideas! They really inspire me. :)
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Tuesday, February 16, 2016 1:20 AM
To: Wang, Zhi A
Cc: Vetter, Daniel; Joonas Lahtinen; Chris Wilson; Lv, Zhiyuan; Tian, Ke
* Ville Syrjälä
> Could you test the following hack while using a 1920x1080 mode with
> 148.5 MHz dotclock, and see if there's any improvement?
I think it might be an improvement, that is, the blanking/flickers
seems to occur less often than it did with 8ed1804, but it is not
completely fixed. I'
On Mon, Feb 15, 2016 at 02:11:24PM +0800, Zhi Wang wrote:
> From SKL, i915 will try to load DMC firmware when system is starting up. You
> can find it from 01.org. Personally, it looks without the firmware, the
> system is also able to work, except a lot warnings. :)
We pretty much require dmc, si
From: Ville Syrjälä
With NV12 we have two color planes to deal with so we must compute the
surface and x/y offsets for the second plane as well.
What makes this a bit nasty is that the hardware expects the surface
offset to be specified as a distance from the main surface offset.
What's worse, t
From: Ville Syrjälä
To make life less surprising we can make intel_adjust_tile_offset()
deal with linear buffers as well. Currently it doesn't seem like there's
a real need for this since only X tiling and NV12 (which would always
be tiled currently) should need it. But I've used it for some debu
From: Ville Syrjälä
Minimize the resulting X coordinate after intel_adjust_tile_offset() is
done with it's offset adjustment. This allows calling
intel_adjust_tile_offset() multiple times in case we need to adjust
the offset several times.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/
From: Ville Syrjälä
Currently we requite the object to be X tiled if the fb is X
tiled. The argument is supposedly FBC GTT tracking. But
actually that no longer holds water since FBC supports
Y tiling as well on SKL+.
A better rule IMO is to require that if there is a fence, the
fb modifier matc
From: Ville Syrjälä
We convert the fb->offsets[] into x/y offsets, so they must be
(macro)pixel aligned. Check for this, and if things look good
allow fb->offsets[] != 0 when creating fbs since we now handle
them correctly.
v2: Move to last place in the series and improve the commit message
Sig
From: Ville Syrjälä
intel_compute_tile_offset() and intel_add_fb_offsets() get passed the fb
and the rotation. As both of those come from the plane state we can just
pass that in instead.
For extra consitency pass the plane state to intel_fb_xy_to_linear() as
well even though it only really need
From: Ville Syrjälä
SKL has nasty limitations with the display surface offsets:
* source x offset + width must be less than the stride for X tiled
surfaces or the display engine falls over
* the surface offset requires lots of alignment (256K or 1M)
These facts mean that we can't just pick any
From: Ville Syrjälä
If there's a fence on the object it will be aligned to the start
of the object, and hence CPU rendering to any fb that straddles
the fence edge will come out wrong due to lines wrapping at the
wrong place.
We have no API to manage fences on a sub-object level, so we can't
rea
From: Ville Syrjälä
rotate_pages() checks to see if it got called with a NULL sg, and then
goes to extract it from sg->sgl. It always gets called with a NULL sg
for the first plane, so moving the initial 'sg=st->sgl' assignment out
into intel_rotate_fb_obj_pages() seems less special-casey.
Signe
From: Ville Syrjälä
Instead of repopulatin the rotation_info struct for the fb every time
we try to use the fb, we can just populate it once when creating the fb,
and later we can just copy the pre-populate struct into the gtt_view.
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
From: Ville Syrjälä
intel_compute_page_offsets() gets passed a bunch of the framebuffer
metadate sepearately. Just pass the framebuffer itself to make life
simpler for the caller, and make it less likely they would make a
mistake in the order of the arguments (as most as just unsigned ints and
su
From: Ville Syrjälä
Soon the fence tiling mode may not always match the fb modifier
even for X tiled buffers. So let's use the fb modifier
consistently for all display tiling decisions.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 33 ++---
From: Ville Syrjälä
intel_pin_and_fence_fb_obj() only needs the framebuffer, and the desird
rotation (to find the right GTT view for it), so no need to pass all
kinds of plane stuff.
The main motivation is to get rid of the uggy NULL plane_state handling
due to fbdev.
v2: Add a note why I reall
From: Ville Syrjälä
We repeat the SKL stride register value calculations a several places.
Move it into a small helper function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 52 +---
drivers/gpu/drm/i915/intel_drv.h | 2 ++
driver
From: Ville Syrjälä
intel_compute_page_offset() can dig up the correct pitch from the fb
itself, no need for the caller to pass it in.
A bit of extra care is needed for the lower level
_intel_compute_page_offset() since that one gets called before the
rotated pitch under intel_fb is populated. N
From: Ville Syrjälä
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling reasier for the plane code
To achieve these goals we reduce intel_rotation_info to only contain
(for each plane) the rotated view width,
From: Ville Syrjälä
Another iteration of the fb offset stuff. Unfortunately this seems
to be one of those things that just keeps on growing when you're
not looking. But I'm hoping we're starting to approach the limit.
Changes from the last time [1]:
* split the chrome plane vma size fix from one
From: Ville Syrjälä
SKL+ needs >4K alignment for tiled surfaces, so make
intel_compute_page_offset() handle it.
The way we do it is first we compute the closest tile boundary
as before, and then figure out how many tiles we need to go
to reach the desired alignment. The difference in the offset
From: Ville Syrjälä
Make if clear whether we're talking tile widths in bytes or in pixels.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dis
From: Ville Syrjälä
The page aligned surface address calculation needs to know which way
things are rotated. The contract now says that the caller must pass the
rotate x/y coordinates, as well as the tile_height aligned stride in
the tile_height direction. This will make it fairly simple to deal
From: Ville Syrjälä
Throw out a bunch of unnecessary stuff from struct intel_rotation_info,
and pull most of the remaining stuff to live under an array of
per-color plane sub-structures.
What still remains outside the sub-structure will be reorgranized later
as well, but that requires more work
From: Ville Syrjälä
The size of the rotated ggtt mapping ought to include the size of the
chroma plane as well. Not a huge deal since we don't expose NV12 (or any
pother planar format for that matter) yet.
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Fixes: 9e759ff1f4a0 ("drm/i915: Return correct si
On Mon, Feb 15, 2016 at 08:17:23PM +0100, Tore Anderson wrote:
> Hello,
>
> Since upgrading to the Fedora 4.3 kernel package, the picture on my the
> BenQ M2700 HD monitor I've got connected to my HP EliteBook Folio 9470m
> laptop began having issues. The monitor is connected with a DP+-to-HDMI
>
Hello,
Since upgrading to the Fedora 4.3 kernel package, the picture on my the
BenQ M2700 HD monitor I've got connected to my HP EliteBook Folio 9470m
laptop began having issues. The monitor is connected with a DP+-to-HDMI
cable (HDMI in the monitor end), and the resolution I'm using is
1920x1080.
On 15/02/16 16:55, Daniel Vetter wrote:
On Thu, Feb 04, 2016 at 12:06:57PM +, Derek Morton wrote:
Added extended wildcard support when specifying --run-subtest.
Wildcard format is as specified in rfc3977 and the uwildmat() implementation
is taken from libinn.
See https://tools.ietf.org/html
On 10/02/16 17:39, Ben Widawsky wrote:
On Wed, Feb 10, 2016 at 04:23:08PM +, Chris Wilson wrote:
On Wed, Feb 10, 2016 at 07:42:23AM -0800, Ben Widawsky wrote:
Do you guys get the CI mails? This version has regressions. v1 did not. I don't
know what to trust.
I didn't even see v2 itself!
On Wed, Feb 10, 2016 at 09:39:33AM -0800, Ben Widawsky wrote:
> On Wed, Feb 10, 2016 at 04:23:08PM +, Chris Wilson wrote:
> > On Wed, Feb 10, 2016 at 07:42:23AM -0800, Ben Widawsky wrote:
> > > Do you guys get the CI mails? This version has regressions. v1 did not. I
> > > don't
> > > know wha
On Wed, Feb 10, 2016 at 07:14:36AM -, Patchwork wrote:
> == Summary ==
>
> Series 3145v2 drm/i915: Check for get_pages instead of shmem (filp)
> http://patchwork.freedesktop.org/api/1.0/series/3145/revisions/2/mbox/
>
> Test pm_rpm:
> Subgroup basic-pci-d3-state:
> fai
On Mon, Feb 15, 2016 at 04:03:49PM +, Wang, Zhi A wrote:
> Hi Daniel:
> Thanks for shedding the light! See my comments below. :)
>
> -Original Message-
> From: Vetter, Daniel
> Sent: Monday, February 15, 2016 5:32 PM
> To: Wang, Zhi A; Joonas Lahtinen; Chris Wilson; Lv, Zhiyuan;
On Mon, Feb 15, 2016 at 03:17:55PM +0100, Peter Zijlstra wrote:
> On Mon, Feb 15, 2016 at 02:36:43PM +0200, Joonas Lahtinen wrote:
> > Instead of implementing a custom locked reference counting, use lockref.
> >
> > Current implementation leads to a deadlock splat on Intel SKL platforms
> > when l
On Mon, Feb 15, 2016 at 06:52:52PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 15, 2016 at 03:21:54PM -, Patchwork wrote:
> > == Summary ==
> >
> > Series 3292v1 drm/i915: Add missing 'else' to intel_digital_port_connected()
> > http://patchwork.freedesktop.org/api/1.0/series/3292/revisions/1/mb
On Fri, Feb 12, 2016 at 08:26:27AM +0200, Jani Nikula wrote:
> On Thu, 11 Feb 2016, Daniel Vetter wrote:
> > On Wed, Feb 10, 2016 at 07:59:05PM +0200, ville.syrj...@linux.intel.com
> > wrote:
> >> From: Ville Syrjälä
> >>
> >> Looks like g4x hpd live status bits actually agree with the spec. At
Originally submitted inline with <20160205145831.ga14...@wunner.de>,
hereby resubmitted standalone for CI as requested by Daniel with
<20160215163251.GR11240@phenom.ffwll.local>.
Above-mentioned message contained the following important note:
> However AFAICT a corner case remains where we're sti
The ->lastclose callback invokes intel_fbdev_restore_mode() and has
been witnessed to run before intel_fbdev_initial_config_async()
has finished.
We might likewise receive hotplug events or be suspended before
we've had a chance to fully set up the fbdev.
Fix by waiting for the asynchronous threa
On Mon, Feb 08, 2016 at 05:08:03PM +0200, Jani Nikula wrote:
> On Mon, 08 Feb 2016, Imre Deak wrote:
> >> > Thanks for the patch, I pushed it to -dinq.
> >>
> >> The rule is, we should wait for the CI results before pushing.
> >
> > Yes, I forgot to wait for the result for this version of the pat
On Mon, Feb 15, 2016 at 03:17:55PM +0100, Peter Zijlstra wrote:
> On Mon, Feb 15, 2016 at 02:36:43PM +0200, Joonas Lahtinen wrote:
> > Instead of implementing a custom locked reference counting, use lockref.
> >
> > Current implementation leads to a deadlock splat on Intel SKL platforms
> > when l
On Fri, Feb 05, 2016 at 04:45:59PM +, Chris Wilson wrote:
> Unknown parameters, especially structure padding, are expected to invoke
> rejection with -EINVAL.
>
> v2: similar issue exists for context-create
>
> Testcase: igt/gem_ctx_create/invalid-pad
> Testcase: igt/gem_ctx_bad_destroy/inval
On Thu, Feb 04, 2016 at 04:25:41PM +0200, Marius Vlad wrote:
> suspend-read-crc-pipe will perform a suspend and then skip the test in case
> the
> pipe is not present on the platform. Skip the test before doing the suspend.
>
>
> Signed-off-by: Marius Vlad
> ---
> tests/kms_pipe_crc_basic.c |
On Thu, Feb 04, 2016 at 12:06:57PM +, Derek Morton wrote:
> Added extended wildcard support when specifying --run-subtest.
>
> Wildcard format is as specified in rfc3977 and the uwildmat() implementation
> is taken from libinn.
> See https://tools.ietf.org/html/rfc3977#section-4 for a descript
On Mon, Feb 15, 2016 at 03:21:54PM -, Patchwork wrote:
> == Summary ==
>
> Series 3292v1 drm/i915: Add missing 'else' to intel_digital_port_connected()
> http://patchwork.freedesktop.org/api/1.0/series/3292/revisions/1/mbox/
>
> Test gem_mmap_gtt:
> Subgroup basic-small-copy-xy:
>
On Thu, Feb 04, 2016 at 06:36:22PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2016 at 06:21:23PM +0200, Jani Nikula wrote:
> > On Thu, 04 Feb 2016, Ville Syrjälä wrote:
> > > On Thu, Feb 04, 2016 at 12:50:51PM +0200, Jani Nikula wrote:
> > >> From: vkorjani
> > >>
> > >> New sequence element
On Fri, Feb 05, 2016 at 06:51:53AM +0530, Thulasimani, Sivakumar wrote:
> not sure how this can be pushed separately even if approved at present.
> why not push this as part of new patch set of the RC patches ?
Yes, please don't send around patches which need depencies. Instead squash
them into th
On Thu, Feb 04, 2016 at 10:41:33AM +0200, Jani Nikula wrote:
> On Thu, 04 Feb 2016, Matt Roper wrote:
> > On Thu, Feb 04, 2016 at 07:17:08AM +0530, Thulasimani, Sivakumar wrote:
> >>
> >>
> >> On 2/4/2016 6:19 AM, Matt Roper wrote:
> >> >From: Bob Paauwe
> >> >
> >> >Broxton has some additional
On Fri, Feb 05, 2016 at 03:58:31PM +0100, Lukas Wunner wrote:
> Hi Chris,
>
> On Fri, Feb 05, 2016 at 11:09:27AM +, Chris Wilson wrote:
> > On Fri, Feb 05, 2016 at 01:27:10AM +0100, Lukas Wunner wrote:
> > > On Thu, Feb 04, 2016 at 09:21:17AM +, Li, Weinan Z wrote:
> > > > We still need th
On Wed, Feb 03, 2016 at 11:44:03AM +0200, Jani Nikula wrote:
> On Tue, 02 Feb 2016, Ramalingam C wrote:
> > From: Uma Shankar
> >
> > During Charging OS mode, mipi display was blanking.This is
> > because during driver load, though encoder, connector were
> > active but crtc returned inactive. Th
On Tue, Feb 02, 2016 at 11:24:16PM +0530, Ramalingam C wrote:
> From: Uma Shankar
>
> During Charging OS mode, mipi display was blanking.This is
> because during driver load, though encoder, connector were
> active but crtc returned inactive. This caused sanitize
> function to disable the DSI pan
On Wed, Feb 03, 2016 at 02:59:11PM +0200, Mika Kahola wrote:
> On Wed, 2016-02-03 at 11:28 +0200, Jani Nikula wrote:
> > On Tue, 02 Feb 2016, Ramalingam C wrote:
> > > We need to enable DSI PLL before configuring the DSI registers.
> > >
> > > Signed-off-by: Ramalingam C
> > > ---
> > > drivers/
On Thu, Feb 11, 2016 at 10:13:30AM +, Chris Wilson wrote:
> On Tue, Feb 02, 2016 at 02:46:19PM +, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > VMA creation and GEM list management need the big lock.
> >
> > v2:
> >
> > Mutex unlock ended on the wrong path somehow. (0-day, Juli
On 15/02/16 14:53, Patchwork wrote:
== Summary ==
Series 3277v1 Assorted reviewed patches for CI run
http://patchwork.freedesktop.org/api/1.0/series/3277/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (skl-i5k-2)
Hi Daniel:
Thanks for shedding the light! See my comments below. :)
-Original Message-
From: Vetter, Daniel
Sent: Monday, February 15, 2016 5:32 PM
To: Wang, Zhi A; Joonas Lahtinen; Chris Wilson; Lv, Zhiyuan; Tian, Kevin
Subject: Re: Discuss GVT context hacks in i915
Am 15/02/2016
On 15/02/16 15:47, Dave Gordon wrote:
On 15/02/16 13:40, Martin Peres wrote:
On 15/02/16 14:24, Dave Gordon wrote:
On 12/02/16 16:31, Martin Peres wrote:
This is not a big issue to return -1 since the only codepath that uses
it is for display purposes.
Caught by Klockwork.
Signed-off-by: Mar
On Mon, Feb 15, 2016 at 04:42:35PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 15, 2016 at 10:55:33AM +0200, Oleksandr Natalenko wrote:
> > 13.02.2016 01:23, Ville Syrjälä wrote:
> > > - Do you have another monitor to try?
> > > - Do you have another cable to try?
> >
> > More on this.
> >
> > Comp
On 12/02/16 13:03, Tvrtko Ursulin wrote:
On 11/02/16 23:09, yu@intel.com wrote:
From: Alex Dai
GuC client object is always pinned during its life cycle. We cache
the kmap of its first page, which includes guc_process_desc and
doorbell. By doing so, we can simplify the code where we read f
== Summary ==
Series 3292v1 drm/i915: Add missing 'else' to intel_digital_port_connected()
http://patchwork.freedesktop.org/api/1.0/series/3292/revisions/1/mbox/
Test gem_mmap_gtt:
Subgroup basic-small-copy-xy:
pass -> DMESG-FAIL (ilk-hp8440p)
Test kms_pipe_crc_basic
== Summary ==
Series 3278v1 drm/i915/guc: Keep the previous context pinned until the next one
has been completed
http://patchwork.freedesktop.org/api/1.0/series/3278/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> INCOMPLETE (hsw
On 10/02/16 20:31, Yu Dai wrote:
On 02/10/2016 09:30 AM, Tvrtko Ursulin wrote:
Hi,
On 10/02/16 00:05, yu@intel.com wrote:
> From: Alex Dai
>
> The cached work queue header pointer is set to last byte of work
> queue buffer. It will make sure the whole work queue buffer is
> available aft
== Summary ==
Series 3277v1 Assorted reviewed patches for CI run
http://patchwork.freedesktop.org/api/1.0/series/3277/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (skl-i5k-2)
Subgroup suspend-read-crc-pipe-b:
On Mon, Feb 15, 2016 at 10:55:33AM +0200, Oleksandr Natalenko wrote:
> 13.02.2016 01:23, Ville Syrjälä wrote:
> > - Do you have another monitor to try?
> > - Do you have another cable to try?
>
> More on this.
>
> Computer DVI —— old DVI-HDMI cable —— old monitor HDMI == not working
> Computer DV
On 12/02/16 13:03, Tvrtko Ursulin wrote:
On 11/02/16 23:09, yu@intel.com wrote:
From: Alex Dai
GuC client object is always pinned during its life cycle. We cache
the kmap of its first page, which includes guc_process_desc and
doorbell. By doing so, we can simplify the code where we read f
== Summary ==
Series 3276v1 drm/i915/gen9: Check for DC state mismatch
http://patchwork.freedesktop.org/api/1.0/series/3276/revisions/1/mbox/
Test drv_module_reload_basic:
pass -> DMESG-WARN (ilk-hp8440p)
Test gem_mmap_gtt:
Subgroup basic-small-copy:
Op 12-02-16 om 14:56 schreef Zanoni, Paulo R:
> Em Qua, 2016-02-10 às 13:49 +0100, Maarten Lankhorst escreveu:
>> Factor out intel_fbc_supports_rotation
> ^ not anymore
>
>
>> and use it in
>> pre_plane_update as well. This leaves intel_crtc->atomic
>> empty, so remove it too.
>>
>> Changes since
Hi Maarten,
[auto build test WARNING on drm/drm-next]
[also build test WARNING on v4.5-rc4 next-20160215]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Maarten-Lankhorst/drm-atomic-Allow-for
== Summary ==
Series 3265v1 CRTC background color support for i915
http://patchwork.freedesktop.org/api/1.0/series/3265/revisions/1/mbox/
Test gem_sync:
Subgroup basic-default:
pass -> DMESG-FAIL (hsw-brixbox)
Test kms_pipe_crc_basic:
Subgroup suspend-read-cr
We have many places in the code where we check if a given display power
domain is enabled and if so access registers backed by this power
domain. We assumed that some modeset lock will prevent the power
reference from vanishing in the middle of the HW access, but this
assumption doesn't always hold
On Mon, Feb 15, 2016 at 02:36:43PM +0200, Joonas Lahtinen wrote:
> Instead of implementing a custom locked reference counting, use lockref.
>
> Current implementation leads to a deadlock splat on Intel SKL platforms
> when lockdep debugging is enabled.
>
> This is due to few of CPUfreq drivers (i
On 15/02/16 13:43, David Weinehall wrote:
On Mon, Feb 15, 2016 at 12:24:04PM +, Dave Gordon wrote:
On 12/02/16 16:31, Martin Peres wrote:
This is not a big issue to return -1 since the only codepath that uses
it is for display purposes.
Caught by Klockwork.
Signed-off-by: Martin Peres
--
== Summary ==
Series 3243v1 drm/i915: Fix hpd live status bits for g4x
http://patchwork.freedesktop.org/api/1.0/series/3243/revisions/1/mbox/
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE
Test kms_pipe_crc_basic:
Subgro
Imre Deak writes:
> The assumption when adding the intel_display_power_is_enabled() checks
> was that if it returns success the power can't be turned off afterwards
> during the HW access, which is guaranteed by modeset locks. This isn't
> always true, so make sure we hold a dedicated reference f
== Summary ==
Series 2906v2 Capture more useful details in error state
http://patchwork.freedesktop.org/api/1.0/series/2906/revisions/2/mbox/
Test gem_sync:
Subgroup basic-bsd:
pass -> DMESG-FAIL (hsw-brixbox)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
On 15/02/16 13:40, Martin Peres wrote:
On 15/02/16 14:24, Dave Gordon wrote:
On 12/02/16 16:31, Martin Peres wrote:
This is not a big issue to return -1 since the only codepath that uses
it is for display purposes.
Caught by Klockwork.
Signed-off-by: Martin Peres
---
src/intel_device.c | 5
On Mon, Feb 15, 2016 at 12:24:04PM +, Dave Gordon wrote:
> On 12/02/16 16:31, Martin Peres wrote:
> >This is not a big issue to return -1 since the only codepath that uses
> >it is for display purposes.
> >
> >Caught by Klockwork.
> >
> >Signed-off-by: Martin Peres
> >---
> > src/intel_device
On 11/02/16 13:36, Chris Wilson wrote:
On Sat, Jan 30, 2016 at 11:17:07AM +, Chris Wilson wrote:
On Fri, Jan 29, 2016 at 07:19:31PM +, Dave Gordon wrote:
From: Nick Hoath
Swap the order of context & engine cleanup, so that contexts are cleaned
up first, and *then* engines. This is a m
On Mon, 15 Feb 2016 14:20:46 +0100,
Gabriel Feceoru wrote:
>
>
>
> On 15.02.2016 14:57, Takashi Iwai wrote:
> > On Mon, 15 Feb 2016 13:57:00 +0100,
> > Gabriel Feceoru wrote:
> >>
> >>
> >>
> >> On 15.02.2016 12:23, Takashi Iwai wrote:
> >>> On Fri, 12 Feb 2016 17:47:21 +0100,
> >>> Gabriel Fece
On 15/02/16 14:24, Dave Gordon wrote:
On 12/02/16 16:31, Martin Peres wrote:
This is not a big issue to return -1 since the only codepath that uses
it is for display purposes.
Caught by Klockwork.
Signed-off-by: Martin Peres
---
src/intel_device.c | 5 -
1 file changed, 4 insertions(+)
== Summary ==
Series 77v8 Kill off intel_crtc->atomic!
http://patchwork.freedesktop.org/api/1.0/series/77/revisions/8/mbox/
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass -> DMESG-WARN (skl-i5k-2)
pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE
On Mon, Feb 15, 2016 at 06:55:07AM +, R, Durgadoss wrote:
> Hi Ville,
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, February 12, 2016 10:43 PM
> >To: R, Durgadoss
> >Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, An
Imre Deak writes:
> The assumption when adding the intel_display_power_is_enabled() checks
> was that if it returns success the power can't be turned off afterwards
> during the HW access, which is guaranteed by modeset locks. This isn't
> always true, so make sure we hold a dedicated reference f
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