Re: [Intel-gfx] [PATCH 4.1, 4.2] drm/i915: Silence DDR DVFS errors on CHV

2015-10-17 Thread Greg KH
On Mon, Sep 28, 2015 at 10:09:11PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > commit 58590c14d80defc94e900308a9d8fa55284de6f2 upstream. This is not the commit id of the patch below at all, I can't take this, please be more careful in the future. thanks, greg k-h >

Re: [Intel-gfx] [PATCH] drm: Explicitly compute the last cacheline for clflush on range

2015-10-17 Thread Imre Deak
On Fri, 2015-10-16 at 20:55 +0100, Chris Wilson wrote: > Fixes regression from > > commit afcd950cafea6e27b739fe7772cbbeed37d05b8b > Author: Chris Wilson > Date: Wed Jun 10 15:58:01 2015 +0100 > > drm: Avoid the double clflush on the last cache line in > drm_clflush_virt_range() > > I'm