[Intel-gfx] [RFC PATCH] drm/i915: PSR regressions on Broadwell

When using PSR, I see the screen freeze after only a few frames (sometimes a split second; sometimes it seems like practically the first frame). Bisecting led me to commit 3301d4092106 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic") in v4.2. This patch is the simplest fix that gets it working

Re: [Intel-gfx] [4/7] drm/i915: PSR: Mask LPSP hw tracking back again.

On Thu, Aug 20, 2015 at 05:55:41PM -0700, Rodrigo Vivi wrote: > At the beginning it was masked to allow PSR at all. > Than it got removed later by my > commit 09108b90f040 ("drm/i915: PSR: Remove Low Power HW tracking mask.") > in order to trying fixing one case reported at intel-gfx mailing list >

Re: [Intel-gfx] [1/7] drm/i915: Remove duplicated dpcd write on hsw_psr_enable_sink.

On Thu, Aug 20, 2015 at 05:55:38PM -0700, Rodrigo Vivi wrote: > This is wrong since my commit (89251b17). The intention of that > commit was to remove this one here that is also wrong anyway, > but it was forgotten. > > Signed-off-by: Rodrigo Vivi Tested-by: Brian Norris (caveat below) I was

Re: [Intel-gfx] [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

On 25/09/2015 19:34, Ville Syrjälä wrote: On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote: Dropping it as it is for pre-production stepping. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_lrc.c| 5 ++--- drivers/gpu/drm/i915/intel_ringbuffer.c | 23 ++

[Intel-gfx] [PATCH] drm/i915/guc: Fix a bug in GuC status check

From: Alex Dai Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE status is a reliable readiness flag only when resuming from RC6. This fix a racing issue that allocation of doorbell fails whilst GuC init is not finished. v2: Split the status check into two parts for better reading

[Intel-gfx] [PATCH] drm/i915/guc: Add host2guc notification for suspend and resume

From: Alex Dai Add host2guc interfaces to nofigy GuC power state changes when enter or resume from power saving state. v2: Add GuC suspend/resume to runtime suspend/resume too v1: Change to a more flexible way when fill host to GuC scratch data in order to remove hard coding. Signed-off-by: Al

[Intel-gfx] [PATCH] drm/i915/guc: Media domain bit needed when notify GuC rc6 state

From: Alex Dai GuC expects two bits for Render and Media domain separately when driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for Render and bit 1 is for Media domain. v2: Keep sync with code for WaRsDoubleRc6WrlWithCoarsePowerGating v1: Add parameters definition to avoid magic valu

[Intel-gfx] [PATCH] drm/i915/guc: Add GuC css header parser

From: Alex Dai The size / offset information of all firmware ingredients are now caculated from header. Driver will validate the header and rsa key size. If any component is out of boundary, driver will reject the loading too. v3: 1) Move DOC to intel_guc_fwif.h right before css_header definitio

Re: [Intel-gfx] [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

On Fri, Sep 25, 2015 at 09:34:13PM +0300, Ville Syrjälä wrote: > On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote: > > Dropping it as it is for pre-production stepping. > > > > Signed-off-by: Arun Siluvery > > --- > > drivers/gpu/drm/i915/intel_lrc.c| 5 ++--- > > drivers/g

Re: [Intel-gfx] [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote: > Dropping it as it is for pre-production stepping. > > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/intel_lrc.c| 5 ++--- > drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++ > 2 files change

Re: [Intel-gfx] [PATCH 01/12] drm/i915/gen9: Handle error returned by gen9_init_workarounds

On Fri, Sep 25, 2015 at 02:33:35PM +0100, Arun Siluvery wrote: > Signed-off-by: Arun Siluvery Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 10 -- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c

Re: [Intel-gfx] [PATCH 03/12] drm/i915/gen9: Merge two WA as they part of same register

On Fri, Sep 25, 2015 at 02:33:37PM +0100, Arun Siluvery wrote: > Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save > an entry in WA array. > > Signed-off-by: Arun Siluvery Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++--- > 1 file ch

Re: [Intel-gfx] [PATCH 10/12] drm/i915/skl: Remove WaDisableVFUnitClockGating

On Fri, Sep 25, 2015 at 02:33:44PM +0100, Arun Siluvery wrote: > Dropping it because it is for pre-production stepping, also removed > bit definition in i915_reg.h as it is not used anywhere else. > > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/i915_reg.h | 1 - > drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH 09/12] drm/i915/skl: Remove WaSetGAPSunitClckGateDisable

On Fri, Sep 25, 2015 at 02:33:43PM +0100, Arun Siluvery wrote: > Dropping it because it is for pre-production stepping, also removed > bit definition in i915_reg as it is not used anywhere else. > > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/i915_reg.h | 1 - > drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH 08/12] drm/i915/skl: Remove WaDisableSDEUnitClockGating

On Fri, Sep 25, 2015 at 02:33:42PM +0100, Arun Siluvery wrote: > Dropping it because it is for pre-production stepping. > > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/intel_pm.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/inte

Re: [Intel-gfx] [PATCH 06/12] drm/i915/bxt: Add WaStoreMultiplePTEenable name

On Fri, Sep 25, 2015 at 02:33:40PM +0100, Arun Siluvery wrote: > Updated WA with the name. > > Signed-off-by: Arun Siluvery Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_pm.c | 9 +++-- > 1 file changed, 3 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH] drm/i915: Consider HW CSB write pointer before resetting the sw read pointer

On 9/25/2015 4:44 PM, Mika Kuoppala wrote: Michel Thierry writes: - ring->next_context_status_buffer = 0; + + /* +* Instead of resetting the Context Status Buffer (CSB) read pointer to +* zero, we need to read the write pointer from hardware and use its +* va

Re: [Intel-gfx] [PATCH 05/12] drm/i915/bxt: update WaSetHDCunitClckGatingDisable

On Fri, Sep 25, 2015 at 02:33:39PM +0100, Arun Siluvery wrote: > The implementation for this WA is same as > WaSetHdcUnitClockGatingDisableInUcgctl6. > Both of them are for BXT:A0 except that > WaSetHdcUnitClockGatingDisableInUcgctl6 > is applicable only when either SS0 or SS2 is active but if we

Re: [Intel-gfx] [PATCH 12/12] drm/i915:skl: Remove WaDisablePowerCompilerClockGating

On Fri, Sep 25, 2015 at 02:33:46PM +0100, Arun Siluvery wrote: > Dropping it because it is for pre-production stepping. > > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 - > 1 file changed, 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbu

Re: [Intel-gfx] [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

On Fri, Sep 25, 2015 at 02:33:41PM +0100, Arun Siluvery wrote: > It is also applicable for B0. > > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/intel_pm.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/dr

Re: [Intel-gfx] [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

On Fri, Sep 25, 2015 at 02:33:38PM +0100, Arun Siluvery wrote: > Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no > name > as they are part of same register. This will save an entry in WA array. > > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/intel_ringbu

Re: [Intel-gfx] [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote: > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/intel_pm.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ab5ac5e..093a5e4 100644 > -

[Intel-gfx] [PATCH i-g-t] tests/pm_rc6_residency: Measure the sleep duration

From: Ville Syrjälä The code is confused about the units of CODE_TIME. The comment says 50 microsseconds, but the actual code makes it 50 milliseconds. Avoid the whole mess by measuring the sleep duration ourselves. Since the time measurement is taken around the whole operation it obviously inclu

Re: [Intel-gfx] [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn

On Fri, Sep 25, 2015 at 05:40:46PM +0100, Arun Siluvery wrote: > Signed-off-by: Arun Siluvery Series lgtm, so Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++-- > 1 file changed, 2 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_

Re: [Intel-gfx] [PATCH] drm/i915: Detect virtual south bridge

On 09/25/2015 08:31 AM, Jesse Barnes wrote: > On 09/24/2015 08:41 PM, Tian, Kevin wrote: >>> From: Jesse Barnes [mailto:jbar...@virtuousgeek.org] >>> Sent: Friday, September 25, 2015 12:41 AM >>> >>> On 08/28/2015 05:10 AM, robert.beck...@intel.com wrote: From: Robert Beckett Virtua

[Intel-gfx] [PATCH v2 05/10] drm/i915/bdw: Remove WaDisableThreadStallDopClockGating

Dropping it because it is for pre-production stepping. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index d8fa9d1..0b545cf 100644 -

[Intel-gfx] [PATCH v2 00/10] Gen8 WA cleanup patches

Add gen8_init_workarounds() and initialize common WA in this func. v2: drop pre-production WA and order them based on register as below (Ville). instpm mi_mode row chicken half slice chicken common slice chicken hdc chicken cache_mode_0 cache_mode_1 gt_mode Only the WA in gen8_init_workarounds()

[Intel-gfx] [PATCH v2 10/10] drm/i915/gen8: Move WaHdcDisableFetchWhenMasked to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 1e60aa0..35afe73 100644 --- a/drivers/gpu/drm/i915/intel_ri

[Intel-gfx] [PATCH v2 06/10] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++--- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 0b545cf..a42dff9 100644 --- a/drivers/g

[Intel-gfx] [PATCH v2 08/10] drm/i915/gen8: Move GEN7_GT_MODE WA to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++-- 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 1b12584..97f9cec 100644 --- a/d

[Intel-gfx] [PATCH v2 01/10] drm/i915/gen8: Add gen8_init_workarounds for common WA

WA in this function should be ordered based on register address. The following order is suggested (Ville), instpm mi_mode row chicken half slice chicken common slice chicken hdc chicken cache_mode_0 cache_mode_1 gt_mode Cc: Ville Syrjälä Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/in

[Intel-gfx] [PATCH v2 02/10] drm/i915/gen8: Move INSTPM WA to common function

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 10f9ea0..4f3942f 100644 --- a/drivers/gpu/drm/i915/intel_ri

[Intel-gfx] [PATCH v2 04/10] drm/i915/gen8: Move WaDisablePartialInstShootdown to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3bc14fa..d8fa9d1 100644 --- a/drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH v2 07/10] drm/i915/gen8: Move Wa4x4STCOptimizationDisable to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a42dff9..1b12584 100644 --- a/drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH v2 09/10] drm/i915/gen8: Move WaForceEnableNonCoherent to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 20 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 97f9cec..1e60aa0 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH v2 03/10] drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 4f3942f..3bc14fa 100644 --- a/drivers/gpu/drm/i915/intel_r

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/guc: Add GuC css header parser

On 09/25/2015 07:45 AM, Jani Nikula wrote: On Thu, 24 Sep 2015, Yu Dai wrote: > On 09/24/2015 12:04 PM, Dave Gordon wrote: >> On 24/09/15 19:34, Yu Dai wrote: >> > >> > >> > On 09/24/2015 07:23 AM, Dave Gordon wrote: >> >> On 22/09/15 21:48, yu@intel.com wrote: >> >> > From: Alex Dai >> >

Re: [Intel-gfx] [PATCH] drm/i915: Don't call intel_prepare_ddi when encoder list isn't yet initialized.

On Fri, 2015-09-25 at 13:52 +0300, Jani Nikula wrote: > On Wed, 23 Sep 2015, Rodrigo Vivi wrote: > > In case something goes wrong with power well initialization we were > > calling > > intel_prepare_ddi during boot while encoder list isnt't initilized. > > Broken record, is this a regression, wha

Re: [Intel-gfx] [PATCH] drm/i915: Consider HW CSB write pointer before resetting the sw read pointer

Michel Thierry writes: > A previous commit resets the Context Status Buffer (CSB) read pointer in > ring init > commit c0a03a2e4c4e ("drm/i915: Reset CSB read pointer in ring init") > > This is generally correct, but this pointer is not reset after > suspend/resume in some platforms (cht). In

Re: [Intel-gfx] [PATCH] drm/i915: Detect virtual south bridge

On 09/24/2015 08:41 PM, Tian, Kevin wrote: >> From: Jesse Barnes [mailto:jbar...@virtuousgeek.org] >> Sent: Friday, September 25, 2015 12:41 AM >> >> On 08/28/2015 05:10 AM, robert.beck...@intel.com wrote: >>> From: Robert Beckett >>> >>> Virtualized systems often use a virtual P2X4 south bridge.

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/guc: Add GuC css header parser

On Thu, 24 Sep 2015, Yu Dai wrote: > On 09/24/2015 12:04 PM, Dave Gordon wrote: >> On 24/09/15 19:34, Yu Dai wrote: >> > >> > >> > On 09/24/2015 07:23 AM, Dave Gordon wrote: >> >> On 22/09/15 21:48, yu@intel.com wrote: >> >> > From: Alex Dai >> >> > >> >> > By using information from GuC css h

Re: [Intel-gfx] [PATCH 02/15] drm/i915/guc: Add GuC css header parser

On Wed, 16 Sep 2015, yu@intel.com wrote: > From: Alex Dai > > By using information from GuC css header, we can eliminate some > hard code w.r.t size of some components of firmware. There's a catch here. You can't trust any of the firmware blob contents. None at all. It's all malicious user in

Re: [Intel-gfx] [PATCH 7/7] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn

On Fri, Sep 25, 2015 at 02:23:34PM +0100, Arun Siluvery wrote: > Signed-off-by: Arun Siluvery > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++--- > 1 file changed, 10 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/

Re: [Intel-gfx] [PATCH 5/7] drm/i915/gen8: Move GEN8_ROW_CHICKEN WA to common init fn

On Fri, Sep 25, 2015 at 02:23:32PM +0100, Arun Siluvery wrote: > Move WaDisablePartialInstShootdown and WaDisableThreadStallDopClockGating NAK for WaDisableThreadStallDopClockGating, we don't want it on production BDW. Should just kill it for BDW instead. > > Signed-off-by: Arun Siluvery > ---

[Intel-gfx] [PATCH v2 7/7] drm/i915: Add HDMI aspect ratio property for SDVO

From: Ville Syrjälä Handle the HDMI aspect ratio property the same way in the SDVO code as we handle it in the HDMI code. v2: Remove stray whitespace change Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 9 - drivers/g

[Intel-gfx] [PATCH v2 4/7] drm/i915: Always use crtc_ timings when dealing with adjustead_mode

From: Ville Syrjälä The adjustead_mode crtc_ timings are what we will program into the hardware, so it's those timings we should be looking practically everywhere. The normal and crtc_ timings should differ only when stere doubling is used. In that case the normal timings are the orignal non-dou

[Intel-gfx] [PATCH v2 3/7] drm/i915: s/mode/adjusted_mode/ in functions that really get passed the adjusted_mode

From: Ville Syrjälä Rename the function argument to 'adjusted_mode' whenever the function only ever gets passed the adjusted_mode. v2: Update due to intel_dsi.c changes Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_audio.c | 17 +

[Intel-gfx] [PATCH 06/12] drm/i915/bxt: Add WaStoreMultiplePTEenable name

Updated WA with the name. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_pm.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c73d37d..9151a2b 100644 --- a/drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 03/12] drm/i915/gen9: Merge two WA as they part of same register

Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save an entry in WA array. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu

[Intel-gfx] [PATCH 10/12] drm/i915/skl: Remove WaDisableVFUnitClockGating

Dropping it because it is for pre-production stepping, also removed bit definition in i915_reg.h as it is not used anywhere else. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_reg.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 6 -- 2 files changed, 7 deletions(-) diff --git a/driv

[Intel-gfx] [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

Dropping it as it is for pre-production stepping. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_lrc.c| 5 ++--- drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++ 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 08/12] drm/i915/skl: Remove WaDisableSDEUnitClockGating

Dropping it because it is for pre-production stepping. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_pm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index be39f7ad..a6ee0d3 100644 --- a/dr

[Intel-gfx] [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no name as they are part of same register. This will save an entry in WA array. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 18 -- 1 file changed, 8 insertions(+), 10 deletions(

[Intel-gfx] [PATCH 12/12] drm/i915:skl: Remove WaDisablePowerCompilerClockGating

Dropping it because it is for pre-production stepping. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index d5fdbc8..2a33b9d 100644

[Intel-gfx] [PATCH 05/12] drm/i915/bxt: update WaSetHDCunitClckGatingDisable

The implementation for this WA is same as WaSetHdcUnitClockGatingDisableInUcgctl6. Both of them are for BXT:A0 except that WaSetHdcUnitClockGatingDisableInUcgctl6 is applicable only when either SS0 or SS2 is active but if we apply the former WA then the latter one also gets applied irrespective o

[Intel-gfx] [PATCH 01/12] drm/i915/gen9: Handle error returned by gen9_init_workarounds

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index fdff606..6671800 100644 --- a/drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

It is also applicable for B0. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_pm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9151a2b..be39f7ad 100644 --- a/drivers/gpu/drm/i915/int

[Intel-gfx] [PATCH 09/12] drm/i915/skl: Remove WaSetGAPSunitClckGateDisable

Dropping it because it is for pre-production stepping, also removed bit definition in i915_reg as it is not used anywhere else. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_reg.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 6 -- 2 files changed, 7 deletions(-) diff --git a/driver

[Intel-gfx] [PATCH 00/12] Gen9: Changes to add/merge/update/remove WA

Changes that add new WA, merge WA that are applied for the same register, update stepping checks and remove pre-production ones . Arun Siluvery (12): drm/i915/gen9: Handle error returned by gen9_init_workarounds drm/i915/gen9: Add WaOCLCoherentLineFlush drm/i915/gen9: Merge two WA as they pa

[Intel-gfx] [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ab5ac5e..093a5e4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -

[Intel-gfx] [PATCH 7/7] drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++--- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index c681c66..fdff606 100644 --- a/drivers/g

[Intel-gfx] [PATCH 1/7] drm/i915/gen8: Add gen8_init_workarounds for common WA

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 16a4ead..10f9ea0 100644 --- a/drivers/gpu/drm/i915/intel_ringbuff

[Intel-gfx] [PATCH 6/7] drm/i915/gen8: Move GEN7_GT_MODE WA to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++-- 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5d15e31..c681c66 100644 --- a/d

[Intel-gfx] [PATCH 5/7] drm/i915/gen8: Move GEN8_ROW_CHICKEN WA to common init fn

Move WaDisablePartialInstShootdown and WaDisableThreadStallDopClockGating Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 3/7] drm/i915/gen8: Move WaDisableAsyncFlipPerfMode to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 4f3942f..3bc14fa 100644 --- a/drivers/gpu/drm/i915/intel_r

[Intel-gfx] [PATCH 4/7] drm/i915/gen8: Move Wa4x4STCOptimizationDisable to common init fn

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3bc14fa..a06788a 100644 --- a/drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH 2/7] drm/i915/gen8: Move INSTPM WA to common function

Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_ringbuffer.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 10f9ea0..4f3942f 100644 --- a/drivers/gpu/drm/i915/intel_ri

Re: [Intel-gfx] [PATCH] drm/i915: On reset/suspend disable hpd pins & cancel pending delayed work

On Fri, Sep 25, 2015 at 08:09:57AM +0200, Egbert Eich wrote: > This makes sure no hpd interrupt or reenable worker fires when > resetting or suspending. > We already call intel_hpd_init() in most cases on resume and > after reset to undo this. > > Signed-off-by: Egbert Eich > --- > drivers/gpu/d

Re: [Intel-gfx] [PATCH] drm/i915: fix task reference leak in i915_debugfs.c

On Fri, Sep 25, 2015 at 02:16:07PM +0300, Jani Nikula wrote: > On Fri, 25 Sep 2015, Geliang Tang wrote: > > Leak a task reference in i915_ppgtt_info(), add put_task_struct() > > to fix it. > > Introduced by > > commit 1c60fef535d143860d5bf6593e24ab6417f5227c > Author: Ben Widawsky > Date: Fri

Re: [Intel-gfx] PROBLEM: Intel VGA output busticated on 4.3-rc2 (regression)

Another regression for Jairo to track. -Daniel On Thu, Sep 24, 2015 at 05:22:09PM -0400, Nick Bowler wrote: > Hi, > > Testing out 4.3-rc2, first thing I notice is that the VGA output is > not working. Specifically, the display is continuously powering on > and off -- at no point is any image vis

Re: [Intel-gfx] [RFC DP-typeC 0/2] Support USB typeC based DP on BXT

Hi Daniel, Thanks for having a look at it.. >-Original Message- >From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter >Sent: Wednesday, September 23, 2015 3:14 PM >To: R, Durgadoss >Cc: Jani Nikula; intel-gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] [RFC D

[Intel-gfx] [PULL] topic/drm-misc

Hi Dave, Another attempt at drm-misc for 4.4 ... - better atomic helpers for runtime pm drivers - atomic fbdev - dp aux i2c STATUS_UPDATE handling (for short i2c replies from the sink) - bunch of constify patches - inital kerneldoc for vga switcheroo - some vblank code cleanups from Ville and Thie

Re: [Intel-gfx] [PATCH v2 04/43] drm/i915: Parametrize fence registers

On Mon, 21 Sep 2015, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > v2: Hide the 945 vs. rest of gen2/3 difference in the macro > > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_gem_fence.c | 41 > +++ > drivers/gpu/drm/i915/i915_

Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

On Fri, Sep 25, 2015 at 12:41:42PM +0300, Imre Deak wrote: > On pe, 2015-09-25 at 10:56 +0200, Patrik Jakobsson wrote: > > On Thu, Sep 24, 2015 at 06:20:14PM +0300, Ville Syrjälä wrote: > > > On Thu, Sep 24, 2015 at 02:50:16PM +0200, Patrik Jakobsson wrote: > > > > On Wed, Sep 23, 2015 at 01:18:00P

Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

On Fri, Sep 25, 2015 at 10:56:31AM +0200, Patrik Jakobsson wrote: > On Thu, Sep 24, 2015 at 06:20:14PM +0300, Ville Syrjälä wrote: > > On Thu, Sep 24, 2015 at 02:50:16PM +0200, Patrik Jakobsson wrote: > > > On Wed, Sep 23, 2015 at 01:18:00PM +0200, Patrik Jakobsson wrote: > > > > On Wed, Sep 23, 20

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Support NV12 in rotated GGTT mapping

On Fri, Sep 25, 2015 at 10:44:44AM +0100, Tvrtko Ursulin wrote: > > On 09/24/2015 05:35 PM, Ville Syrjälä wrote: > > On Mon, Sep 21, 2015 at 10:45:34AM +0100, Tvrtko Ursulin wrote: > >> From: Tvrtko Ursulin > >> > >> Just adding the rotated UV plane at the end of the rotated Y plane. > >> > >> v2

Re: [Intel-gfx] [PATCH v2] drm/i915: Add CD and pixel clock information

On Fri, Sep 25, 2015 at 02:00:32PM +0300, Mika Kahola wrote: > This patch adds information of current and maximum CD clock > frequency and pixel clock frequency information on 'i915_debugfs.c'. > > v2: > - combined seperate patches for current CD clock, maximum CD clock > and maximum pixel clock

[Intel-gfx] [PATCH] drm/i915: fix task reference leak in i915_debugfs.c

Leak a task reference in i915_ppgtt_info(), add put_task_struct() to fix it. Signed-off-by: Geliang Tang --- drivers/gpu/drm/i915/i915_debugfs.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c

Re: [Intel-gfx] [PATCH] drm/i915: fix task reference leak in i915_debugfs.c

On Fri, 25 Sep 2015, Geliang Tang wrote: > Leak a task reference in i915_ppgtt_info(), add put_task_struct() > to fix it. Introduced by commit 1c60fef535d143860d5bf6593e24ab6417f5227c Author: Ben Widawsky Date: Fri Dec 6 14:11:30 2013 -0800 drm/i915: Dump all ppgtt > > Signed-off-by: G

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add primary plane to mask if it's visible

On Wed, 23 Sep 2015, Maarten Lankhorst wrote: > This fixes the warnings like > > "plane A assertion failure, should be disabled but not" > > that on the initial modeset during boot. This can happen if > the primary plane is enabled by the firmware, but inheriting > it fails because the DMAR is ac

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix primary_get_hw_state for gen9+.

On Wed, 23 Sep 2015, Maarten Lankhorst wrote: > On skylake and broxton the old registers are no longer in use. > Instead it uses universal planes, fix primary_get_hw to use the > correct registers. > > Signed-off-by: Maarten Lankhorst > Cc: sta...@vger.kernel.org #v4.2+ SKL/BXT have only prelim

[Intel-gfx] [PATCH v2] drm/i915: Add CD and pixel clock information

This patch adds information of current and maximum CD clock frequency and pixel clock frequency information on 'i915_debugfs.c'. v2: - combined seperate patches for current CD clock, maximum CD clock and maximum pixel clock - space added between the frequency value and the unit Signed-off-by: M

Re: [Intel-gfx] [PATCH] drm/i915: Don't call intel_prepare_ddi when encoder list isn't yet initialized.

On Wed, 23 Sep 2015, Rodrigo Vivi wrote: > In case something goes wrong with power well initialization we were calling > intel_prepare_ddi during boot while encoder list isnt't initilized. Broken record, is this a regression, what is the regressing commit, or if this was always broken, which comm

Re: [Intel-gfx] [BXT MIPI PATCH v4 14/14] drm/i915: Added BXT DSI backlight support

>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Thursday, September 24, 2015 10:29 PM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Kumar, Shobhit >Subject: Re: [Intel-gfx] [BXT MIPI PATCH v4 14/14] drm/i915: Added BXT DSI >backlight suppor

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add max DOT clock frequency to debugfs

On Thu, 2015-09-24 at 23:49 +0300, Ville Syrjälä wrote: > On Thu, Sep 24, 2015 at 02:28:41PM +0300, Mika Kahola wrote: > > Information on maximum supported pixel clock frequency to > > i915_frequency_info. > > > > Signed-off-by: Mika Kahola > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 1 + >

[Intel-gfx] Link training error with 4.3.rc2+

Hi, With 4.3.rc2+ I am seeing below WARN followed by a link training error when the login screen comes up on ubuntu. Once I get the error log in console screen goes blank and stays that way. I am also not able to get to virtual terminal. The panel connected is eDP. [ 67.279643] ACPI: Vide

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Support NV12 in rotated GGTT mapping

On 09/24/2015 05:35 PM, Ville Syrjälä wrote: On Mon, Sep 21, 2015 at 10:45:34AM +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Just adding the rotated UV plane at the end of the rotated Y plane. v2: Rebase. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_gtt.c | 37 ++

Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

On pe, 2015-09-25 at 10:56 +0200, Patrik Jakobsson wrote: > On Thu, Sep 24, 2015 at 06:20:14PM +0300, Ville Syrjälä wrote: > > On Thu, Sep 24, 2015 at 02:50:16PM +0200, Patrik Jakobsson wrote: > > > On Wed, Sep 23, 2015 at 01:18:00PM +0200, Patrik Jakobsson wrote: > > > > On Wed, Sep 23, 2015 at 10

Re: [Intel-gfx] [RFC PATCH] drm/i915/skl: Add DC6 disabling as a power well

On Thu, Sep 24, 2015 at 06:20:14PM +0300, Ville Syrjälä wrote: > On Thu, Sep 24, 2015 at 02:50:16PM +0200, Patrik Jakobsson wrote: > > On Wed, Sep 23, 2015 at 01:18:00PM +0200, Patrik Jakobsson wrote: > > > On Wed, Sep 23, 2015 at 10:43:00AM +0200, Daniel Vetter wrote: > > > > On Mon, Sep 21, 2015

Re: [Intel-gfx] [PATCH v2] drm/i915: set proper N/CTS in modeset

On Fri, 25 Sep 2015 10:01:48 +0200, Jani Nikula wrote: > > On Fri, 25 Sep 2015, libin.y...@intel.com wrote: > > From: Libin Yang > > > > When modeset occurs and the TMDS frequency is set to some > > speical values, the N/CTS need to be set manually if audio > > is playing. > > > > Signed-off-by:

[Intel-gfx] [PATCH v4] drm/i915/bdw: Check for slice, subslice and EU count for BDW

Added checks for available slices, subslices and EUs for Broadwell. This information is filled in intel_device_info and is available to user with GET_PARAM. Added checks for enabled slices, subslices and EU for Broadwell. This information is based on available counts but takes power gated slices in

Re: [Intel-gfx] [PATCH v2] drm/i915: set proper N/CTS in modeset

On Fri, 25 Sep 2015, libin.y...@intel.com wrote: > From: Libin Yang > > When modeset occurs and the TMDS frequency is set to some > speical values, the N/CTS need to be set manually if audio > is playing. > > Signed-off-by: Libin Yang Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/int

Re: [Intel-gfx] [PATCH 1/2] drm: Add a non-locking version of drm_kms_helper_poll_enable(), v2

On Fri, 25 Sep 2015, Egbert Eich wrote: > Jani Nikula writes: > > > > Shouldn't this be _unlocked? > > > > I thought the convention was that functions that do not acquire locks > > are called _unlocked (although they may require a lock to be held when > > called). And you might have foo()