Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD
exit.
Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/inte
From: Alex Dai
GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
Signed-off-by: Alex Dai
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e4818d..4d6bb6b 100644
--- a/drivers/gpu/drm/i
It will be usefull to specify w/a that affects only SKL GT3 and GT4.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5db246..1e48c86 100644
--- a
Combining all the patches together in this thread related to
RC6, Turbo and CPG.
Other pending patches under review are in the
1. Several GuC related patches
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075663.html
2. drm/i915: Increase maximum polling tim
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
v2: Added GT3/GT4 Check.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
Cc: Alex Dai
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
b/drivers/gpu/drm/i915/i915_guc_reg.h
i
Enable TO mode for RC6 for SKL till D0 and BXT till A0.
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/drm_dp_helper.c
between commits:
79a2b161c12a ("drm/dp: Define AUX_RETRY_INTERVAL as 500 us")
4efa83c8c786 ("drm/dp: Adjust i2c-over-aux retry count based on message size
and i2c bus speed")
f36203
From: Vivek Kasireddy
Currently, fb objects with rotated views are ignored while pinning. Therefore,
include the rotated view type and use the view size instead of the object's
size to determine if it is fenceable. And, look at the view and its offset
while writing and pinning to the fence regis
From: dw kim
Correct bit mapping of EUs in 'eu_disable' fuse register
for each subslice is (each word represents one subslice),
bit # 7 6 5 4 3 2 1 0
EU # 11 10 9 8 3 2 1 0
In BXT, each subslice has 6 EUs at most, which are EU0~EU2
and EU8~EU10 (EU11 and EU3 don't exi
From: dw kim
Correct bit mapping of EUs in 'eu_disable' fuse register
for each subslice is (each word represents one subslice),
bit # 7 6 5 4 3 2 1 0
EU # 11 10 9 8 3 2 1 0
In BXT, each subslice has 6 EUs at most, which are EU0~EU2
and EU8~EU10 (EU11 and EU3 don't exi
2015-08-19 5:24 GMT-03:00 ch...@chris-wilson.co.uk :
> On Tue, Aug 18, 2015 at 09:49:34PM +, Zanoni, Paulo R wrote:
>> Em Sáb, 2015-08-15 às 09:29 +0100, Chris Wilson escreveu:
>> > On Fri, Aug 14, 2015 at 06:34:13PM -0300, Paulo Zanoni wrote:
>> > > The FBC hardware for these platforms doesn't
Hi all,
New -testing cycle with cool stuff:
- initialize backlight from VBT as fallback (Jani)
- hpd A support from Ville
- various atomic polish all over (mostly from Maarten)
- first parts of virtualize gpu guest support on bdw from
Zhiyuan Lv
- GuC fixes from Alex
- polish for the chv clocks
On Tue, 1 Sep 2015 14:44:14 -0300
Danilo Cesar Lemes de Paula wrote:
> Docproc process EXPORT_SYMBOL(f1) macro and uses -nofunc f1 to
> avoid duplicated documentation in the next call.
> It works for most of the cases, but there are some specific situations
> where a struct has the same name of
From: Ville Syrjälä
This stolen reserved stuff was introduced on g4x, so no need to waste
stolen on older platforms. Unfortunately configdb is no more so I can't
look up the right way to detect this stuff. I do have one hint as to
where the register might be on ctg, but I don't have a ctg to test
From: Ville Syrjälä
Ignore DEVICE_TYPE_NOT_HDMI_OUTPUT and DEVICE_TYPE_DIGITAL_OUTPUT when
trying to determine the presence of eDP based on the VBT child device
type. Apparently a significant portion of VLV systems have these bits
set incorrectly, and so we currently fail to detect eDP on said sy
From: Ville Syrjälä
We don't support eDP on g4x, so let's not even look at the VBT
to determine the port type, just in case the VBT is bonkers
on some g4x machines and indicates the precense of eDP.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 7 +++
1 file changed, 7
On Fri, Sep 11, 2015 at 4:40 AM Sonika Jindal
wrote:
> Using intel_encoder's hpd_pin to check the live status
> because of BXT A0/A1 WA for HPD pins and hpd_pin contains the
> updated pin for the corresponding port.
>
It makes sense, but is it always true? or we should have a fallback to
intel_d
Thanks
Reviewed-by: Rodrigo Vivi
On Fri, Sep 11, 2015 at 4:38 AM Sonika Jindal
wrote:
> The Bspec is very clear that Live status must be checked about before
> trying to read EDID over DDC channel. This patch makes sure that HDMI
> EDID is read only when live status is up.
>
> The live status
On 09/10/2015 11:16 PM, Kamble, Sagar A wrote:
Hi Alex,
Kindly incorporate changes in this patch in your patch at:
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075668.html
- [PATCH 5/6] drm/i915/guc: Media domain bit needed when notify GuC rc6
state
This is because GuC sampl
On 09/11/2015 01:29 AM, Chris Wilson wrote:
> On Thu, Sep 10, 2015 at 08:20:28AM -0700, Jesse Barnes wrote:
>> Use WARN_ONCE in a bunch of places and demote a message that would
>> continually spam us.
>>
>> Signed-off-by: Jesse Barnes
>> ---
>> drivers/gpu/drm/i915/intel_csr.c| 12 +-
This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (me)
v3:
-cosmetic update, split checks into two (Ville)
v4:
-Add stride alignment and modifier checks for UV subplane (Ville)
v5:
-Make modifier check general (Vill
This patch adds NV12 to list of supported formats for
primary plane.
v2:
-Rebased (me)
v3:
-Rebased on top of primary plane YUV support patch (Ville)
Signed-off-by: Chandra Konduru
Testcase: igt/kms_nv12
---
drivers/gpu/drm/i915/intel_display.c | 26 --
1 file changed
This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.
v2:
-Added helper function for need_scaling (Ville)
v3:
-Rebased to current kernel version 4.2.0.rc4 (me)
v4:
-minor updates (Ville)
v5:
-updated scaler he
On 10 September 2015 at 16:24, Micah Fedke wrote:
> Thomas,
>
> Sure thing. Here you go:
> https://git.collabora.com/cgit/user/fedke.m/intel-gpu-tools.git/log/?h=drm_open_parameter_review05
Thanks, I've merged the series and added your signed-off-by as discussed.
>
>
> -mf
>
>
> On 09/09/2015 0
A new intel-gpu-tools quarterly release is available with the following changes:
- Various new tests and tools
- New statistical analysis functions. (Damien Lespiau)
- New benchmark tests. (Chris Wilson)
- Old register tools that were superseded by intel_reg have been removed.
- Various tests
Daniel Vetter writes:
> On Tue, Aug 04, 2015 at 11:25:40AM +0530, Animesh Manna wrote:
>>
>>
>> On 8/4/2015 9:16 AM, Nagaraju, Vathsala wrote:
>> >"This patch contains the changes to remove the byte swapping logic
>> >introduced with old dmc firmware."
>> >Which version of DMC need reversal l
On 09/11/2015 03:56 PM, Chris Wilson wrote:
On Fri, Sep 11, 2015 at 03:31:33PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Prevent leaking VMAs and PPGTT VMs when objects are imported
via flink.
Scenario is that any VMAs created by the importer will be left
dangling after the importer
On Fri, Sep 11, 2015 at 03:31:33PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Prevent leaking VMAs and PPGTT VMs when objects are imported
> via flink.
>
> Scenario is that any VMAs created by the importer will be left
> dangling after the importer exits, or destroys the PPGTT conte
From: Tvrtko Ursulin
Prevent leaking VMAs and PPGTT VMs when objects are imported
via flink.
Scenario is that any VMAs created by the importer will be left
dangling after the importer exits, or destroys the PPGTT context
with which they are associated.
This is caused by object destruction not r
From: Tvrtko Ursulin
Test that VMAs associated with a context are cleaned up when
contexts are destroyed.
In practice this emulates the leak seen between fbcon and X server.
Every time the X server exits we gain one VMA on the fbcon frame
buffer object as externally visible via for example
/sys/
This adds a test that compiles the link training code from i915 into a
separate executable and uses it to train a fake sink device. The test
iterates over possible combinations of max voltage swing, pre emphasis
and bit rates, with the sink attemting to get the highest values
possible. The test doe
On Fri, Sep 11, 2015 at 07:24:31PM +0530, Kamble, Sagar A wrote:
>
>
> On 9/11/2015 7:07 PM, Ville Syrjälä wrote:
> > On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
> >> Coarse power gating is disabled prior to BXT B0 and till SKL E0,
> >> hence even for render and media well
On 9/11/2015 7:07 PM, Ville Syrjälä wrote:
On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
Coarse power gating is disabled prior to BXT B0 and till SKL E0,
hence even for render and media well registers blitter forcewake request
need to be used.
Change-Id: Ibfa8abf02b4d27ca
On Sun, Aug 23, 2015 at 05:52:50PM +0530, Sagar Arun Kamble wrote:
> Coarse power gating is disabled prior to BXT B0 and till SKL E0,
> hence even for render and media well registers blitter forcewake request
> need to be used.
>
> Change-Id: Ibfa8abf02b4d27ca1fcd68fc9e98c2daade7c286
> Signed-off-
Thanks Chris.
Domain refcount tracking is not common single function.
its present in __force_wake_get, __intel_uncore_forcewake_get and
likewise for put functions.
Either we will have to bring them together in fw_domains_get and then
add change you have suggested
Or
Prepare WA version of __f
From: Ville Syrjälä
Each bit in the device type is supposed to mean something. Decode their
meaning.
Signed-off-by: Ville Syrjälä
---
tools/intel_bios.h| 18 ++
tools/intel_bios_reader.c | 32
2 files changed, 50 insertions(+)
diff --gi
From: Ville Syrjälä
Decode the MIPI [sic] device type.
Signed-off-by: Ville Syrjälä
---
tools/intel_bios.h| 1 +
tools/intel_bios_reader.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index a97797f..6135a2b 100644
--- a/tools/intel_bios.
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
tools/intel_bios.h| 8
tools/intel_bios_reader.c | 28
2 files changed, 36 insertions(+)
diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index 64e723d..cd6abf9 100644
--- a/tools/intel_bios
There are a few strange line breaks - intel_lrc.c lines 2475, 2478, 2486.
But anyway,
Reviewed-by: Thomas Daniel
> -Original Message-
> From: Hoath, Nicholas
> Sent: Friday, September 11, 2015 12:54 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Hoath, Nicholas; Daniel Vetter; Chris Wilso
Due to flip interrupts routed to GuC, GuC stays awake always and GT does not
enter RC6.
GuC firmware should re-direct to GuC those interrupts that it can handle.
v2: Commit message change and routing all interrupts to host. (Tom)
Cc: Alex Dai
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sag
On Fri, Sep 11, 2015 at 02:20:35PM +0200, Patrik Jakobsson wrote:
> On Fri, Sep 11, 2015 at 03:10:05PM +0300, Dmitry V. Levin wrote:
> > On Fri, Sep 11, 2015 at 01:39:29PM +0200, Patrik Jakobsson wrote:
> > > On Wed, Sep 09, 2015 at 01:50:40AM +0300, Dmitry V. Levin wrote:
> > > > On Mon, Aug 24, 2
Hi Tom, Akash
Kindly review this patch.
Thanks
Sagar
On 9/11/2015 11:53 AM, Kamble, Sagar A wrote:
Gentle reminder for review.
Thanks
Sagar
On 8/23/2015 5:52 PM, Sagar Arun Kamble wrote:
Disable Turbo on steppings prior to B0 on BXT due to hangs seen
during GT CPD exit.
Change-Id: I50c5c
Enable TO mode for RC6 for SKL till D0 and BXT till A0.
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915
Cc: Alex Dai
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
b/drivers/gpu/drm/i915/i915_guc_reg.h
i
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e4818d..4d6bb6b 100644
--- a/drivers/gpu/drm/i
On Fri, Sep 11, 2015 at 03:10:05PM +0300, Dmitry V. Levin wrote:
> On Fri, Sep 11, 2015 at 01:39:29PM +0200, Patrik Jakobsson wrote:
> > On Wed, Sep 09, 2015 at 01:50:40AM +0300, Dmitry V. Levin wrote:
> > > On Mon, Aug 24, 2015 at 02:42:50PM +0200, Patrik Jakobsson wrote:
> > > > +static int drm_m
On Fri, Sep 11, 2015 at 01:39:29PM +0200, Patrik Jakobsson wrote:
> On Wed, Sep 09, 2015 at 01:50:40AM +0300, Dmitry V. Levin wrote:
> > On Mon, Aug 24, 2015 at 02:42:50PM +0200, Patrik Jakobsson wrote:
> > > +static int drm_mode_create_dumb(struct tcb *tcp, const unsigned int
> > > code, long arg
On Fri, Sep 11, 2015 at 01:31:02PM +0200, Patrik Jakobsson wrote:
> On Tue, Sep 08, 2015 at 04:18:11AM +0300, Dmitry V. Levin wrote:
> > On Mon, Aug 24, 2015 at 02:42:49PM +0200, Patrik Jakobsson wrote:
> > > +static int i915_getparam(struct tcb *tcp, const unsigned int code, long
> > > arg)
> > >
We need to be able to control if DC6 is allowed or not. Much like
requesting power to a specific piece of the hardware we need to be able
to request that we don't enter DC6 during certain hw access.
To solve this without introducing too much infrastructure I'm hooking
into the power well / power d
Extend init/init_hw split to context init.
- Move context initialisation in to i915_gem_init_hw
- Move one off initialisation for render ring to
i915_gem_validate_context
- Move default context initialisation to logical_ring_init
Rename intel_lr_context_deferred_create to
intel_lr
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
v2: Added GT3/GT4 Check.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
On Wed, Sep 09, 2015 at 01:50:40AM +0300, Dmitry V. Levin wrote:
> On Mon, Aug 24, 2015 at 02:42:50PM +0200, Patrik Jakobsson wrote:
> > First batch of drm / kms ioctls.
>
> Several comments in addition to issues similar to 4/5 patch.
>
> > +static int drm_mode_rm_fb(struct tcb *tcp, const unsign
Using intel_encoder's hpd_pin to check the live status
because of BXT A0/A1 WA for HPD pins and hpd_pin contains the
updated pin for the corresponding port.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_dp.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --
The Bspec is very clear that Live status must be checked about before
trying to read EDID over DDC channel. This patch makes sure that HDMI
EDID is read only when live status is up.
The live status doesn't seem to perform very consistent across various
platforms when tested with different monitors
On Tue, Sep 08, 2015 at 04:18:11AM +0300, Dmitry V. Levin wrote:
> On Mon, Aug 24, 2015 at 02:42:49PM +0200, Patrik Jakobsson wrote:
> > +static int i915_getparam(struct tcb *tcp, const unsigned int code, long
> > arg)
> > +{
> > + struct drm_i915_getparam param;
> > + int value;
> > +
> > +
On Fri, 11 Sep 2015, Deepak M wrote:
> In CABC (Content Adaptive Brightness Control) content grey level
> scale can be increased while simultaneously decreasing
> brightness of the backlight to achieve same perceived brightness.
>
> The CABC is not standardized and panel vendors are free to follow
On Tue, Sep 08, 2015 at 03:36:25AM +0300, Dmitry V. Levin wrote:
> On Mon, Aug 24, 2015 at 02:42:48PM +0200, Patrik Jakobsson wrote:
> > * Makefile.am: Add compilation of drm.c.
> > * defs.h: Add extern declaration of drm_ioctl when drm headers are found.
> > * drm.c: New file.
> > * ioctl.c (ioctl
On 9/10/2015 12:25 AM, Rodrigo Vivi wrote:
I liked the approach and agree with Daniel, so with his suggestions feel
free to use:
Reviewed-by: Rodrigo Vivi mailto:rodrigo.v...@intel.com>>
On Fri, Sep 4, 2015 at 7:46 AM Daniel Vetter mailto:dan...@ffwll.ch>> wrote:
On Fri, Sep 04, 2015 at 0
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
v2: Added GT3/GT4 Check.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
It will be usefull to specify w/a that affects only SKL GT3 and GT4.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5db246..1e48c86 100644
--- a
On Thu, Sep 10, 2015 at 08:20:28AM -0700, Jesse Barnes wrote:
> Use WARN_ONCE in a bunch of places and demote a message that would
> continually spam us.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_csr.c| 12 +--
> drivers/gpu/drm/i915/intel_runtime_pm.c |
On Fri, Sep 11, 2015 at 03:47:25AM +0200, David Herrmann wrote:
> Hi
>
> On Thu, Sep 10, 2015 at 10:39 PM, Daniel Vetter
> wrote:
> > It's completely unused and there's really no reason for this:
> > - drm_framebuffer structures are invariant after creation, no need for
> > helpers to manipula
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