Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6864
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6860
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK -1
As power well 1 is superset of power well 2 and always pw2
will be disabled first and then pw1. On the other hand dmc
is responsible to save & restore back pw1 when display
engine goes and come back from low power state. Before
disabling pw1 dmc must be loaded, so adding flush_work()
while disablin
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vatsala Nagaraju
---
drivers/gpu/drm/i915/intel_csr.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr
From: Daniel Vetter
As all csr firmware related opertion are not using any
any data structures of drm framework level, so better to
use dev_priv instead of dev. it's a new style! :)
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
-
From: Daniel Vetter
Avoids non-static functions since all the callers are in intel_rpm.c.
Only thing we need for that is to move the register definitions into
i915_reg.h.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers
As csr firmware is taking care of loading the firmware,
so no need for driver to load again.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/i915_drv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/
From: Daniel Vetter
The loader function will get a bit more complicated soon, extract the
parsing code to make the control flow clearer. While doing that just
use dev_priv->csr.dmc_payload as the indicator for whether it all
suceeded or not.
Also restrict the forced big-edian casting to just one
From: Daniel Vetter
If we really want to we can be more verbose here, but we really don't
need an entire function for this.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.c | 20
Grabbing a runtime pm reference with intel_runtime_pm_get will only
prevent device D3. But dmc firmware is required even earlier (namely
for the skl power well 1). DMC is responsible to save the status of
power well 1 and shut off the power well when panel is self refresh
mode of display is complet
From: Daniel Vetter
We need to make sure we don't put garbage into the hw if dmc firmware
loading failed mid-thru.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Daniel Vetter
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i
From: Daniel Vetter
Two benefits:
- We can use FW_LOADER_USERSPACE_FALLBACK.
- We can use flush_work to synchronize with the oustanding worker,
which is a notch more obvious what it does than having a special
completion.
The next patch will properly synchronize against the async loader in
th
While display engine entering into low power state no need to disable
cdclk pll as CSR firmware of dmc will take care. If pll is already
enabled firmware execution sequence will be blocked. This is one
of the criteria for dmc to work properly.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
S
Mmio register access after dc6/dc5 entry is causing the
system hang, so enabling dc6 as the last call in suspend flow.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/i915/i9
From: Daniel Vetter
Standard is to align continuations of parameter lists and if
conditions to the opening ( in i915 and drm code.
Apply this across the entire file since it was sticking out a bit too
much.
Also align register definitions while at it.
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sun
From: Daniel Vetter
This removes two anti-patterns:
- Locking shouldn't be used to synchronize with async work (of any
form, whether callbacks, workers or other threads). This is what the
mutex_lock/unlock seems to have been for in intel_csr_load_program.
Instead ordering should be ensured
As skl is fully dependent on dmc to go to low power state (dc5/dc6)
which requires a trigger from rpm and to ensure the dmc firmware
is available for runtime pm support rpm-reference-count is used
by not releasing the rpm reference acquire when starting the
firmware loader work.
So moved the intel
Added stepping info in intel_csr.c which is required to extract
specific firmware from packaged dmc firmware.
Cc: Vetter, Daniel
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 11 +++
1 file changed, 11 insertions
Modified HAS_CSR macro defination which earlier only supported
for skl, now added support for BXT.
Cc: Vetter, Daniel
Cc: Damien Lespiau
Cc: Imre Deak
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Cc: Damien Lespiau
Cc: Rodrigo Vivi
Cc: Sunil Kamath
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/intel_csr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 6d8a7bf..1866426 100644
--- a/drivers/gpu/drm
Display microcontroller(DMC) used to save and restore display engine status
while entering into low power display states for gen9 platform.
Though skylake and broxton both are gen9 platform but dmc act diferently.
Skylake is solely dependednt on dmc for entering into low power
state - namely dc5 an
Hello,
We launched Intel GPU Tools on 6 platforms: Skylake-Y, Braswell-M,
Broadwell-U, Baytrail M and T, Haswell-ULT to validate kernel 4.12-rc2 tag
drm-intel-testing-2015-07-17.
Here are the results:
New bugs reported:
https://bugs.freedesktop.org/show_bug.cg
On Sat, Jul 25, 2015 at 12:52:10PM +0200, Sedat Dilek wrote:
> Hi,
>
> my build breaks like this on Ubuntu/precise AMD64...
commit bff0272b4fbd0e786f77a0f5a9e4ad1eb6df893e
Author: Chris Wilson
Date: Sat Jul 25 11:54:04 2015 +0100
sna: Put the assert(!kgem->can_fence) back to where they we
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6861
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
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