On Thu, 11 Jun 2015, Hugh Greenberg wrote:
> What if you fired the uevent regardless of the previous state?
Not sending the uevent is actually a side effect of this bug, not the
main problem. I think we need something like this no matter
what. Unconditionally sending the uevent is a separate ques
On Thursday 11 June 2015 07:01 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV
docs got updated at some point to say that we need to align them to
128k, just like we do on gen4.
So far I've seen the problem man
On 06/11/2015 06:31 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV
docs got updated at some point to say that we need to align them to
128k, just like we do on gen4.
So far I've seen the problem manifest when t
Actually, observed that modprobe i915 itself is reporting
CRTC fixup failed and completing with no active planes
but with active pipe.
This looks like issue reported in:
https://bugs.freedesktop.org/show_bug.cgi?id=90861
From: Konduru, Chandra
Sent: Thursday, June 11, 2015 12:11 PM
To: intel-gfx
On Thu, Jun 11, 2015 at 07:14:28PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> When the GPU gets reset __i915_wait_request() returns -EIO to the
> mmio flip worker. Currently we WARN whenever we get anything other
> than 0. Ignore the -EIO too since it's a perfectly norm
On Thu, 2015-06-11 at 09:02 +0100, Dave Gordon wrote:
> On 10/06/15 16:52, Chris Wilson wrote:
> > On Wed, Jun 10, 2015 at 06:26:58PM +0300, Imre Deak wrote:
> >> On ke, 2015-06-10 at 08:10 -0700, Jesse Barnes wrote:
> >>> On 06/10/2015 03:59 AM, Imre Deak wrote:
> I think the discussion here
When running some kms tests (e.g., kms_plane) immediately after i915 load,
getting below error:
Jun 11 12:03:39 cmkondur-skl kernel: [ 423.098254]
[drm:intel_modeset_pipe_config] CRTC fixup failed
I am using drm-intel-nightly as of last Friday:
commit d4f412886ec9694658ab17092c3f70569a0405f9
Au
From: Paulo Zanoni
We already had a few bugs in the past where FBC was compressing
nothing when it was enabled, which makes the feature quite useless.
Add this information to debugfs so the test suites can check for
regressions in this piece of the code.
Our igt/tests/kms_frontbuffer_tracking al
From: Paulo Zanoni
Let's try to get the easy stuff merged while the rest is not ready
yet.
This is a nice opportunity for you to easily increase your patch
review count!
Paulo Zanoni (4):
drm/i915: print FBC compression status on debugfs
drm/i915: add FBC_ROTATION to enum no_fbc_reason
dr
From: Paulo Zanoni
This commit has two main advantages: simplify intel_fbc_update()
and deduplicate the strings.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 +++
drivers/gpu/drm/i915/intel_drv.h| 1 +
drivers/gpu/drm/i915/intel_fbc.c
From: Paulo Zanoni
Because we're currently using FBC_UNSUPPORTED_MODE for two different
cases.
This commit will also allow us to write the next one without hiding
information from the user.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +++
drivers/gpu/drm/i915/i915_
From: Paulo Zanoni
This commit is just to make the intentions explicit: on HSW+ these
bits are MBZ, but since we only support plane A and the macro
evaluates to zero when plane A is the parameter, we're not fixing any
bug.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 7 ++
Michel Thierry writes:
> After Mika's ppgtt cleanup series, all the other free functions have
> drm_device as the first parameter, except this one.
>
> No functional changes.
>
> Signed-off-by: Michel Thierry
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 --
>
Michel Thierry writes:
> A safer way to update the PDPx registers is sending lri commands, added
> in the ring before the batchbuffer start. Otherwise, the ctx must be idle
> before trying to change anything (but the ring-tail) in the ctx image. An
> example where the ctx won't be idle is lite-re
Maintain base page handling functions in order of
alloc, free, init. No functional changes.
v2: s/Introduce/Maintain (Michel)
Signed-off-by: Mika Kuoppala
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 ++---
1 file changed, 27 insertio
As there is flushing involved when we have done the cpu
write, make functions for mapping for cpu space. Make macros
to map any type of paging structure.
v2: Make it clear tha flushing kunmap is only for ppgtt (Ville)
v3: Flushing fixed (Ville, Michel). Removed superfluous semicolon
Cc: Ville Syr
When we setup page directories and tables, we point the entries
to a to the next level scratch structure. Make this generic
by introducing a fill_page_dma which maps and flushes. We also
need 32 bit variant for legacy gens.
v2: Fix flushes and handle valleyview (Ville)
v3: Now really fix flushes (
All the paging structures are now similar and mapped for
dma. The unmapping is taken care of by common accessors, so
don't overload the reader with such details.
v2: Be consistent with goto labels (Michel)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++
All our paging structures have struct page and dma address
for that page.
Add struct for page/dma address pairs and use it to make
the setup and teardown for different paging structures
identical.
Include the page directory offset also in the struct for legacy
gens. Rename it to clearly point out
We can have exactly 4GB sized ppgtt with 32bit system.
size_t is inadequate for this.
v2: Convert a lot more places (Daniel)
Signed-off-by: Mika Kuoppala
---
drivers/char/agp/intel-gtt.c| 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 42 ++---
drivers/gp
When we touch gen8+ page maps, mark them dirty like we
do with previous gens.
v2: Update comment (Joonas)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_g
From: Ville Syrjälä
When the GPU gets reset __i915_wait_request() returns -EIO to the
mmio flip worker. Currently we WARN whenever we get anything other
than 0. Ignore the -EIO too since it's a perfectly normal thing
to get during a GPU reset.
Also give intel_finish_fb() the same treatment, whic
Tomas Elf writes:
> On 22/05/2015 18:05, Mika Kuoppala wrote:
>> During review of dynamic page tables series, I was able
>> to hit a lite restore bug with execlists. I assume that
>> due to incorrect pd, the batch run out of legit address space
>> and into the scratch page area. The ACTHD was inc
Michel Thierry writes:
> On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
>> Lay out scratch page structure in similar manner than other
>> paging structures. This allows us to use the same tools for
>> setup and teardown.
>>
>> Signed-off-by: Mika Kuoppala
>> ---
>> drivers/gpu/drm/i915/i915_gem_gt
From: Ville Syrjälä
When the GPU gets reset __i915_wait_request() returns -EIO to the
mmio flip worker. Currently we WARN whenever we get anything other
than 0. Ignore the -EIO too since it's a perfectly normal thing
to get during a GPU reset.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i
A new intel-gpu-tools quarterly release is available with the following changes:
- Various new tests and tools
- Single combined test list (supported by piglit since commit 8a122bb)
- Optional dependency on libunwind to provide automatic stack traces on test
failures. (Thomas Wood)
- Add opti
Joonas Lahtinen writes:
> On pe, 2015-05-22 at 20:04 +0300, Mika Kuoppala wrote:
>> Check the allocation area against the known end
>> of address space instead of against fixed value.
>>
>> v2: Return ENODEV on internal bugs (Chris)
>>
>> Signed-off-by: Mika Kuoppala
>> ---
>> drivers/gpu/drm
On Thu, Jun 11, 2015 at 02:26:59AM +0300, Dmitry V. Levin wrote:
> On Wed, Jun 10, 2015 at 01:52:33PM +0200, Patrik Jakobsson wrote:
> > On Wed, Jun 10, 2015 at 01:14:20AM +0300, Dmitry V. Levin wrote:
> > > On Tue, Jun 09, 2015 at 01:26:42PM +0200, Patrik Jakobsson wrote:
> [...]
> > > > +#define
Dave Gordon writes:
> On 10/06/15 12:42, Michel Thierry wrote:
>> On 5/29/2015 1:53 PM, Michel Thierry wrote:
>>> On 5/29/2015 12:05 PM, Michel Thierry wrote:
On 5/22/2015 6:04 PM, Mika Kuoppala wrote:
> With BDW/SKL and 32bit addressing mode only, the hardware preloads
> pdps. Howev
On Thu, Jun 11, 2015 at 04:31:16PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The docs don't support the 64k linear scanout alignment we impose
> on gen2/3. And it really makes no sense since we have no DSPSURF
> register, so the only thing that the hardware will see is
On Thu, Jun 11, 2015 at 04:31:14PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Currently intel_gen4_compute_page_offset() simply picks the closest
> page boundary below the linear offset. That however may not be suitably
> aligned to satisfy any hardware specific restric
On Thu, Jun 11, 2015 at 02:27:12AM +0300, Dmitry V. Levin wrote:
> On Wed, Jun 10, 2015 at 02:45:24PM +0200, Patrik Jakobsson wrote:
> > On Wed, Jun 10, 2015 at 01:35:35AM +0300, Dmitry V. Levin wrote:
> > > On Tue, Jun 09, 2015 at 01:26:43PM +0200, Patrik Jakobsson wrote:
> [...]
> > > > +static i
From: Ville Syrjälä
Currently intel_gen4_compute_page_offset() simply picks the closest
page boundary below the linear offset. That however may not be suitably
aligned to satisfy any hardware specific restrictions. So let's make
sure the page boundary we choose is properly aligned.
Also to play
From: Ville Syrjälä
VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV
docs got updated at some point to say that we need to align them to
128k, just like we do on gen4.
So far I've seen the problem manifest when the stride is an odd multiple
of 512 bytes, and the surface addr
From: Ville Syrjälä
The docs don't support the 64k linear scanout alignment we impose
on gen2/3. And it really makes no sense since we have no DSPSURF
register, so the only thing that the hardware will see is the linear
offset which will be just pixel aligned anyway.
There is one case where 64k
On Wed, Jun 10, 2015 at 04:16:12PM -0700, Chandra Konduru wrote:
> Delete the duplicate #defines introduced by:
>
> commit 6b457d31ea0465fcadcf6d5044f5f71398954727
> Author: A.Sunil Kamath
> Date: Thu Apr 16 14:22:09 2015 +0530
>
> drm/i915/skl: Implement enable
On Thu, 11 Jun 2015, Tvrtko Ursulin wrote:
> On 06/11/2015 08:06 AM, Chris Wilson wrote:
>> With the introduction of multiple views of an obj in the same vm, each
>> vma was taught to cache its copy of the pages (so that different views
>> could have different page arrangements). However, this mis
From: dhanyapr
This patch will verify color correction capability of a display driver.
Currently Pipe level CSC and Pipe level Gamma are supported.
Signed-off-by: dhanyapr
---
tests/Makefile.sources |1 +
tests/kms_color.c | 508
2 fil
True.
Chris and Vivi,
I am trying to understand the PSR exit and entry along with SFU
requirement here.
AFAIK in existing code also
on rendering start fb_obj_invalidate is calling the
psr_invalidate(psr_exit)
on flip prepare single frame update is done
on flip complet
From: dhanyapr
This patch will verify color correction capability of a display driver.
Currently Pipe level CSC and Pipe level Gamma are supported.
Signed-off-by: dhanyapr
---
tests/Makefile.sources |1 +
tests/kms_color.c | 508
2 fil
On 6/11/2015 8:31 AM, Dave Gordon wrote:
On 10/06/15 12:42, Michel Thierry wrote:
On 5/29/2015 1:53 PM, Michel Thierry wrote:
On 5/29/2015 12:05 PM, Michel Thierry wrote:
On 5/22/2015 6:04 PM, Mika Kuoppala wrote:
With BDW/SKL and 32bit addressing mode only, the hardware preloads
pdps. Howeve
On Wed, Jun 10, 2015 at 09:18:29AM -0700, Matt Roper wrote:
> On Thu, Jun 04, 2015 at 06:01:35PM +0300, Imre Deak wrote:
> > According to bspec the DDI PHY vswing scale value is "don't care" in
> > case the scale enable bit [27] is clear. But this doesn't seem to be
> > correct. The scale value see
On 06/11/2015 08:06 AM, Chris Wilson wrote:
With the introduction of multiple views of an obj in the same vm, each
vma was taught to cache its copy of the pages (so that different views
could have different page arrangements). However, this missed decoupling
those vma->ggtt_view.pages when the v
On Thu, Jun 11, 2015 at 03:08:35PM +0530, Ramalingam C wrote:
> After scheduling a flip for obj, frontbuffer should be invalidated.
> Hence intel_frontbuffer_invalidate is invoked at flip preparation.
>
> Signed-off-by: Ramalingam C
> Cc: Chris Wilson
> References: https://bugs.freedesktop.org/s
After scheduling a flip for obj, frontbuffer should be invalidated.
Hence intel_frontbuffer_invalidate is invoked at flip preparation.
Signed-off-by: Ramalingam C
Cc: Chris Wilson
References: https://bugs.freedesktop.org/show_bug.cgi?id=90418
---
drivers/gpu/drm/i915/intel_frontbuffer.c |1
fb_obj invalidate is divided into two functions. So that
we can invoke the frontbuffer invalidation from the flip
preparation also.
Signed-off-by: Ramalingam C
Cc: Chris Wilson
References: https://bugs.freedesktop.org/show_bug.cgi?id=90418
---
drivers/gpu/drm/i915/intel_frontbuffer.c | 42 +++
Sorry for late response. I was away for longer.
Daniel,
As we have the intel_frontbuffer_flush, I have created the
intel_frontbuffer_invalidate.
This can be called from flip preparation notification to handle the
frontbuffer invalidation.
I will share the patches now.
On Monday 18 May 2015 0
On 08/06/15 18:45, Chris Wilson wrote:
> On Mon, Jun 08, 2015 at 06:03:28PM +0100, Tomas Elf wrote:
>> 1. The i915_wedged_set function allows us to schedule three forms of hang
>> recovery:
>>
>> a) Legacy hang recovery: By passing e.g. -1 we trigger the legacy full
>> GPU reset recovery
On Thu, 2015-06-11 at 12:03 +0300, Jani Nikula wrote:
> On Thu, 11 Jun 2015, Mika Kahola wrote:
> > Limit CHV maximum cdclk to 320MHz.
> >
> > v2: Rebase to the latest
> >
> > Signed-off-by: Mika Kahola
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+),
On 08/06/15 18:03, Tomas Elf wrote:
> In preparation for per-engine reset add way for setting context reset stats.
>
> OPEN QUESTIONS:
> 1. How do we deal with get_reset_stats and the GL robustness interface when
> introducing per-engine resets?
>
> a. Do we set context that cause per-engin
On Thu, 11 Jun 2015, "Malladi, Kausal" wrote:
> I am guessing, the mails were not received because I wasn't subscribed
> to the these two mailing lists. Now I am subscribed and shouldn't have
> any problem hopefully.
In that case they should've popped up in the intel-gfx moderation list,
but for
On Thu, 11 Jun 2015, Mika Kahola wrote:
> Limit CHV maximum cdclk to 320MHz.
>
> v2: Rebase to the latest
>
> Signed-off-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b
On Thu, Jun 11, 2015 at 11:35:59AM +0300, Jani Nikula wrote:
> Currently it's possible this happens when a (non-DP) cable is unplugged:
>
> - user starts unplugging cable
> - hotplug irq fires
> - hotplug work function runs
> - connector detect function runs
> - ddc pin is still connected, edid re
On Thu, 11 Jun 2015, Jani Nikula wrote:
> Currently it's possible this happens when a (non-DP) cable is unplugged:
>
> - user starts unplugging cable
> - hotplug irq fires
> - hotplug work function runs
> - connector detect function runs
> - ddc pin is still connected, edid read succeeds
> -> we
Hi Dave -
Skylake CSR firmware name change for v4.2. Hopefully we can stick to
this one now.
BR,
Jani.
The following changes since commit 501fd70fcaebc911b6b96a7b331e6960e5af67e7:
drm/i915: limit PPGTT size to 2GB in 32-bit platforms (2015-05-29 19:08:22
+0200)
are available in the git re
Hi Dave -
Fix for the regression Linus called out, and another for probing
dongles.
BR,
Jani.
The following changes since commit d4a4f75cd8f29cd9464a5a32e9224a91571d6649:
Linux 4.1-rc7 (2015-06-07 20:23:50 -0700)
are available in the git repository at:
git://anongit.freedesktop.org/drm-
Currently it's possible this happens when a (non-DP) cable is unplugged:
- user starts unplugging cable
- hotplug irq fires
- hotplug work function runs
- connector detect function runs
- ddc pin is still connected, edid read succeeds
-> we decide nothing changed, no uevent
- cable completely un
On Thu, Jun 11, 2015 at 09:25:16AM +0100, Dave Gordon wrote:
> On 10/06/15 15:58, Chris Wilson wrote:
> > As the clflush operates on cache lines, and we can flush any byte
> > address, in order to flush all bytes given in the range we issue an
> > extra clflush on the last byte to ensure the last c
On 10/06/15 15:58, Chris Wilson wrote:
> As the clflush operates on cache lines, and we can flush any byte
> address, in order to flush all bytes given in the range we issue an
> extra clflush on the last byte to ensure the last cacheline is flushed.
> We can can the iteration to be over the actual
On Thu, Jun 11, 2015 at 09:02:44AM +0100, Dave Gordon wrote:
> On 10/06/15 16:52, Chris Wilson wrote:
> > I seem to recall that we tried clflushing for gen6+, but we didn't
> > record any details, so it may be worth retesting ivb with that w/a.
>
> Is that clflush on the CPU, or MI_CLFLUSH on the
On 10/06/15 16:52, Chris Wilson wrote:
> On Wed, Jun 10, 2015 at 06:26:58PM +0300, Imre Deak wrote:
>> On ke, 2015-06-10 at 08:10 -0700, Jesse Barnes wrote:
>>> On 06/10/2015 03:59 AM, Imre Deak wrote:
I think the discussion here is about two separate things:
1. Possible ordering issue be
I am guessing, the mails were not received because I wasn't subscribed to the
these two mailing lists. Now I am subscribed and shouldn't have any problem
hopefully.
Thanks Damien for bringing it to my notice.
Regards
Kausal
-Original Message-
From: Lespiau, Damien
Sent: Tuesday, June
For Cherryview the CD clock is limited up
to 320MHz.
Mika Kahola (1):
drm/i915: Limit CHV max cdclk
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.free
Limit CHV maximum cdclk to 320MHz.
v2: Rebase to the latest
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c38c297..ab40d04
On 10/06/15 12:42, Michel Thierry wrote:
> On 5/29/2015 1:53 PM, Michel Thierry wrote:
>> On 5/29/2015 12:05 PM, Michel Thierry wrote:
>>> On 5/22/2015 6:04 PM, Mika Kuoppala wrote:
With BDW/SKL and 32bit addressing mode only, the hardware preloads
pdps. However the TLB invalidation only
On Thu, 11 Jun 2015, Dhanya Pillai wrote:
> From: dhanyapr
>
Please split your patch title to form a proper commit message. See git
log for examples.
BR,
Jani.
> Signed-off-by: dhanyapr
> ---
> tests/Makefile.sources | 1 +
> tests/kms_color.c | 508
> +++
With the introduction of multiple views of an obj in the same vm, each
vma was taught to cache its copy of the pages (so that different views
could have different page arrangements). However, this missed decoupling
those vma->ggtt_view.pages when the vma released its reference on the
obj->pages. As
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