On Wed, 06 May 2015, "Jindal, Sonika" wrote:
> On 5/5/2015 7:28 PM, Jani Nikula wrote:
>> On Tue, 05 May 2015, Damien Lespiau wrote:
>>> On Tue, May 05, 2015 at 02:39:48PM +0300, Jani Nikula wrote:
There's still the question whether we can default to using the vbt value
if that can be b
So. -rc1 broke suspending by closing my laptop lid and it's not fixed in
-rc2. It works exactly *one* first time and every subsequent lid-closing
is ignored.
Biscted and tested first bad commit:
14aa02449064541217836b9f3d3295e241d5ae9c
This pulls in i915 changes as well as ACPI changes. I don't k
On 5/5/2015 7:28 PM, Jani Nikula wrote:
On Tue, 05 May 2015, Damien Lespiau wrote:
On Tue, May 05, 2015 at 02:39:48PM +0300, Jani Nikula wrote:
There's still the question whether we can default to using the vbt value
if that can be broken...
This is a workaround for SDPs loaded with a "def
i-g-t now creates a single combined test list for tests with
and without subtests. This patch adapts run-tests.sh to that
change.
Signed-off-by: Mike Mason
---
scripts/run-tests.sh | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/scripts/run-tests.sh b/scr
Repeating those tests[1] on linux-next 20150505 gave the same results,
but having seen the intermittent "no window title bar" problem twice
more, I now have to consider it a result of my patch[0], and hence
withdraw it.
However, that doesn't mean there isn't a security proble
2015-04-07 10:44 GMT-03:00 Daniel Vetter :
> On Tue, Apr 07, 2015 at 11:12:09AM +0100, Chris Wilson wrote:
>> On Tue, Apr 07, 2015 at 11:07:07AM +0200, Daniel Vetter wrote:
>> > On Tue, Apr 07, 2015 at 09:36:37AM +0100, Chris Wilson wrote:
>> > > On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vet
From: Paulo Zanoni
Commit 47f6b1305cc3752f318a555b932e194e1500c1d8 completely broke this
test due to the fread() assertion. When we're reading the debugfs file
we really don't care about how many bytes we read because the number
is not constant and we just use strstr() later. Change the assertion
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6320
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 05/05/2015 11:57 AM, Peter Hurley wrote:
> On 05/05/2015 11:42 AM, Daniel Vetter wrote:
>> I'm also somewhat confused about how you to a line across both cpus for
>> barriers because barriers only have cpu-local effects (which is why we
>> always need a barrier on both ends of a transaction).
I
On Thu, Apr 30, 2015 at 04:39:23PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f637667..25
On Thu, Apr 30, 2015 at 04:39:21PM +0100, Damien Lespiau wrote:
> We need to re-init the display hardware when going out of suspend. This
> includes:
>
> - Hooking the PCH to the reset logic
> - Restoring CDCDLK
> - Enabling the DDB power
>
> Among those, only the CDCDLK one is a bit tricky
On Thu, Apr 30, 2015 at 04:39:20PM +0100, Damien Lespiau wrote:
> The specs tell us to ungate PG1 and Misc I/O at display init. We'll use
> the PLLS power domain to ensure those two power wells are up.
>
> Signed-off-by: Damien Lespiau
Yep, spec does say that.
Reviewed-by: Ville Syrjälä
> ---
On Thu, Apr 30, 2015 at 04:39:19PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
Patches 2,3,4 satisfy my brain's visual pattern matcher.
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
>
On Thu, Apr 30, 2015 at 04:39:16PM +0100, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runti
On 29/04/15 23:13, yu@intel.com wrote:
> From: Alex Dai
>
> All gem objects used by GuC are pinned to ggtt space out of range
> [0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
> used internally for its Boot ROM, SRAM etc. Currently this WPOCM
> size is 512K. This is done by
> -Original Message-
> From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
> Sent: Tuesday, May 05, 2015 2:53 AM
> To: Intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko; Konduru, Chandra; Wood, Thomas
> Subject: [PATCH i-g-t 4/4] kms_plane_scaling: Find the image regardless h
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6319
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On ti, 2015-05-05 at 22:14 +0530, Kannan, Vandana wrote:
>
> On 5/5/2015 9:14 PM, Imre Deak wrote:
> > On ma, 2015-05-04 at 20:50 +0530, Vandana Kannan wrote:
> >> BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
> >> VCO frequencies. Program i_lockthresh in PORT_PLL_9.
>
On 5/5/2015 9:14 PM, Imre Deak wrote:
On ma, 2015-05-04 at 20:50 +0530, Vandana Kannan wrote:
BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.
VCO calculated based on the formula:
Desired Output = Port bit rate in
On ti, 2015-05-05 at 15:20 +0100, Nick Hoath wrote:
> On 29/04/2015 15:35, Deak, Imre wrote:
> > On pe, 2015-03-20 at 09:29 +, Nick Hoath wrote:
> >> This stepping isn't listed separately in the specs, so needs confirmation.
> >>
> >> Signed-off-by: Nick Hoath
> >> ---
> >> drivers/gpu/drm/i
On 1 May 2015 at 15:53, Chris Wilson wrote:
> * where is the doubly-linked circular list?
IIRC there was some patches from Jason, that move the the gallium one
to src/util/list.h [1]. Not sure on the status of it though. On a
related note - would be great if one day we nuke the glsl one
(exec_no
On 05/05/2015 11:42 AM, Daniel Vetter wrote:
> On Tue, May 05, 2015 at 10:36:24AM -0400, Peter Hurley wrote:
>> On 05/04/2015 12:52 AM, Mario Kleiner wrote:
>>> On 04/16/2015 03:03 PM, Daniel Vetter wrote:
On Thu, Apr 16, 2015 at 08:30:55AM -0400, Peter Hurley wrote:
> On 04/15/2015 01:31
On ma, 2015-05-04 at 20:50 +0530, Vandana Kannan wrote:
> BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
> VCO frequencies. Program i_lockthresh in PORT_PLL_9.
>
> VCO calculated based on the formula:
> Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz
On Tue, May 05, 2015 at 11:45:05AM +0100, Lee Jones wrote:
> This is not how we submit subsequent patch-sets.
It is unfortunately how we handle patches on dri-devel&intel-gfx to be
able to cope with massive mail load. If everyone who submits to intel-gfx
would always resend the entire series for m
On Tue, May 05, 2015 at 10:36:24AM -0400, Peter Hurley wrote:
> On 05/04/2015 12:52 AM, Mario Kleiner wrote:
> > On 04/16/2015 03:03 PM, Daniel Vetter wrote:
> >> On Thu, Apr 16, 2015 at 08:30:55AM -0400, Peter Hurley wrote:
> >>> On 04/15/2015 01:31 PM, Daniel Vetter wrote:
> On Wed, Apr 15,
On 05/04/2015 12:52 AM, Mario Kleiner wrote:
> On 04/16/2015 03:03 PM, Daniel Vetter wrote:
>> On Thu, Apr 16, 2015 at 08:30:55AM -0400, Peter Hurley wrote:
>>> On 04/15/2015 01:31 PM, Daniel Vetter wrote:
On Wed, Apr 15, 2015 at 09:00:04AM -0400, Peter Hurley wrote:
> Hi Daniel,
>
>>>
On Mon, May 04, 2015 at 09:57:17AM +0200, Daniel Vetter wrote:
> On Mon, Apr 27, 2015 at 08:33:38PM +, Konduru, Chandra wrote:
> > > -Original Message-
> > > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > > Sent: Monday, April 27, 2015 8:28 AM
> > > On Fri, Feb 20, 2015
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6318
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 29/04/2015 13:26, Deak, Imre wrote:
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i9
On Tue, 05 May 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> CPT/PPT require a specific procedure for enabling 12bpc HDMI. Implement
> it, and to keep things neat pull the code into a function.
>
> v2: Rebased due to crtc->config changes
> s/HDMI_GC/HDMIUNIT_GC/ to match
On 29/04/2015 15:35, Deak, Imre wrote:
On pe, 2015-03-20 at 09:29 +, Nick Hoath wrote:
This stepping isn't listed separately in the specs, so needs confirmation.
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
From: Ville Syrjälä
On IBX the SDVO/HDMI register write may be masked when enabling the
port, so it may need to written twice. The HDMI code does this, but
the SDVO code does not. Add the workaround to the SDVO code as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c |
From: Ville Syrjälä
Bspec says we should disable the FDI RX/TX before disabling the PCH
ports. Do so.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/g
From: Ville Syrjälä
Currently the IBX transcoder B workarounds are not working correctly.
Well, the HDMI one seems to be working somewhat, but the DP one is
definitely busted.
After a bit of experimentation it looks like the best way to make this
work is first disable the port on transcoder B, a
From: Ville Syrjälä
Follow the BSpec sequence for the CRT port as well on PCH platforms,
ie. disable the pipe before the port.
Didn't bother looking at DDI in detail yet, so leave that one be even
though the CRT is a PCH port there.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_
From: Ville Syrjälä
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
b/drivers/gpu/drm/i915/intel_sdvo.c
index 4a87691..d24ef75 100644
--- a/driver
From: Ville Syrjälä
Use POSTING_READ() in intel_sdvo_write_sdvox() as appropriate.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
b/drivers/gpu/drm/i915/intel_sdvo.c
From: Ville Syrjälä
BSpec says we should disable all ports after the pipe on PCH
platforms. Do so. Fixes a pipe off timeout on ILK now caused by
the transcoder B workaround.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_hdmi.c | 33 +
1 file change
From: Ville Syrjälä
Currently we're always enabling enhanced framing on CPT even if the sink
doesn't support it. Fix this up by actaully looking at what the sink
tells us.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 3 +--
drivers/gpu/drm/i915/intel_dp.c | 9 ++
From: Ville Syrjälä
IBX can have problems with the first write to the port register getting
masked when enabling the port. We are trying to apply the workaround
also when disabling the port where it's not needed, and we also try
to apply it for CPT/PPT as well which don't need it. Just kill it.
From: Ville Syrjälä
intel_dp.c is a mess with all the checks for different
platform/PCH variants and ports. Try to clean it up by recognizing
the following facts:
- IVB port A, and CPT port B/C/D are always the special cases
- VLV/CHV don't have port A
- Using the same kind of logic everywhere ma
From: Ville Syrjälä
Define a TRANS_DP_PIPE_TO_PORT() to make the CPT DP .get_hw_state()
pipe readout neater.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 26 +-
2 files changed, 6 insertions(+), 21 deletions(
From: Ville Syrjälä
While fixing up the 12bpc HDMI code I ran afoul of the IBX transcoder B
workaround. Turns out that's currently busted. So I fixed it, but that
caused the dreaded pipe off timeout to make a reappearance. So to fix that
I had to reorganize the crtc disable sequence to actually m
From: Ville Syrjälä
The IBX 12bpc port enable toggle is only relevant when enabling
the port, not when disabling it. Also this code doesn't actually
toggle anything, and essentially just writes the port register
one extra time. Furthermore CPT/PPT don't need such workarounds
and yet we include th
On Mon, 04 May 2015, Lukas Wunner wrote:
> Single channel LVDS maxes out at 112 MHz. The 15" pre-retina models
> shipped with 1440x900 (106 MHz) by default or 1680x1050 (119 MHz)
> as a BTO option, both versions used dual channel LVDS even though
> the smaller one would have fit into a single chan
From: Ville Syrjälä
Currently we're forgetting to double the port clock when using double
clocked modes with 12bpc on HDMI. We're only accounting for the 1.5x
factor due to the 12bpc. So further double the 1.5x port clock when we
have a double clocked mode.
Unfortunately I don't have any display
From: Ville Syrjälä
Account for the pixel multiplier when reading out the HDMI
mode dotclock. Makes the state checked happier on my ILK when using
double clocked modes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_hdmi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/dri
From: Ville Syrjälä
GCP infoframes are required to inform the HDMI sink about the color
depth.
Send the GCP infoframe whenever the sink supports any deep color modes
since such sinks must anyway be capable of receiving them. For sinks
that don't support deep color let's skip the GCP in case it m
From: Ville Syrjälä
Check that the DIP is enabled on the right port on IBX and VLV/CHV as
we're doing on g4x, and also check for all the infoframe enable bits on
all platforms.
Eventually we should track each infoframe type independently, and also
their contents. This is a small step in that dir
From: Ville Syrjälä
Our HDMI 12bpc support has always been broken. This series aims to fix that.
The problems addressed include:
- missing GCP infoframes entirely
- IBX w/a code was mostly nonsense
- missing w/a for CPT/PPT
- 12bpc vs. DBLCLK was busted
Part of this was already posted [1] quite
From: Ville Syrjälä
Follow the procedure listed in Bspec to toggle the port enable bit off
and on when enabling HDMI with 12bpc and pixel repeat on IBX. The old
code didn't actually enable the port before "toggling" the bit back off,
so the whole workaround was essentially a nop.
Also take the o
From: Ville Syrjälä
IBX BSpec says we must specify 8bpc in TRANSCONF for both 8bpc
and 12bpc HDMI output. Do so.
v2: Pass intel_crtc to intel_pipe_has_type()
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
From: Ville Syrjälä
Currently we just disable the GCP infoframe when turning off the port.
That means if the same transcoder is used on a DP port next, we might
end up pushing infoframes over DP, which isn't intended. Just disable
all the infoframes when turning off the port.
Also protect agains
From: Ville Syrjälä
When the video timings are suitably aligned so that all different
periods start at phase 0 (ie. none of the periods start mid-pixel)
we can inform the sink about this. Supposedly the sink can then
optimize certain things. Obviously this is only relevant when
outputting >8bpc d
From: Ville Syrjälä
CPT/PPT require a specific procedure for enabling 12bpc HDMI. Implement
it, and to keep things neat pull the code into a function.
v2: Rebased due to crtc->config changes
s/HDMI_GC/HDMIUNIT_GC/ to match spec better
Factor out intel_enable_hdmi_audio()
Signed-off-by:
On Tue, 05 May 2015, Damien Lespiau wrote:
> On Tue, May 05, 2015 at 02:39:48PM +0300, Jani Nikula wrote:
>> There's still the question whether we can default to using the vbt value
>> if that can be broken...
>
> This is a workaround for SDPs loaded with a "default" VBT which doesn't
> correspond
On Mon, 04 May 2015, Daniel Vetter wrote:
> On Thu, Apr 30, 2015 at 03:30:10PM -0300, Paulo Zanoni wrote:
>> 2015-04-18 4:04 GMT-03:00 Todd Previte :
>> > Updates the EDID compliance test function to perform the analyze and react
>> > to
>> > the EDID data read as a result of a hot plug event. Th
missed the changes attached. so adding rb tag
Reviewed-by: Sivakumar Thulasimani
On 5/5/2015 7:02 PM, Jani Nikula wrote:
On Tue, 05 May 2015, Sivakumar Thulasimani
wrote:
two points
1) The eDP spec says Audio is optional so it is allowed to have audio,
but i am yet to come across any eDP p
sure, you can check for port A alone then. DDI A will have edp in all
SKUs so checking for eDP should ideally be the same as DDIA.
On 5/5/2015 7:02 PM, Jani Nikula wrote:
On Tue, 05 May 2015, Sivakumar Thulasimani
wrote:
two points
1) The eDP spec says Audio is optional so it is allowed to h
On Tue, 05 May 2015, Sivakumar Thulasimani
wrote:
> two points
> 1) The eDP spec says Audio is optional so it is allowed to have audio,
> but i am yet to come across any eDP panel that supports Audio.
> 2) Also, there is no support for audio in DDI A port as well :)
>
> So please change the chec
On Tue, May 05, 2015 at 02:39:48PM +0300, Jani Nikula wrote:
> There's still the question whether we can default to using the vbt value
> if that can be broken...
This is a workaround for SDPs loaded with a "default" VBT which doesn't
correspond to the full fleet of SPDs. For actual product, it's
On Tue, May 05, 2015 at 05:12:25PM +0530, Ankitprasad Sharma wrote:
> On Wed, 2015-04-29 at 11:27 +0100, Chris Wilson wrote:
> > On Wed, Apr 29, 2015 at 03:01:59PM +0530, ankitprasad.r.sha...@intel.com
> > wrote:
> > > From: Ankitprasad Sharma
> > >
> > > This patch extends the get_aperture_ioct
On 29/04/15 23:13, yu@intel.com wrote:
> From: Alex Dai
>
> Allocate a gem obj to hold GuC log data. Also a debugfs interface
> (i915_guc_log_dump) is provided to print out the log content.
>
> Issue: VIZ-4884
> Signed-off-by: Alex Dai
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 41 +
two points
1) The eDP spec says Audio is optional so it is allowed to have audio,
but i am yet to come across any eDP panel that supports Audio.
2) Also, there is no support for audio in DDI A port as well :)
So please change the check to
if (!is_edp(encoder))
On 5/5/2015 2:39 PM, Jani Nikula
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6317
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, 2015-04-29 at 11:27 +0100, Chris Wilson wrote:
> On Wed, Apr 29, 2015 at 03:01:59PM +0530, ankitprasad.r.sha...@intel.com
> wrote:
> > From: Ankitprasad Sharma
> >
> > This patch extends the get_aperture_ioctl to add support
> > for getting total size of the stolen region and available
>
On Tue, 05 May 2015, Sonika Jindal wrote:
> This provides an option to override the value set by VBT
> for selecting edp Vswing Pre-emph setting table.
>
> https://bugs.freedesktop.org/show_bug.cgi?id=89554
> Signed-off-by: Sonika Jindal
> ---
> drivers/gpu/drm/i915/i915_drv.h|4 +++-
>
On Tue, 05 May 2015, Vandana Kannan wrote:
> Enabling BLC on BXT.
> Includes register definition, and new functions for BXT.
>
> In BXT, there are 2 sets of registers for BLC. Until there is clarity
> about which set would be effective, set 1 is being used.
> This would have to be re-visited if th
On Mon, 04 May 2015, Lukas Wunner wrote:
> Hi Ville,
>
>> I would suggest splitting that into a separate patch. Otherwise it's
>> going to harder to revert either change separately, should the need
>> arise. So that part is
>> Reviewed-by: Ville Syrjälä
>
> Okay, commit split in two as requested.
From: Akash Goel
Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per the
efficient frequency value.
Issue: VIZ-5143
Signed-off-by: Akash Goel
---
driver
From: Akash Goel
Ring frequency table programming changes for SKL. No need for a
floor on ring frequency, as the issue of performance impact with
ring running below DDR frequency, is believed to be fixed on SKL
Issue: VIZ-5144
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_pm.c | 26
This is not how we submit subsequent patch-sets.
Please submit them as a whole, seperately from the first submission
and with versioning information i.e. [PATCH v2 X/Y] Stuff ...
> In case we unload and load a driver module again that is registering a
> lookup table, without this it will result i
On Tue, 05 May 2015, Shobhit Kumar wrote:
> On 04/29/2015 07:54 PM, Lee Jones wrote:
> > On Wed, 29 Apr 2015, Shobhit Kumar wrote:
> >
> >> On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
> >> entry for the same to be used by the consumer (Intel GFX)
> >>
> >> v2: Remove t
On Mon, 2015-05-04 at 16:18 +0200, Daniel Vetter wrote:
> On Fri, Apr 24, 2015 at 11:06:10AM +0300, Mika Kahola wrote:
> > This patch adds information on current CD clock
> > frequency to debugfs i915_frequency_info
> >
> > Signed-off-by: Mika Kahola
> > ---
> > drivers/gpu/drm/i915/i915_debugfs
On Mon, 04 May 2015, Daniel Vetter wrote:
> On Tue, Apr 28, 2015 at 03:30:54PM +0300, Jani Nikula wrote:
>> Produce the intel_reg man page from rst using rst2man. Also facilitate
>> writing any man page in reStructured text, as long as rst2man is
>> available.
>>
>> v2: configure check for rst2ma
On Mon, 04 May 2015, Daniel Vetter wrote:
> On Tue, Apr 28, 2015 at 03:04:26PM +0300, Jani Nikula wrote:
>> Signed-off-by: Jani Nikula
>> ---
>> lib/intel_io.h | 4
>> lib/intel_mmio.c | 24
>> 2 files changed, 28 insertions(+)
>>
>> diff --git a/lib/intel_io.h
This provides an option to override the value set by VBT
for selecting edp Vswing Pre-emph setting table.
https://bugs.freedesktop.org/show_bug.cgi?id=89554
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/i915_drv.h|4 +++-
drivers/gpu/drm/i915/i915_params.c |7 +++
drivers
From: Tvrtko Ursulin
I think;
commit a26f9f9ad0e679c7ce413a25d34f6914e1174151
Author: chandra konduru
Date: Mon Mar 30 13:52:04 2015 -0700
i-g-t: Adding plane scaling test case
introduced a condition where it attempts to update a disabled plane because
of the newly introduce
From: Tvrtko Ursulin
There were two paths for fb and !fb.
Signed-off-by: Tvrtko Ursulin
Cc: chandra konduru
Cc: Thomas Wood
---
lib/igt_kms.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 33d437d..b5ba273 100644
--- a/lib/
From: Tvrtko Ursulin
commit a26f9f9ad0e679c7ce413a25d34f6914e1174151
Author: chandra konduru
Date: Mon Mar 30 13:52:04 2015 -0700
i-g-t: Adding plane scaling test case
Started doing this and broke kms_rotation_crc.
Signed-off-by: Tvrtko Ursulin
Cc: chandra konduru
---
From: Tvrtko Ursulin
As it stands running the test like "sudo tests/kms_plane_scaling"
does not work.
Fix it by using the same method igt_paint_image uses.
v2: Export Cairo read callback instead of duplicating it. (Thomas Wood)
Signed-off-by: Tvrtko Ursulin
Cc: chandra konduru
Cc: Thomas Woo
On 04/29/2015 07:54 PM, Lee Jones wrote:
> On Wed, 29 Apr 2015, Shobhit Kumar wrote:
>
>> On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
>> entry for the same to be used by the consumer (Intel GFX)
>>
>> v2: Remove the lookup table on driver unload (Thierry)
>>
>> CC: Samu
On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
entry for the same to be used by the consumer (Intel GFX)
v2: Remove the lookup table on driver unload (Thierry)
v3: Correct the subject line (Lee jones)
CC: Samuel Ortiz
Cc: Linus Walleij
Cc: Alexandre Courbot
Cc: Thierr
The Crystalcove PMIC controls PWM signals and this driver exports that
capability as a PWM chip driver. This is platform device implementtaion
of the drivers/mfd cell device for CRC PMIC
v2: Use the existing config callback with duty_ns and period_ns(Thierry)
v3: Correct the subject line (Lee jon
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
v2: Make the lookup table static (Thierry)
Remove the lookup table during driver remove (Thierry)
v3: Co
Needed for PWM control suuported by the PMIC
v2: Correct the subject line (Lee jones)
CC: Samuel Ortiz
Cc: Linus Walleij
Cc: Alexandre Courbot
Cc: Thierry Reding
Acked-by: Lee Jones
Signed-off-by: Shobhit Kumar
---
drivers/mfd/intel_soc_pmic_crc.c | 3 +++
1 file changed, 3 insertions(+)
In case some drivers are unloading, they can remove lookup tables which
they would have registered during their load time to avoid redundant
entries if loaded again
v2: Ccing maintainers
v3: Correct the subject line (Lee jones)
CC: Samuel Ortiz
Cc: Linus Walleij
Cc: Alexandre Courbot
Cc: Thier
In case we unload and load a driver module again that is registering a
lookup table, without this it will result in multiple entries. Provide
an option to remove the lookup table on driver unload
v2: Ccing maintainers
v3: Correct the subject line (Lee jones)
Cc: Samuel Ortiz
Cc: Linus Walleij
C
On 05/04/2015 12:51 PM, Joonas Lahtinen wrote:
On to, 2015-04-30 at 15:54 +0100, Tvrtko Ursulin wrote:
On 04/30/2015 12:21 PM, Joonas Lahtinen wrote:
Use partial view for huge BOs (bigger than the mappable aperture)
in fault handler so that they can be accessed without trying to make
room for
On Tue, 05 May 2015, Sivakumar Thulasimani
wrote:
> On 5/4/2015 7:50 PM, Jani Nikula wrote:
>> The eDP port A register on PCH split platforms has a slightly different
>> register layout from the other ports, with bit 6 being either alternate
>> scrambler reset or reserved, depending on the genera
Enabling BLC on BXT.
Includes register definition, and new functions for BXT.
In BXT, there are 2 sets of registers for BLC. Until there is clarity
about which set would be effective, set 1 is being used.
This would have to be re-visited if there is any change or when 2 LFPs are
enabled on BXT.
T
Export a set of interfaces to allow the caller to have precise control
over mapping the buffer - but still provide caching of the mmaps between
callers.
Signed-off-by: Chris Wilson
---
intel/intel_bufmgr.h | 4 ++
intel/intel_bufmgr_gem.c | 148 +
Using WAIT is preferrable to SET_DOMAIN as it doesn't have
any domain management side-effects - but has the same flushing
semantics.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
---
intel/intel_bufmgr_gem.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/intel/intel_buf
If the GPU is still processing the buffers, then keep them alive as the
pages are still pinned and hot - ripe for reuse.
Signed-off-by: Chris Wilson
---
intel/intel_bufmgr_gem.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 22f75
Convert the bo-cache into 2 phases:
1. A two second cache of recently used buffers, keep untouched.
2. A two second cache of older buffers, marked for eviction.
This helps reduce ioctl traffic on a rapid turnover in working sets. The
issue is that even a 2 second window is enough for an applicati
The kernel interface requires us to request only PAGE_SIZE aligned
buffers, so make sure that all allocation requests are indeed sized
correctly (and in the process remove the excess calls to getpagesize()).
Signed-off-by: Chris Wilson
---
intel/intel_bufmgr_gem.c | 14 --
1 file cha
Though we don't have precise tracking for when buffers in the cache list
become idle (we don't have request tracking at this layer), we do have
some basic assumptions that the head is inactive and the tail active. So
when inserting buffers in the cache, it would be good not to completely
ignore tho
[ 1572.417121] BUG: unable to handle kernel NULL pointer dereference at
(null)
[ 1572.421010] IP: [] ftrace_raw_event_i915_context+0x5d/0x70
[i915]
[ 1572.424970] PGD 1766a3067 PUD 1767a2067 PMD 0
[ 1572.428892] Oops: [#1] SMP
[ 1572.432787] Modules linked in: ipv6 dm_mod iTCO_wdt
On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote:
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote:
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote:
On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote:
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepa...@linux.in
I agree Daniel. We need two patches here, 1) moving the enabling of the
interrupts early on. 2) split the WA initialization into GT & Display and move
GT workarounds before ring init.
Thanks
Deepak
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Dan
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