When we have bound vma into an address space, the layout
of page table structures is immutable. So we can be absolutely
certain that if vma is already bound, there is no need to
(re)allocate a virtual address range for it.
v2: - add sanity checks and remove superfluous GLOBAL_BIND set
- we mig
Reviewed-by: Sivakumar Thulasimani
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
V4:
- when HPD long pulse is received, the flag is cleared
that indicates if DP link training is r
Reviewed-by: Sivakumar Thulasimani
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.
In ca
This is patch series optimizes DP link training by reusing
the link parameter settings if DP link has bee previously
trained. In case we are not able to train the link by reusing
the known values, the link training parameters are set
to zero and training is restarted.
The first patch is for eDP on
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.
In case we are not able to train the link by reusing
the known values, the link traini
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
V4:
- when HPD long pulse is received, the flag is cleared
that indicates if DP link training is required or not
(based on Sivakumar's comment)
Signed-off-by: Mika Kahola
---
Commit c9f038a1a592 ("drm/i915: Don't assume primary & cursor are
always on for wm calculation (v4)") fixes a null pointer dereference.
Setting the primary and cursor panes to false in
ilk_compute_wm_parameters to false does however give the following
errors in the kernel log and causes the screen
Thomas Gummerer writes:
> Commit c9f038a1a592 ("drm/i915: Don't assume primary & cursor are
> always on for wm calculation (v4)") fixes a null pointer dereference.
> Setting the primary and cursor panes to false in
> ilk_compute_wm_parameters to false does however give the following
> errors in t
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
v3: Updated bias setting for chv (Deepak)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 12 +
From: Deepak S
After feedback from the hardware team, now we set the GPU min/idel freq to RPe.
Punit is expecting us to operate GPU between Rpe & Rp0. If we drop the
frequency to RPn, punit is failing to change the input voltage to
minimum :(
Since Punit validates the rps range [RPe, RP0]. This
From: Deepak S
Based on the spec, Setting up static BIAS for GPU to improve the
rps performace.
v2: rename reg defn to match spec. (Ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 12
2 files changed, 17 insertions(
On Wednesday 29 April 2015 12:02 AM, Ville Syrjälä wrote:
On Tue, Apr 28, 2015 at 11:16:29AM -0700, Jesse Barnes wrote:
On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote:
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN.
On Tuesday 28 April 2015 11:46 PM, Jesse Barnes wrote:
Yeah I think this is fine (may need a rebase though, you can keep my r-b
if you do that in case Jani doesn't want to deal with the merge conflicts).
Reviewed-by: Jesse Barnes
Sure Jesse, I will rebase the patch.
Thanks
Deepak
___
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/i915_drv.c between commit 5df0582bf036
("drm/i915/vlv: remove wait for previous GFX clk disable request") from
Linus' tree and commit 85250ddff7a6 ("drm/i915/chv: Remove Wait for a
previous gfx force-off"
On Tue, Apr 28, 2015 at 11:16:29AM -0700, Jesse Barnes wrote:
> On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote:
> > From: Deepak S
> >
> > When GPU is idle on VLV, Request freq to punit should be good enough to
> > get the voltage back to VNN. Also, make sure gfx clock force applies
> > b
On 03/04/2015 08:08 PM, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> When GPU is idle on VLV, Request freq to punit should be good enough to
> get the voltage back to VNN. Also, make sure gfx clock force applies
> before requesting the freq fot vlv.
>
> Bugzilla: https://bugs.freedesktop
On 17/04/15 22:21, yu@intel.com wrote:
> From: Sagar Kamble
>
> The firmware loader will use GuC DMA engine to move data from
> ggtt to WOPCM. Need to take forcewake before GuC loading.
>
> Issue: VIZ-4884
> Change-Id: Ie422fc1e122933b161ff63cab23622197e6bba54
> Signed-off-by: Sagar Kamble
On 04/28/2015 08:12 AM, Dave Gordon wrote:
On 23/04/15 18:48, Dave Gordon wrote:
> On 17/04/15 22:21, yu@intel.com wrote:
>> From: Alex Dai
>>
>> Add GuC firmware loader. It uses the unified firmware loader to
>> fetch firmware blob first, then load to hw in driver main thread.
>>
>> Issue
On 23/04/15 18:48, Dave Gordon wrote:
> On 17/04/15 22:21, yu@intel.com wrote:
>> From: Alex Dai
>>
>> Add GuC firmware loader. It uses the unified firmware loader to
>> fetch firmware blob first, then load to hw in driver main thread.
>>
>> Issue: VIZ-4884
>> Signed-off-by: Alex Dai
>> ---
>
On Tue, Apr 28, 2015 at 05:56:17PM +0300, Mika Kuoppala wrote:
> When we have bound vma into an address space, the layout
> of page table structures is immutable. So we can be absolutely
> certain that if vma is already bound, there is no need to
> (re)allocate a virtual address range for it.
>
>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6277
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 28/04/15 10:21, Dave Gordon wrote:
> On 24/04/15 06:52, Antoine, Peter wrote:
>> I picked up this work due to the following Jira ticket created by the
>> security team (on Android) and was asked to give it a second look and
>> found a few more issues with the hw lock code.
>>
>> https://jira01.d
When we have bound vma into an address space, the layout
of page table structures is immutable. So we can be absolutely
certain that if vma is already bound, there is no need to
(re)allocate a virtual address range for it.
v2: - add sanity checks and remove superfluous GLOBAL_BIND set
- we mig
On Tue, Apr 28, 2015 at 02:38:25PM +, Antoine, Peter wrote:
> So is the plan to push these patches and have follow-on work to cover the
> other paths?
> As this fixes the Bugzilla issue that has been raised.
You've identified an issue, but I think your patch is incomplete.
-Chris
--
Chris W
On to, 2015-04-16 at 14:22 +0530, Animesh Manna wrote:
> [...]
> +
> +#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
Animesh, does this firmware loading patchset work with skl_dmc_ver4.bin?
If so please re-send this patch with the above pointing to
i915/skl_dmc_ver4.bin (since that is the published
On Thu, 16 Apr 2015, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> This WA is avoid problem between shadow vs wake FIFO unload
> problem during CPD/RC6 transactions on CHV.
>
> v2: Define individual bits GTFIFOCTL (Ville)
>
> v3: move WA to uncore_early_sanitize (ville)
>
> Signed-off-by: D
So is the plan to push these patches and have follow-on work to cover the other
paths?
As this fixes the Bugzilla issue that has been raised.
Peter.
-Original Message-
From: Deepak S [mailto:deepa...@linux.intel.com]
Sent: Tuesday, April 28, 2015 9:56 AM
To: Chris Wilson; S, Deepak; Ant
From: Tvrtko Ursulin
New subtests to excercise flips from tiled to tiled and from
linear to tiled frame buffers.
These will catch display programming issues like not preserving the
tiling mode in page flips or not re-programming the watermarks.
v2: Cleanup crc object after failing subtests.
v3
On Tue, 28 Apr 2015, han...@intel.com wrote:
> From: "Lu, Han"
>
> In SKL, HDMI/DP codec and PCH HD Audio Controller are in different
> power wells, so it's necessary to reset display audio codecs when
> power well on, otherwise display audio codecs will disappear when
> resume from low power stat
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6275
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Tue, 2015-04-28 at 16:08 +0300, Ville Syrjälä wrote:
> On Tue, Apr 28, 2015 at 11:29:06AM +, Antoine, Peter wrote:
> > > > > diff --git a/include/drm/drmP.h b/include/drm/drmP.h index
> > > > > 62c40777..367e42f 100644
> > > > > --- a/include/drm/drmP.h
> > > > > +++ b/include/drm/drmP.h
>
On Tue, Apr 28, 2015 at 11:29:06AM +, Antoine, Peter wrote:
> > > > diff --git a/include/drm/drmP.h b/include/drm/drmP.h index
> > > > 62c40777..367e42f 100644
> > > > --- a/include/drm/drmP.h
> > > > +++ b/include/drm/drmP.h
> > > > @@ -137,17 +137,18 @@ void drm_err(const char *format, ...);
On Tue, Apr 28, 2015 at 01:46:23PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Measures DRM_IOCTL_MODE_SETCRTC and DRM_IOCTL_MODE_SETPLANE as proxy for
> drm_atomic_helper_update_plane if I got it right.
>
> Discovered some slow cursor updates (1.6ms) so needed something to test
> di
From: Tvrtko Ursulin
Measures DRM_IOCTL_MODE_SETCRTC and DRM_IOCTL_MODE_SETPLANE as proxy for
drm_atomic_helper_update_plane if I got it right.
Discovered some slow cursor updates (1.6ms) so needed something to test
different kernel configs etc.
v2:
* Move to a test case and fail if ioctl ta
Produce the intel_reg man page from rst using rst2man. Also facilitate
writing any man page in reStructured text, as long as rst2man is
available.
v2: configure check for rst2man, credits to Thomas Wood for that.
Signed-off-by: Jani Nikula
---
README| 1 +
configure.ac | 3
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6274
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6273
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
igfx_get_mmio() uses the global mmio variable by accident. Use a local
variable instead.
The intention is to rename the global variable later on, so shadowing it
here does not matter.
Signed-off-by: Jani Nikula
---
tests/gen7_forcewake_mt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/te
Global variable names should reflect the fact that they are indeed
global, and at the very least they should not be as short as just
"mmio". Rename mmio to igt_global_mmio.
Signed-off-by: Jani Nikula
---
lib/intel_io.h | 2 +-
lib/intel_mmio.c | 44 +---
Use INREG and OUTREG instead of using mmio directly.
Signed-off-by: Jani Nikula
---
tools/intel_vga_read.c | 2 +-
tools/intel_vga_write.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/intel_vga_read.c b/tools/intel_vga_read.c
index e635c59cda3b..ea5070577a1e 1006
Use INREG instead of using mmio directly.
Signed-off-by: Jani Nikula
---
tools/intel_reg_checker.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c
index 22d979613ea1..2d6da70c3afa 100644
--- a/tools/intel_reg_checke
Use INREG instead of using mmio directly.
Signed-off-by: Jani Nikula
---
tools/intel_watermark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index e5dee46db78f..0b7c5e5193ef 100644
--- a/tools/intel_watermark.c
+++ b/tools
Use INREG and OUTREG instead of using mmio directly.
Signed-off-by: Jani Nikula
---
tools/intel_display_poller.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
index 2eab6c494f68..6d6ea21ca974 100644
--- a/t
Use INREG and OUTREG instead of using mmio directly.
Signed-off-by: Jani Nikula
---
tools/intel_reg_read.c | 5 ++---
tools/intel_reg_write.c | 8 +++-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c
index 3b9129148878..46fa664b
Signed-off-by: Jani Nikula
---
lib/intel_io.h | 4
lib/intel_mmio.c | 24
2 files changed, 28 insertions(+)
diff --git a/lib/intel_io.h b/lib/intel_io.h
index 04aa3fd496b4..1c3b4445cd5b 100644
--- a/lib/intel_io.h
+++ b/lib/intel_io.h
@@ -43,7 +43,11 @@ void inte
First reduce to use of the mmio global variable by switching to INREG
and OUTREG, and finally rename mmio to igt_global_mmio.
BR,
Jani.
Jani Nikula (10):
lib: add 16 and 8 bit versions of INREG and OUTREG
intel_reg: switch to INREG and OUTREG
intel_backlight: switch to INREG and OUTREG
i
Use INREG and OUTREG instead of using mmio directly.
Signed-off-by: Jani Nikula
---
tools/intel_backlight.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/tools/intel_backlight.c b/tools/intel_backlight.c
index 17deb88d4be8..067fd4180968 100644
--- a/to
Use INREG and OUTREG instead of using mmio directly.
Signed-off-by: Jani Nikula
---
tools/intel_reg.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/tools/intel_reg.c b/tools/intel_reg.c
index 975529d4555b..0f98266932e5 100644
--- a/tools/intel_reg.c
+++ b/tools/i
reply at end.
On Tue, 2015-04-28 at 13:40 +0300, Ville Syrjälä wrote:
> On Tue, Apr 28, 2015 at 05:52:20AM +, Antoine, Peter wrote:
> > Hi,
> >
> > (replies inline)
> >
> > -Original Message-
> > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> > Sent: Monday, April 27,
From: Tvrtko Ursulin
commit a26f9f9ad0e679c7ce413a25d34f6914e1174151
Author: chandra konduru
Date: Mon Mar 30 13:52:04 2015 -0700
i-g-t: Adding plane scaling test case
Started doing this and broke kms_rotation_crc.
Signed-off-by: Tvrtko Ursulin
Cc: chandra konduru
---
From: Tvrtko Ursulin
I think;
commit a26f9f9ad0e679c7ce413a25d34f6914e1174151
Author: chandra konduru
Date: Mon Mar 30 13:52:04 2015 -0700
i-g-t: Adding plane scaling test case
introduced a condition where it attempts to update a disabled plane because
of the newly introduce
In ancient pre-KMS times, I was able to get a particular pineview-based
(Atom D525) desktop computer & monitor to run at decent resolutions.
Recently, I have tried the 2.99.917 snapshot, and the best I can
manage is 1024x768.
Bad parts of the system are:
- the monitor's EDID is invalid
- it presen
On Monday 13 April 2015 05:40 PM, Ville Syrjälä wrote:
On Mon, Apr 13, 2015 at 02:55:12PM +0300, Jani Nikula wrote:
On Thu, 05 Mar 2015, deepa...@linux.intel.com wrote:
From: Deepak S
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also,
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6272
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Tue, Apr 28, 2015 at 05:52:20AM +, Antoine, Peter wrote:
> Hi,
>
> (replies inline)
>
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Monday, April 27, 2015 6:04 PM
> To: Antoine, Peter
> Cc: intel-gfx@lists.freedesktop.org; airl...@redhat
From: "Lu, Han"
In SKL, HDMI/DP codec and PCH HD Audio Controller are in different
power wells, so it's necessary to reset display audio codecs when
power well on, otherwise display audio codecs will disappear when
resume from low power state.
The reset step when power on is:
enable codec wak
From: "Lu, Han"
In SKL, HDMI/DP codec and PCH HD Audio Controller are in different
power wells, so it's necessary to reset display audio codecs when
power well on, otherwise display audio codecs will disappear when
resume from low power state.
The reset step when power on is:
enable codec wak
On Tue, 2015-04-28 at 15:18 +0530, Sivakumar Thulasimani wrote:
> On 4/28/2015 3:12 PM, Mika Kahola wrote:
> > On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote:
> >>
> >> On 4/28/2015 1:44 PM, Mika Kahola wrote:
> >>> On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
> >
On Tue, Apr 28, 2015 at 10:21:49AM +0100, Dave Gordon wrote:
> On 24/04/15 06:52, Antoine, Peter wrote:
> > I picked up this work due to the following Jira ticket created by the
> > security team (on Android) and was asked to give it a second look and
> > found a few more issues with the hw lock co
On Tue, Apr 28, 2015 at 09:28:51AM +, Antoine, Peter wrote:
> Also, the PARAM should give legitimate code the opportunity to avoid the
> problems but avoiding these features completely.
There are no legitimate users.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
On 4/28/2015 3:12 PM, Mika Kahola wrote:
On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote:
On 4/28/2015 1:44 PM, Mika Kahola wrote:
On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
On 4/28/2015 12:13 PM, Mika Kahola wrote:
This patch adds DP link training optimiz
There are several issues with the hardware locks functions that stretch
from kernel crashes to priority escalations. This new test will test the
the fixes for these features.
This test will cause a driver/kernel crash on un-patched kernels, the
following patches should be applied to stop the crash
On Tue, 2015-04-28 at 13:51 +0530, Sivakumar Thulasimani wrote:
>
>
> On 4/28/2015 1:44 PM, Mika Kahola wrote:
> > On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
> >> On 4/28/2015 12:13 PM, Mika Kahola wrote:
> >>> This patch adds DP link training optimization by reusing the
> >>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6271
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6271
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Mon, 2015-04-27 at 16:33 +0100, Chris Wilson wrote:
> On Mon, Apr 27, 2015 at 04:24:37PM +0100, Thomas Wood wrote:
> > On 23 April 2015 at 15:07, Peter Antoine wrote:
> > > There are several issues with the hardware locks functions that stretch
> > > from kernel crashes to priority escalations.
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6271
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6271
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Tue, Apr 28, 2015 at 10:18:53AM +0100, Tvrtko Ursulin wrote:
> On 04/27/2015 10:20 PM, Chris Wilson wrote:
> >Same comment for commit = COMMIT_LEGACY here, mainly now for consistency
> >with before.
>
> Here we want to be able to choose between commit types if we want to
> keep two subtests.
I
On 24/04/15 06:52, Antoine, Peter wrote:
> I picked up this work due to the following Jira ticket created by the
> security team (on Android) and was asked to give it a second look and
> found a few more issues with the hw lock code.
>
> https://jira01.devtools.intel.com/browse/GMINL-5388
> I/O co
On 04/27/2015 10:20 PM, Chris Wilson wrote:
On Mon, Apr 27, 2015 at 04:34:05PM +0100, Tvrtko Ursulin wrote:
+static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe,
+igt_plane_t *plane)
+{
+ drmModeModeInfo *mode;
+ igt_display_t *display
Yes agreed, we need to make changes in other paths :)
On Tuesday 28 April 2015 02:14 PM, Chris Wilson wrote:
On Tue, Apr 28, 2015 at 08:29:13AM +, S, Deepak wrote:
Thanks Chirs for review, We moved "Init_hw" to initialize WA's before any BB
submission.
Init_hw calls " init_clock_gating"
On Tue, Apr 28, 2015 at 08:29:13AM +, S, Deepak wrote:
> Thanks Chirs for review, We moved "Init_hw" to initialize WA's before any BB
> submission.
>
> Init_hw calls " init_clock_gating"
But you appreciate the same issue exists on other paths?
-Chris
--
Chris Wilson, Intel Open Source Te
Thanks for the review, new patch inbound.
-Original Message-
From: Thomas Wood [mailto:thomas.w...@intel.com]
Sent: Monday, April 27, 2015 4:25 PM
To: Antoine, Peter
Cc: Intel Graphics Development; airl...@redhat.com;
dri-de...@lists.freedesktop.org; Daniel Vetter
Subject: Re: [Intel-gfx
On 04/27/2015 03:50 PM, Tvrtko Ursulin wrote:
+for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
+view->params.partial.offset)
+{
+if (st->nents >= view->params.partial.size)
+break;
+
+sg_set_page(sg, NULL, PAGE_SIZE, 0);
+sg_
Thanks Chirs for review, We moved "Init_hw" to initialize WA's before any BB
submission.
Init_hw calls " init_clock_gating"
Thanks
Deepak
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Tuesday, April 28, 2015 12:53 PM
To: Antoine, Peter
Cc: intel-gfx@li
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6262
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 4/28/2015 1:44 PM, Mika Kahola wrote:
On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
On 4/28/2015 12:13 PM, Mika Kahola wrote:
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
Signed-off-by: Mika Kahola
On Tue, 2015-04-28 at 13:19 +0530, Sivakumar Thulasimani wrote:
>
> On 4/28/2015 12:13 PM, Mika Kahola wrote:
> > This patch adds DP link training optimization by reusing the
> > previously trained values.
> >
> > v2:
> > - rebase
> >
> > V3:
> > - rebase
> >
> > Signed-off-by: Mika Kahola
> > --
On 4/28/2015 12:13 PM, Mika Kahola wrote:
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
V3:
- rebase
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
This is the wrong layer to apply an arbitrary restriction and the wrong
error code (object too large!). If we do want to prevent large offsets
being return to the user on 32bit systems (to hide bugs in userspace),
you want to restrict the drm_mm range manager instead. This first tells
userspace abo
On 24/04/15 17:18, Marc MERLIN wrote:
> On Fri, Apr 24, 2015 at 04:53:53PM +0100, Chris Wilson wrote:
>> Whether of not it tears depends upon your window manager. On bare X,
>> using mplayer -vo xv or -vo gl, should not tear. Under a compositing
>> window manager, it depends upon how it decides to
On Tue, Apr 28, 2015 at 08:18:14AM +0100, Peter Antoine wrote:
> This patch fixed a timing issue that causes a GPU hang when a the system
> comes out of power saving.
>
> During pm_resume, We are submitting batchbuffers before enabling Interrupts
> this is causing us to miss the context switch int
On ma, 2015-04-27 at 14:55 +0100, Tvrtko Ursulin wrote:
> Hi,
>
> On 04/24/2015 01:09 PM, Joonas Lahtinen wrote:
> >
> > GGTT VMA sizes might be smaller than the whole object size due to
> > different GGTT views.
> >
> > v2:
> > - Separate GGTT view constraint calculations from normal view
> >
This patch fixed a timing issue that causes a GPU hang when a the system
comes out of power saving.
During pm_resume, We are submitting batchbuffers before enabling Interrupts
this is causing us to miss the context switch interrupt, and in consequence
intel_execlists_handle_ctx_events is not trigg
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