Re: [Intel-gfx] Intel-gfx Digest, Vol 86, Issue 409

On Thu, Mar 26, 2015 at 12:44:19PM -0700, intel-gfx-requ...@lists.freedesktop.org wrote: > Send Intel-gfx mailing list submissions to > intel-gfx@lists.freedesktop.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://lists.freedesktop.org/mailman/listinfo/intel-g

Re: [Intel-gfx] [PATCH v3 15/15] Documentation/drm: kerneldoc for GuC

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6226 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

[Intel-gfx] [PATCH i-g-t] tests/tools_test: Find tools in source or installed locations

Signed-off-by: Mike Mason --- tests/tools_test | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/tools_test b/tests/tools_test index 8bda263..a6178e1 100755 --- a/tests/tools_test +++ b/tests/tools_test @@ -6,9 +6,9 @@ SOURCE_DIR="$( dirname "${BASH_SOURCE[0]}" )" .

[Intel-gfx] [PATCH v3 15/15] Documentation/drm: kerneldoc for GuC

From: Alex Dai Add overview design of GuC, plus some key points related to the implementation. Signed-off-by: Alex Dai --- Documentation/DocBook/drm.tmpl | 19 +++ 1 file changed, 19 insertions(+) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl ind

[Intel-gfx] [PATCH v3 09/15] drm/i915: Integration of GuC client

From: Alex Dai Implementation of GuC client. A GuC client has its own doorbell and workqueue. It maintains the doorbell cache line, process description object and work queue item. A default guc_client is created to do the in-order legacy execlist submission. Issue: VIZ-4884 Signed-off-by: Alex

[Intel-gfx] [PATCH v3 07/15] drm/i915: Add functions to allocate / release gem obj for GuC

From: Alex Dai All gem objects used by GuC are pinned to ggtt space out of range [0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is used internally for its Boot ROM, SRAM etc. Currently this WPOCM size is 512K. This is done by using of PIN_OFFSET_BIAS. Issue: VIZ-4884 Signed-off-b

[Intel-gfx] [PATCH v3 12/15] drm/i915: debugfs of GuC status

From: Alex Dai Now print out Bootrom, uKernel and MIA Core status. The scratch reg 0 & 15 are used for communication between driver and firmware. Their status is also printed out. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_debugfs.c | 79 +

[Intel-gfx] [PATCH v3 06/15] drm/i915: Move execlists defines from .c to .h

From: "Michael H. Nguyen" Move defines from intel_lrc.c to i915_reg.h so they are accessible by the guc files Issue: VIZ-4884 Signed-off-by: Michael H. Nguyen --- drivers/gpu/drm/i915/i915_reg.h | 77 drivers/gpu/drm/i915/intel_lrc.c | 76 -

[Intel-gfx] [PATCH v3 14/15] drm/i915: Taking forcewake during GuC load.

From: Sagar Kamble The firmware loader will use GuC DMA engine to move data from ggtt to WOPCM. Need to take forcewake before GuC loading. Issue: VIZ-4884 Change-Id: Ie422fc1e122933b161ff63cab23622197e6bba54 Signed-off-by: Sagar Kamble --- drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++ 1 fil

[Intel-gfx] [PATCH v3 13/15] drm/i915: Enable GuC firmware log

From: Alex Dai Allocate a gem obj to hold GuC log data. Also a debugfs interface (i915_guc_log_dump) is provided to print out the log content. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_debugfs.c | 29 +++ drivers/gpu/drm/i915/i915_drv.h | 1

[Intel-gfx] [PATCH v3 05/15] drm/i915: Defer default hardware context initialisation until first open

From: Dave Gordon In order to fully initialise the default contexts, we have to execute batchbuffer commands on the GPU engines. But we can't do that until any required firmware has been loaded, which may not be possible during driver load, because the filesystem(s) containing the firmware may no

[Intel-gfx] [PATCH v3 10/15] drm/i915: Interrupt routing for GuC scheduler

From: Alex Dai Turn on interrupt steering to route necessary interrupts to GuC. Issue: VIZ-4884 Signed-off-by: Dave Gordon Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_reg.h| 11 -- drivers/gpu/drm/i915/intel_guc.h | 7 drivers/gpu/drm/i915/intel_guc_s

[Intel-gfx] [PATCH v3 00/15] *** Command submission via GuC for SKL ***

From: Alex Dai v3: a) Fix regressions found in igt. The debugfs entries for GuC should not be avaliable for no-GuC platform. b) Firmware name is changed to _guc_ver.bin. In this way, end user can roll back to old kernel without knowledge of which version firmware is needed by kernel, as

[Intel-gfx] [PATCH v3 11/15] drm/i915: Enable commands submission via GuC

From: Alex Dai Add functions to submit work queue item and ring the door bell. GuC TLB needs to be invalided if LRC context changes. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/intel_guc.h| 3 + drivers/gpu/drm/i915/intel_guc_client.c | 198 ++

[Intel-gfx] [PATCH v3 03/15] drm/i915: Unified firmware loading mechanism

From: Dave Gordon Factor out the common code of loading firmware into a new file, leaving only the uC-specific parts in the GuC loaders. Issue: VIZ-4884 Signed-off-by: Alex Dai Signed-off-by: Dave Gordon --- drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/intel_uc_loader.

[Intel-gfx] [PATCH v3 08/15] drm/i915: Functions to support command submission via GuC

From: Alex Dai To enable GuC command submission / scheduling, we need to setup firmware initializaion properly. i915.enable_guc_scheduling is introduced to enable / disable GuC submission. GuC firmware uses the one page after Ring Context as shared data. However, GuC uses same offset to address

[Intel-gfx] [PATCH v3 01/15] drm/i915: Add guc firmware interface headers

From: Alex Dai These are the subset of GuC interface that we are going to use to enable command submission through GuC. The definition of these struct and bit setting need to match those in firmware. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/intel_guc_api.h | 217 +++

[Intel-gfx] [PATCH v3 02/15] drm/i915: Add i915_gem_object_write() to i915_gem.c

From: "Michael H. Nguyen" i915_gem_object_write() is a generic function to copy data from user memory to gem object. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_gem.c | 30 ++ 2 files changed, 33 in

[Intel-gfx] [PATCH v3 04/15] drm/i915: GuC firmware loader

From: Alex Dai Add GuC firmware loader. It uses the unified firmware loader to fetch firmware blob first, then load to hw in driver main thread. Issue: VIZ-4884 Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_dma.c | 6 + driver

Re: [Intel-gfx] [RFC, 1/4] drm/i915: Convert requests to use struct fence

On 07/04/15 12:18, Maarten Lankhorst wrote: > Hey, > > Op 07-04-15 om 12:59 schreef John Harrison: >> On 07/04/2015 10:18, Maarten Lankhorst wrote: >>> Hey, >>> >>> Op 20-03-15 om 18:48 schreef john.c.harri...@intel.com: From: John Harrison There is a construct in the linux kernel

Re: [Intel-gfx] [RFC 2/4] drm/i915: Removed now redudant parameter to i915_gem_request_completed()

On 20/03/15 17:48, john.c.harri...@intel.com wrote: > From: John Harrison > > The change to the implementation of i915_gem_request_completed() means that > the > lazy coherency flag is no longer used. This can now be removed to simplify the > interface. > > For: VIZ-5190 > Signed-off-by: John H

Re: [Intel-gfx] [PATCH] igt/dp: Displayport Compliance Testing - Userspace Component

On 4/17/2015 11:42 AM, Dave Gordon wrote: On 10/04/15 16:54, Todd Previte wrote: This is the userspace component of the Displayport compliance testing software requried for compliance testing of the i915 driver. The README included in the dp_compliance/ directory contains the most up to date i

Re: [Intel-gfx] [PATCH] igt/dp: Displayport Compliance Testing - Userspace Component

On 10/04/15 16:54, Todd Previte wrote: > This is the userspace component of the Displayport compliance testing > software requried for compliance testing of the i915 driver. The README > included in the dp_compliance/ directory contains the most up to date > information on the use and operation of

Re: [Intel-gfx] [PATCH 10/17] drm/i915: Remove misleading comment around bind_to_vm

Daniel Vetter writes: > It's true that we might need to context switch, but both the signalling > and implementation of the same are a few source files away. Remove it. > > Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem.c | 4 > 1 file chan

Re: [Intel-gfx] [PATCH] igt/dp: Displayport Compliance Testing - Userspace Component

On 4/17/2015 6:44 AM, Thomas Wood wrote: On 10 April 2015 at 16:54, Todd Previte wrote: This is the userspace component of the Displayport compliance testing software requried for compliance testing of the i915 driver. The README included in the dp_compliance/ directory contains the most up t

Re: [Intel-gfx] [PATCH 09/17] drm/i915: Don't use atomics for pg_dirty_rings

Daniel Vetter writes: > It's already protected by the bkl^Wdev->struct_mutex. While at it > realign some related code. > > Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem_context.c| 16 > drivers/gpu/drm/i915/i915_gem_execbuf

[Intel-gfx] [PATCH v2 2/2] drm/i915: fix intel_prepare_ddi

At the moment intel_prepare_ddi buffer will iterate through both MST and CRT encoders, which is incorrect. Neither of these encoder types have an embedding intel_digital_port object, so for these encoder types we will use random data when dereferencing the corresponding intel_digital_port->port fie

[Intel-gfx] [PATCH v2 1/2] drm/i915: factor out ddi_get_encoder_port

In the next patch we'll need to get at both the encoder's intel_digital_port object - which maybe NULL for a CRT - and it's port, so factor out this functionality. No functional change. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90067 Signed-off-by: Imre Deak --- drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH] drm/i915: fix for_each_digital_port

On pe, 2015-04-17 at 09:36 -0300, Paulo Zanoni wrote: > 2015-04-17 8:58 GMT-03:00 Imre Deak : > > We should check if a given encoder is of a digital type before casting > > it to a digital port object. This broke on HSW when iterating the VGA > > encoder. > > > > Introduced in > > commit b403745c84

Re: [Intel-gfx] [PATCH 05/17] drm/i915: Move PTE_READ_ONLY to ->pte_encode vfunc

Daniel Vetter writes: > It's only used as a flag there, so unconfuse things a bit. > Also separate the bind_vma flag space from the pte_encode flag > space in the code. > > Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +-

Re: [Intel-gfx] [PATCH 04/17] drm/i915: Unify aliasing ppgtt handling

Daniel Vetter writes: > With the dynamic pagetable alloc code aliasing ppgtt special-cases > where again mixed in all over the place with the low-level init code. > > Extract the va preallocation and clearing again into the common code > where aliasing ppgtt gets set up. > > Note that with this w

Re: [Intel-gfx] [PATCH] drm/i915: Fixup kerneldoc for struct intel_context

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6222 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

Re: [Intel-gfx] [PATCH 1/2] drm/i915: do not clear mappings beyond VMA size

On Fri, Apr 17, 2015 at 04:59:46PM +0300, Joonas Lahtinen wrote: > Do not to clear mappings outside the allocated VMA under any > circumstances. Only clear the smaller of VMA or object page count. > > This is required to allow creating partial object VMAs which in > turn are needed for partial GGT

Re: [Intel-gfx] [PATCH 2/2] drm/i915: do not make assumptions on GGTT VMA sizes

On Fri, Apr 17, 2015 at 05:00:07PM +0300, Joonas Lahtinen wrote: > GGTT VMA sizes might be smaller than the whole object size due to > different GGTT views. > > Signed-off-by: Joonas Lahtinen > --- > drivers/gpu/drm/i915/i915_gem.c | 32 +++- > drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH 03/17] drm/i915: Clean up aliasing ppgtt correctly on error paths

Daniel Vetter writes: > While at it inline the free functions - they don't actually free the > ppgtt, just clean up the allocations done for it. > > Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 30 ++ > 1 fi

Re: [Intel-gfx] [PATCH 02/17] drm/i915: Move vma vfuns to adddress_space

Daniel Vetter writes: > They change with the address space and not with each vma, so move them > into the right pile of vfuncs. Save 2 pointers per vma and clarifies > the code. > > Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem.c | 2 +- >

Re: [Intel-gfx] [PATCH 01/17] drm/i915: Move gen8 clear_range vfunc setup into common code

Daniel Vetter writes: > Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 9041f3df

Re: [Intel-gfx] [PATCH] drm/i915: Fix view type in warning message

On to, 2015-04-16 at 10:13 +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > One month passed between posting a patch and it getting merged, and > unfortunately even though it still applies, it needs fixing to account > for changes in function parameters since: > >commit d385612e15b8b6

[Intel-gfx] [PATCH 2/2] drm/i915: do not make assumptions on GGTT VMA sizes

GGTT VMA sizes might be smaller than the whole object size due to different GGTT views. Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem.c | 32 +++- drivers/gpu/drm/i915/i915_gem_gtt.c | 23 +++ drivers/gpu/drm/i915/i915_gem_gt

[Intel-gfx] [PATCH 1/2] drm/i915: do not clear mappings beyond VMA size

Do not to clear mappings outside the allocated VMA under any circumstances. Only clear the smaller of VMA or object page count. This is required to allow creating partial object VMAs which in turn are needed for partial GGTT views. Signed-off-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_ge

Re: [Intel-gfx] [PATCH 08/17] drm/i915: Don't look at pg_dirty_rings for aliasing ppgtt

Daniel Vetter writes: > On Tue, Apr 14, 2015 at 06:53:41PM +0100, Chris Wilson wrote: >> On Tue, Apr 14, 2015 at 07:11:25PM +0200, Daniel Vetter wrote: >> > On Tue, Apr 14, 2015 at 05:06:36PM +0100, Chris Wilson wrote: >> > > On Tue, Apr 14, 2015 at 05:35:18PM +0200, Daniel Vetter wrote: >> > > >

Re: [Intel-gfx] [PATCH] igt/dp: Displayport Compliance Testing - Userspace Component

On 10 April 2015 at 16:54, Todd Previte wrote: > This is the userspace component of the Displayport compliance testing > software requried for compliance testing of the i915 driver. The README > included in the dp_compliance/ directory contains the most up to date > information on the use and oper

Re: [Intel-gfx] [PATCH 04/17] drm/i915: Unify aliasing ppgtt handling

Daniel Vetter writes: > With the dynamic pagetable alloc code aliasing ppgtt special-cases > where again mixed in all over the place with the low-level init code. > > Extract the va preallocation and clearing again into the common code > where aliasing ppgtt gets set up. > > Note that with this w

[Intel-gfx] [PATCH] Enable dithering for NS 2501 DVO

Hi Daniel, hi Ville, did you get this? Greetings, Thomas Signed-off-by: Thomas Richter This patch enables the (unfortunately undocumented) scaler of the NatSemi 2501 DVO found in the Fujitsu-Siemens S6010 laptop and other machines of the same series and age. Parts of the DVO scaler logic

[Intel-gfx] [PATCH v5 2/2] drm/i915/skl: Add DC5 Trigger Sequence

From: Suketu Shah Add triggers as per expectations mentioned in gen9_enable_dc5 and gen9_disable_dc5 patch. Also call POSTING_READ for every write to a register to ensure that its written immediately. v1: Remove POSTING_READ calls as they've already been added in previous patches. v2: Rebase t

Re: [Intel-gfx] [PATCH] drm/i915: fix for_each_digital_port

2015-04-17 8:58 GMT-03:00 Imre Deak : > We should check if a given encoder is of a digital type before casting > it to a digital port object. This broke on HSW when iterating the VGA > encoder. > > Introduced in > commit b403745c84592b26a0713e6944c2b109f6df5c82 > Author: Damien Lespiau > Date: M

Re: [Intel-gfx] [PATCH] drm/i915: fix for_each_digital_port

On pe, 2015-04-17 at 14:58 +0300, Imre Deak wrote: > We should check if a given encoder is of a digital type before casting > it to a digital port object. This broke on HSW when iterating the VGA > encoder. > > Introduced in > commit b403745c84592b26a0713e6944c2b109f6df5c82 > Author: Damien Lespia

[Intel-gfx] [PATCH] drm/i915: fix for_each_digital_port

We should check if a given encoder is of a digital type before casting it to a digital port object. This broke on HSW when iterating the VGA encoder. Introduced in commit b403745c84592b26a0713e6944c2b109f6df5c82 Author: Damien Lespiau Date: Mon Aug 4 22:01:33 2014 +0100 drm/i915: Iterate t

[Intel-gfx] [PATCH] drm/i915: Fixup kerneldoc for struct intel_context

From: Tvrtko Ursulin commit ae6c4806927b8b0781ecc187aa16b10c820fc430 Author: Daniel Vetter Date: Wed Aug 6 15:04:53 2014 +0200 drm/i915: Only track real ppgtt for a context Changed the code but didn't update kerneldoc. Signed-off-by: Tvrtko Ursulin Cc: "Thierry, Michel" Cc

Re: [Intel-gfx] [PATCH libdrm] intel: Leak the userptr test bo

On Fri, Apr 17, 2015 at 11:57:28AM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > In order to use userptr, the kernel tracks the owner's mm with a > mmu_notifier. Setting that is very expensive - it involves taking all > mm_locks and a stop_machine(). This tracking lives only for as long

Re: [Intel-gfx] [PATCH] vt: Don't check KD_GRAPHICS when binding/unbinding

Hi On Mon, Apr 13, 2015 at 11:16 AM, Daniel Vetter wrote: > This was introduced in > > commit 6db4063c5b72b46e9793b0f141a7a3984ac6facf > Author: Antonino A. Daplas > Date: Mon Jun 26 00:27:12 2006 -0700 > > [PATCH] VT binding: Add sysfs control to the VT layer > > with the justification >

[Intel-gfx] [PATCH libdrm] intel: Leak the userptr test bo

From: Tvrtko Ursulin In order to use userptr, the kernel tracks the owner's mm with a mmu_notifier. Setting that is very expensive - it involves taking all mm_locks and a stop_machine(). This tracking lives only for as long as the client is using userptr objects - so if the client allocates then

Re: [Intel-gfx] [PATCH v2] drm/i915: Add debugfs to read any DPCD register

On Fri, Apr 17, 2015 at 06:33:57AM +, R, Durgadoss wrote: > >-Original Message- > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > >Sent: Thursday, April 16, 2015 8:03 PM > >To: Jani Nikula > >Cc: R, Durgadoss; intel-gfx@lists.freedesktop.org; Syrjala, Ville; Zanoni, > >Pa

Re: [Intel-gfx] [PATCH 14/14] drm/i915: Modeset global_pipes() update

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6220 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

[Intel-gfx] [QA 2015/04/17 ww16] Testing report for `drm-intel-testing`

Summary We covered the platforms: Skylake, Braswell, Broadwell, Haswell, Baytrail. In this circle, we don't find big regression, 4 new bugs have been found in manual testing and 8 new bugs have been found in nightly testing. 90006 - [BSW] ASUS P

Re: [Intel-gfx] [PATCH v4 2/8] drm/i915/skl: Add DC5 Trigger Sequence.

On Fri, 2015-04-17 at 11:29 +0530, Animesh Manna wrote: > > On 4/16/2015 3:18 PM, Imre Deak wrote: > > On to, 2015-04-16 at 12:25 +0300, Imre Deak wrote: > >> On to, 2015-04-16 at 14:22 +0530, Animesh Manna wrote: > >>> [...] > >>> @@ -223,11 +244,13 @@ static void finish_csr_load(const struct f

Re: [Intel-gfx] [PATCH v3] drm/i915: Simplify and fix object to display tracking

On ma, 2015-04-13 at 11:50 +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Purpose of this tracking is to know when to flush the cache between > the CPU and the non-coherent display engine. Prior to: > >commit 121920faf2ccce9aa66a7e2588415c9647b66104 >Author: Tvrtko Ursulin >