On ke, 2015-04-15 at 16:52 -0700, Rodrigo Vivi wrote:
> From: Imre Deak
>
> Due this typo we don't save/restore the GFX_MAX_REQ_COUNT register across
> suspend/resume, so fix this.
>
> This was introduced in
>
> commit ddeea5b0c36f3665446518c609be91f9336ef674
> Author: Imre Deak
> Date: Mon
On 04/16/2015 03:29 AM, Peter Hurley wrote:
On 04/15/2015 05:26 PM, Mario Kleiner wrote:
A couple of questions to educate me and one review comment.
On 04/15/2015 07:34 PM, Daniel Vetter wrote:
This was a bit too much cargo-culted, so lets make it solid:
- vblank->count doesn't need to be an a
Chris Wilson writes:
> On Tue, Apr 14, 2015 at 05:35:12PM +0200, Daniel Vetter wrote:
>> They change with the address space and not with each vma, so move them
>> into the right pile of vfuncs. Save 2 pointers per vma and clarifies
>> the code.
>
> Using per-vma vfunc allows you make, for example
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6203
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_r
On Thursday 16 April 2015 12:09 AM, Ville Syrjälä wrote:
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Vil
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6201
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 04/15/2015 05:26 PM, Mario Kleiner wrote:
> A couple of questions to educate me and one review comment.
>
> On 04/15/2015 07:34 PM, Daniel Vetter wrote:
>> This was a bit too much cargo-culted, so lets make it solid:
>> - vblank->count doesn't need to be an atomic, writes are always done
>>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6198
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6198
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, 2015-04-15 at 16:52 -0700, Rodrigo Vivi wrote:
> From: Mika Kuoppala
>
> We just allocated the intel_ringbuffer with kzalloc. There
> is no chance of the ringbuf->obj being other than NULL
> so remove the redudant check.
>
> Signed-off-by: Mika Kuoppala
> Signed-off-by: Rodrigo Vivi
>
Reviewed-by: Rodrigo Vivi
On Wed, 2015-04-15 at 16:52 -0700, Rodrigo Vivi wrote:
> From: Mika Kuoppala
>
> commit 939fd762083f988be271da8c96398178daf9baf0
> Author: Mika Kuoppala
> Date: Thu Jan 30 19:04:44 2014 +0200
>
> drm/i915: Get rid of acthd based guilty batch search
>
> Failed
From: Mika Kuoppala
We just allocated the intel_ringbuffer with kzalloc. There
is no chance of the ringbuf->obj being other than NULL
so remove the redudant check.
Signed-off-by: Mika Kuoppala
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_lrc.c | 29 +
From: Imre Deak
Due this typo we don't save/restore the GFX_MAX_REQ_COUNT register across
suspend/resume, so fix this.
This was introduced in
commit ddeea5b0c36f3665446518c609be91f9336ef674
Author: Imre Deak
Date: Mon May 5 15:19:56 2014 +0300
drm/i915: vlv: add runtime PM support
I no
From: Gaurav K Singh
On CHT, changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.
Signed-off-by: Gaurav
From: Mika Kuoppala
commit 939fd762083f988be271da8c96398178daf9baf0
Author: Mika Kuoppala
Date: Thu Jan 30 19:04:44 2014 +0200
drm/i915: Get rid of acthd based guilty batch search
Failed to cleanup properly as it made the head obsolete.
Signed-off-by: Mika Kuoppala
Signed-off-by: Rodri
With frontbuffer tracking taking care of fbc
we were duplicating fbc update call on these cases here.
Cc: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 12
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 13 deletions(-)
diff --g
From: Chris Wilson
We don't need to incur the overhead of checking whether the object is
pinned prior to changing its madvise. If the object is pinned, the
madvise will not take effect until it is unpinned and so we cannot free
the pages being pointed at by hardware. Marking a pinned object with
From: Gaurav K Singh
For MIPI panels requiring higher DSI clk, values needs to be added
in lfsr_converts table for getting the correct values of pll ctrl
and dividor values which gets programmed in cck regs, otherwise DSI
PLL does not get locked leading to no display on the MIPI panel.
Signed-of
Let userspace know the status of Panel Self-Refresh by virtue of a
property on the appropriate connector.
v2: Only attach the property if the driver is capable of PSR.
v3: Add docbook courtesy of Damien.
v4: Mark the initial value as 'unsupported' - it will be determined
correctly when we late
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
Here goes the update list in order for better reviewers assignment:
Patch drm/i915: Remove pinned check from madvise_ioctl - Reviewer:
Patch drm/i915/vlv: check po
From: Jesse Barnes
Same as IBX and G4x, they all share the same genetic material.
v2: we all need a bit more port in our lives
Signed-off-by: Jesse Barnes
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/
From: chandra konduru
Adding rotation to kms_plane_scaling test.
Signed-off-by: chandra konduru
---
tests/kms_plane_scaling.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 00db5cb..8d22ba4 1
Sonika,
I have rebased 13/14 and 14/14 of scaler series on top of 90/270
and did some refactoring to reduce function size.
Previous versions are already reviewed and Matt gave r-b
for those changes.
Can you review v5 changes and give r-b or ack for them?
You can see below (v5) list of changes trig
This patch enables skylake primary plane scaling using shared
scalers atomic desgin.
v2:
-use single copy of scaler limits (Matt)
v3:
-move detach_scalers to crtc commit path (Matt)
-use values in plane_state->src as regular integers (me)
v4:
-changes to align with updated scaler structures (Mat
This patch enables skylake sprite plane display scaling using shared
scalers atomic desgin.
v2:
-use single copy of scaler limits (Matt)
v3:
-detaching scalers moved to crtc commit path (Matt)
v4:
-changes to align with updated scaler structures (Matt, me)
-keep sprite src rect in 16.16 format (
Displayport compliance test 4.2.2.6 requires that a source device be capable of
detecting a corrupt EDID. The test specification states that the sink device
sets up the EDID with an invalid checksum. To do this, the sink sets up an
invalid EDID header, expecting the source device to generate the ch
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6197
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On 4/15/2015 1:25 PM, Paulo Zanoni wrote:
2015-04-15 14:15 GMT-03:00 Todd Previte :
Displayport compliance test 4.2.2.6 requires that a source device be capable of
detecting a corrupt EDID. The test specification states that the sink device
sets up the EDID with an invalid checksum. To do this
Hi Daniel,
Thank you for the patch.
On Friday 10 April 2015 16:22:39 Daniel Vetter wrote:
> It's a silly thing to do and surprises driver writers. Most likely
> this did already blow up for exynos.
>
> It's also a silly thing to change plane state when it's off, but fbdev
> is silly (it does an
On Wed, Apr 15, 2015 at 2:39 PM, Rodrigo Vivi wrote:
> On Fri, Mar 13, 2015 at 1:46 PM, Eric Caruso wrote:
>> On Fri, Mar 13, 2015 at 1:14 PM, Paulo Zanoni wrote:
>>> 2015-03-13 16:01 GMT-03:00 Daniel Vetter :
On Fri, Mar 13, 2015 at 7:10 PM, Eric Caruso wrote:
> This patch allows user
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6193
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -8
On Fri, Mar 13, 2015 at 1:46 PM, Eric Caruso wrote:
> On Fri, Mar 13, 2015 at 1:14 PM, Paulo Zanoni wrote:
>> 2015-03-13 16:01 GMT-03:00 Daniel Vetter :
>>> On Fri, Mar 13, 2015 at 7:10 PM, Eric Caruso wrote:
This patch allows userspace to toggle PSR through a debugfs interface.
It add
A couple of questions to educate me and one review comment.
On 04/15/2015 07:34 PM, Daniel Vetter wrote:
This was a bit too much cargo-culted, so lets make it solid:
- vblank->count doesn't need to be an atomic, writes are always done
under the protection of dev->vblank_time_lock. Switch to a
2015-04-15 14:15 GMT-03:00 Todd Previte :
> Displayport compliance test 4.2.2.6 requires that a source device be capable
> of
> detecting a corrupt EDID. The test specification states that the sink device
> sets up the EDID with an invalid checksum. To do this, the sink sets up an
> invalid EDID h
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
WARN_ON(!drm_modeset_is_locked(&crtc->mutex)) on intel_psr_ready()
has been removed on v3. We don't dereferrence crtc here anymore so
we don't need this check. All configs are now checked from received
2015-04-15 16:28 GMT-03:00 Todd Previte :
> Move the DPCD read to the top and check for an interrupt from the sink to
> catch
> Displayport automated testing requests necessary to support Displayport
> compliance testing. The checks for active connectors and link status are moved
> below the check
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6195
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
suppo
Move the DPCD read to the top and check for an interrupt from the sink to catch
Displayport automated testing requests necessary to support Displayport
compliance testing. The checks for active connectors and link status are moved
below the check for the interrupt.
The main reason for doing this i
On Tue, Mar 17, 2015 at 11:39:55AM +0200, Imre Deak wrote:
> From: Vandana Kannan
>
> Rename vlv_cdclk_freq to cdclk_freq so that it can be used for all
> platforms as required. Needed by the next patch.
>
> Signed-off-by: Vandana Kannan
> Signed-off-by: A.Sunil Kamath
> Signed-off-by: Imre De
On Wed, Apr 15, 2015 at 04:07:24PM +0300, Mika Kahola wrote:
> Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
> into one function 'intel_modeset_global_pipes()'
>
> v2:
> - we don't modify 'disable_pipes', so passing this as a pointer
> is removed (based on Ville's comment
On Wed, Apr 15, 2015 at 04:07:23PM +0300, Mika Kahola wrote:
> Limit CHV maximum cdclk to 320MHz.
>
> Signed-off-by: Mika Kahola
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i9
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6190
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6190
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -3
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6192
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, 2015-04-15 at 17:15 +0300, Imre Deak wrote:
> From: Satheeshakrishna M
>
> PORT_CLK_SEL programming is needed only on HSW/BDW.
>
> v2:
> - don't program PORT_CLK_SEL from mst encoders either (imre)
> v3:
> - fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien)
>
> Signed-off-by
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> This WA is avoid problem between shadow vs wake FIFO unload
> problem during CPD/RC6 transactions on CHV.
>
> v2: Define individual bits GTFIFOCTL (Ville)
>
> v3: move WA to uncore_early_sanitize (vil
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6196
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, Apr 15, 2015 at 07:34:43PM +0200, Daniel Vetter wrote:
> This was a bit too much cargo-culted, so lets make it solid:
> - vblank->count doesn't need to be an atomic, writes are always done
> under the protection of dev->vblank_time_lock. Switch to an unsigned
> long instead and update c
Hi Daniel, hi Ville,
please find the reworked NS2501 DVO patch with changes as suggested
attached.
Unfortunately, the relation between the DVO scaler settings and the
actual mode
values remain still somewhat mysterious, so the mode settings remain a
table lookup
at this time. On the bright sid
2015-04-15 12:37 GMT-03:00 Todd Previte :
>
>
> On 4/14/2015 9:53 AM, Paulo Zanoni wrote:
>>
>> 2015-04-13 11:53 GMT-03:00 Todd Previte :
>>>
>>> Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in
>>> the
>>> Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read
This was a bit too much cargo-culted, so lets make it solid:
- vblank->count doesn't need to be an atomic, writes are always done
under the protection of dev->vblank_time_lock. Switch to an unsigned
long instead and update comments. Note that atomic_read is just a
normal read of a volatile va
On Wed, Apr 15, 2015 at 09:00:04AM -0400, Peter Hurley wrote:
> Hi Daniel,
>
> On 04/15/2015 03:17 AM, Daniel Vetter wrote:
> > This was a bit too much cargo-culted, so lets make it solid:
> > - vblank->count doesn't need to be an atomic, writes are always done
> > under the protection of dev->v
On Wed, Apr 15, 2015 at 06:11:33PM +0100, Michel Thierry wrote:
> WaIdleLiteRestore is an execlists-only workaround, and requires the driver
> to ensure that any context always has HEAD!=TAIL when attempting lite
> restore.
>
> Add two extra MI_NOOP instructions at the end of each request, but kee
Updates the EDID compliance test function to perform the EDID read as
required by the tests. This read needs to take place in the kernel for
reasons of speed and efficiency. The results of the EDID read operations
are handed off to userspace so that the userspace app can set the display
mode approp
Update the hot plug function to handle the SST case. Instead of placing
the SST case within the long/short pulse block, it is now handled after
determining that MST mode is not in use. This way, the topology management
layer can handle any MST-related operations while SST operations are still
corre
Displayport compliance test 4.2.2.6 requires that a source device be capable of
detecting a corrupt EDID. The test specification states that the sink device
sets up the EDID with an invalid checksum. To do this, the sink sets up an
invalid EDID header, expecting the source device to generate the ch
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
suppo
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.
Add two extra MI_NOOP instructions at the end of each request, but keep
the requests tail pointing before the MI_NOOPs. We may not need to
execu
On 4/15/2015 5:40 PM, Chris Wilson wrote:
On Wed, Apr 15, 2015 at 05:17:13PM +0100, Michel Thierry wrote:
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.
Add two extra MI_NOOP instructions
On Wed, Apr 15, 2015 at 05:17:13PM +0100, Michel Thierry wrote:
> WaIdleLiteRestore is an execlists-only workaround, and requires the driver
> to ensure that any context always has HEAD!=TAIL when attempting lite
> restore.
>
> Add two extra MI_NOOP instructions at the end of each request, but kee
With PSR enabled being pre computed on pipe_config we can now
prevent DRRS to be enabled along with PSR.
v2: Rebase after changing previous patch
Cc: Ramalingam C
Signed-off-by: Rodrigo Vivi
Reviewed-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_dp.c | 10 +-
1 file changed, 5 inser
Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.
v2: Removing is_edp_psr func that is not used after this patch.
Rename match_conditions and document it since it is now external.
Moving to a propper place as pointed out by Sivakumar.
Use
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.
Add two extra MI_NOOP instructions at the end of each request, but keep
the requests tail pointing before the MI_NOOPs. We may not need to
execu
Since the pin_ioctl is defunct, we only care about whether an object is
pinned into the display for debug purposes.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drive
Since the removal of the user pin_ioctl, the only means for pinning an
object is either through binding to the scanout or during execbuf
reservation. As the later prevents a call to set-tiling, we need only
check if the obj is pinned into the display plane to see if we need
reject the set-tiling io
The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1
specifies that repeated AUX transactions after a failure (no response /
invalid response) must have a minimum delay of 400us before the resend can
occur. Tests 4.2.1.1 and 4.2.1.2 are two tests that require this specifically.
This patch adds 3 debugfs files for handling Displayport compliance testing
and supercedes the previous patches that implemented debugfs support for
compliance testing. Those patches were:
- [PATCH 04/17] drm/i915: Add debugfs functions for Displayport
compliance testing
The debug message is missing a newline at the end and it makes the
logs hard to read when a device defers a lot. Simple 2-character fix
adds the newline at the end.
Signed-off-by: Todd Previte
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Paulo Zanoni
Reviewed-by: Alex Deucher
---
drivers/g
This patch is a combination of changes that does the following:
- Ignore disconnected Displayport connectors in check_link_status
- Move the DPCD read further up in intel_dp_check_link_status()
- Adds a new function that checks the HW HPD pin status
- Replace the ch
Add the skeleton framework for supporting automation for Displayport compliance
testing. This patch adds the necessary framework for the source device to
appropriately respond to test automation requests from a sink device.
V2:
- Addressed previous mailing list feedback
- Fixed compilation issue (
For test 4.2.2.5 to pass per the Link CTS Core 1.2 rev1.1 spec, the source
device must attempt at least 7 times to read the EDID when it receives an
I2C defer. The normal DRM code makes only 7 retries, regardless of whether
or not the response is a native defer or an I2C defer. Test 4.2.2.5 fails
s
Updates the EDID compliance test function to perform the EDID read as
required by the tests. This read needs to take place in the kernel for
reasons of speed and efficiency. The results of the EDID read operations
are handed off to userspace so that the userspace app can set the display
mode approp
This is the 6th iteration of the Displayport compliance testing patch set for
performing compliance testing operations of the i915 driver. High level changes
are listed below, with the specifics for each patch listed in the commit
messages.
Kernel:
Changes for V4:
- Removed the code for link c
Update the hot plug function to handle the SST case. Instead of placing
the SST case within the long/short pulse block, it is now handled after
determining that MST mode is not in use. This way, the topology management
layer can handle any MST-related operations while SST operations are still
corre
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID read is also
used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual
suppo
Displayport compliance test 4.2.2.6 requires that a source device be capable of
detecting a corrupt EDID. The test specification states that the sink device
sets up the EDID with an invalid checksum. To do this, the sink sets up an
invalid EDID header, expecting the source device to generate the ch
On 4/14/2015 9:53 AM, Paulo Zanoni wrote:
2015-04-13 11:53 GMT-03:00 Todd Previte :
Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the
Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for
all HPD plug events. To reduce the amount of code, this EDID
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 50
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
3 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/int
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 18 +--
drivers/gpu/drm/i915/intel_display.c | 196 --
drivers/gpu/drm/i915/intel_sprite.c | 25 +---
3 files changed, 134 insertions(+), 105 deletions(-)
diff --git a/driver
This makes disabling planes more explicit.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
drivers/gpu/drm/i915/intel_display.c | 36 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 24 insertions(+), 18 dele
This is used by the next commit to disable all planes on a crtc
without caring what type it is.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 38 +---
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_sprite.c
To make it clear that it isn't called during crtc enable.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d6f147
They're the same code, so why not?
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 158 ++-
drivers/gpu/drm/i915/intel_drv.h | 2 -
drivers/gpu/drm/i915/intel_sprite.c | 68 ---
3 files changed, 102 insertions(+), 12
This allows disabling all planes affecting a crtc without caring what type it
is.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/intel_display.c | 91 ++--
2 files changed, 20 insertions(+), 76 deletions(-)
Some of the flags that were used are still useful when transitioning
to atomic, so keep those around for now. This removes some of the
complications of crtc->primary_enabled, making it easier to remove.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_drv.h| 6 -
drivers/
On Wed, Apr 15, 2015 at 04:42:57PM +0300, Imre Deak wrote:
> From: Vandana Kannan
>
> Add PHY specific display initialization sequence as per BSpec.
>
> Note that the PHY initialization/uninitialization are done
> at their current place only for simplicity, in a future patch - when more
> of the
Hi Daniel,
I am having a look at this now, as have some time.
So, to sum up what I think you want.
1. Re-base and apply the patches (so that the known holes are closed in
the Nouveau driver).
2. Add DRIVER_KMS_LEGACY_CONTEXT to include/drm/drmP.h
3. Add DRIVER_KMS_LEGACY_CONTEXT to .driver_featur
From: Jesse Barnes
Broxton has the same panel fitter registers as Skylake.
v2:
- add MISSING_CASE for future platforms (daniel)
Signed-off-by: Jesse Barnes
Signed-off-by: Imre Deak
Reviewed-by: Sagar Kamble
---
drivers/gpu/drm/i915/intel_display.c | 19 +--
1 file changed, 1
On Wed, Apr 15, 2015 at 04:07:10PM +0300, Mika Kahola wrote:
> This patch series rebases Ville's original cdclk patch series
> excluding the ones that have been reviewed.
>
> http://lists.freedesktop.org/archives/intel-gfx/2014-November/055633.html
>
> The patches include modifications to
From: Satheeshakrishna M
PORT_CLK_SEL programming is needed only on HSW/BDW.
v2:
- don't program PORT_CLK_SEL from mst encoders either (imre)
v3:
- fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien)
Signed-off-by: Satheeshakrishna M
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i91
On Wed, Apr 15, 2015 at 03:08:56PM +0100, Tvrtko Ursulin wrote:
>
> On 04/14/2015 05:31 PM, Chris Wilson wrote:
> >In order to use userptr, the kernel tracks the owner's mm with a
> >mmu_notifier. Setting that is very expensive - it involves taking all
> >mm_locks and a stop_machine(). This tracki
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu
From: Suketu Shah
Add triggers for DC9 as per details provided in bxt_enable_dc9
and bxt_disable_dc9 implementations.
v1:
- Add SKL check in gen9_disable_dc5 as it is possible for DC5
to remain disabled only for SKL.
- Add additional checks for whether DC5 is already disabled during
DC5-disa
On Wed, Apr 15, 2015 at 04:42:56PM +0300, Imre Deak wrote:
> From: Vandana Kannan
>
> Add CDCLK specific display clock initialization sequence as per BSpec.
>
> Note that the CDCLK initialization/uninitialization are done at their
> current place only for simplicity, in a future patch - when mor
On 04/14/2015 05:31 PM, Chris Wilson wrote:
In order to use userptr, the kernel tracks the owner's mm with a
mmu_notifier. Setting that is very expensive - it involves taking all
mm_locks and a stop_machine(). This tracking lives only for as long as
the client is using userptr objects - so if th
Hi,
I forgot to update authorships. I'll fix this and resend the patch
series.
Thanks for pointing this out!
-Mika-
On Wed, 2015-04-15 at 14:16 +0100, Damien Lespiau wrote:
> Hi Mika,
>
> On Wed, Apr 15, 2015 at 04:07:10PM +0300, Mika Kahola wrote:
> > This patch series rebases Ville's origina
On Wed, Apr 15, 2015 at 04:42:58PM +0300, Imre Deak wrote:
> Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.
>
> v2:
> - add more detail about the mapping between ports and transcoders (ville)
>
> Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
> ---
> Documentation/D
From: Vandana Kannan
Add CDCLK specific display clock initialization sequence as per BSpec.
Note that the CDCLK initialization/uninitialization are done at their
current place only for simplicity, in a future patch - when more of the
runtime PM features will be enabled - these will be moved to p
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