Re: [Intel-gfx] [PATCH 13/14] drm/i915: skylake primary plane scaling using shared scalers

On Tue, Apr 07, 2015 at 03:28:46PM -0700, Chandra Konduru wrote: > This patch enables skylake primary plane scaling using shared > scalers atomic desgin. > > v2: > -use single copy of scaler limits (Matt) > > v3: > -move detach_scalers to crtc commit path (Matt) > -use values in plane_state->src

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

Thanks for the update Mika. The issue will be that audio plays faster or slower than normal. i.e it will be < 1x or > 1x. can you confirm if audible sound plays after CD Clock change at 1x speed ? regards, Sivakumar On 4/14/2015 12:06 PM, Mika Kahola wrote: I tested this patch with the audio i

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

I tested this patch with the audio in place. With this setup in my HSW machine I can hear the pink noise played back with DP-HDMI cable attatched. speaker-test -c 2 -r 48000 -F S16_LE -t pink --device=plughw:0,7 Cheers, Mika On Tue, 2015-04-07 at 14:06 +0530, Sivakumar Thulasimani wrote: > where

Re: [Intel-gfx] [PATCH] drm/i915: Workaround to avoid lite restore with HEAD==TAIL

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6171 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -3

Re: [Intel-gfx] [Contact] Graphics Driver for Broadwell-H CPU

Thanks! Jim Poh Heah | Platform Application Engineer | IoTG Intel Penang | 604-253-7860 | jim.poh.h...@intel.com From: Zhang, Xiong Y Sent: Tuesday, April 14, 2015 12:45 PM To: Heah, Jim Poh; intel-gfx@lists.freedesktop.org Cc: Zhang, Xiong Y Subject: RE:

Re: [Intel-gfx] [Contact] Graphics Driver for Broadwell-H CPU

I don’t know the status of Fedora. You could compile upstream 3.19.3 / 4.0 kernel and xf86-video-intel – 2.99.917 in Fedora. thanks From: Heah, Jim Poh Sent: Tuesday, April 14, 2015 12:38 PM To: Zhang, Xiong Y; intel-gfx@lists.freedesktop.org Subject: RE: [Contact] Graphics Driver for Broadwell-

Re: [Intel-gfx] [Contact] Graphics Driver for Broadwell-H CPU

Thanks Xiong, What about Fedora? Are there any plans for Fedora? Jim Poh Heah | Platform Application Engineer | IoTG Intel Penang | 604-253-7860 | jim.poh.h...@intel.com From: Zhang, Xiong Y Sent: Tuesday, April 14, 2015 10:57 AM To: Heah, Jim Poh; intel-

Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl: Support for 90/270 rotation

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6170 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

Re: [Intel-gfx] [Contact] Graphics Driver for Broadwell-H CPU

Ubuntu 15.04 which will be released at the end of this month should support Broadwell-H. Ubuntu 15.04 beta still couldn’t support Broadwell-H. Several days ago, I run Kernel 3.19.3 and xf86-video-intel – 2.99.917 on BDW-H. thanks From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] O

[Intel-gfx] FW: [Contact] Graphics Driver for Broadwell-H CPU

Hi, I am getting Kernel Panics when testing with Broadwell-H CPU (Intel Internal silicon) on Fedora 21 and Ubuntu 14.10. Can you let me know the schedule for testing Broadwell-H silicon? One of the messages were: "drm kms helper: panic occurred" Jim Poh Heah | Platform Application Engi

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Enable PSR by default.

Another questions, Are you using powertop --auto-tune? If so, can you please try to repdoruce X slowness issue on these 2 scenarios: 1. without doing the powertop auto-tune and psr enabled. 2. with powertop auto-tune but with PSR disabled by i915.enable_psr=0 Thanks in advance, Rodrigo. On Mon

Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl: Support for 90/270 rotation

On Mon, Apr 13, 2015 at 01:49:22PM +0300, Ville Syrjälä wrote: > On Mon, Apr 13, 2015 at 03:53:22PM +0530, Jindal, Sonika wrote: > > > > > > On 4/13/2015 3:40 PM, Ville Syrjälä wrote: > > > On Mon, Apr 13, 2015 at 09:36:02AM +0530, Jindal, Sonika wrote: > > >> > > >> > > >> On 4/10/2015 8:14 PM,

Re: [Intel-gfx] [PATCH 1/7] drm/i915: PSR: Remove wrong LINK_DISABLE.

On Thu, Apr 9, 2015 at 10:42 AM, Matthew Garrett wrote: > I've put this patchset on top of current Linus git. Switching to fbcon > tends to result in rolling graphics, and turning the screen back on > often gives me a static display or one that only updates every few > seconds. This is with a Dell

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Enable PSR by default.

Hi Matthew, Could you please check if you can reproduce your issue using this branch: http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=intel_psr Also, 1. What Platform are you using? BDW? 2. What desktop environment do you use? 3. What is your resolution? 4. Is IPS running? 5. Could you plea

Re: [Intel-gfx] [PATCH 06/13] drm: Add supporting structure for Displayport Link CTS test 4.2.2.6

2015-04-13 11:53 GMT-03:00 Todd Previte : > Displayport compliance test 4.2.2.6 requires that a source device be capable > of > detecting a corrupt EDID. The test specification states that the sink device > sets up the EDID with an invalid checksum. To do this, the sink sets up an > invalid EDID h

Re: [Intel-gfx] [PATCH 05/11] drm/i915: Add a delay in Displayport AUX transactions for compliance testing

2015-04-10 13:12 GMT-03:00 Todd Previte : > The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1 > specifies that repeated AUX transactions after a failure (no response / > invalid response) must have a minimum delay of 400us before the resend can > occur. Tests 4.2.1.1 and 4.2.1

[Intel-gfx] [RFC 04/10] drm/i915/config: Add init-time configuration of dp panel fitter property.

Use the init-time configuration setting for scaling_mode to set the initial value of the scaling_mode connector property. v2: Use drm connector name (Jani) Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/intel_dp.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/dr

[Intel-gfx] [RFC 08/10] drm/i915: Add PPS delay values to debugfs.

So that we verify which values are currently in use. Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/i915_debugfs.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2394924..a9b96

[Intel-gfx] [RFC 00/10] i915 init-time configuration (v2)

Background: This capability is targeted at deeply embedded appliance like devices that make use of Intel integrated graphics. There are a few use cases that are not currently supported by the i915 driver. For example, they may not be running user space code that is capable of querying and settin

[Intel-gfx] [RFC 09/10] drm/i915: Add backlight max and level to debugfs output.

To allow us to verify the current backlight max and level values. Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/i915_debugfs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a9b96fd..2bac3bc 100644 --

[Intel-gfx] [RFC 03/10] drm/i915/config: Add init-time configuration of general connector properties.

Set the initial value of the force audio and broadcast rgb properties using property values found in the init-time configuration. v2: Use drm connector name (Jani) Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/intel_modes.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --

[Intel-gfx] [RFC 07/10] drm/i915/config: Add init-time configuration of eDP backlight settings.

Allow the configuration file to overide the backlight max and level settings. Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/intel_panel.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index d8686ce..54c8c

[Intel-gfx] [RFC 06/10] drm/i915/config: Add init-time configuration of eDP PPS delays.

Allow the configuration file to overide the various panel power sequence delay values. Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/intel_dp.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b05ff6d

[Intel-gfx] [RFC 10/10] drm/i915/config: An example/test ACPI property table.

This is an example of what an ACPI property table looks like. Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/i915-properties.asl | 167 +++ 1 file changed, 167 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915-properties.asl diff --git a/drivers/gpu/drm

[Intel-gfx] [RFC 02/10] drm/i915/config: Add init-time configuration of bits per color.

Allow the init-time configuration to specify the bits per color value that gets used if bits per color is not present in EDID data (or if EDID is not present). v2: Use connector->base.name for connector name (Jani) Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/intel_display.c | 14

[Intel-gfx] [RFC 01/10] drm/i915/config: Initial framework

This adds an init-time configuration framework that parses configuration data from an ACPI property table. The table is assumed to have well defined sub-device property tables that correspond to the various driver components. Initially the following sub-device tables are defined: CRTC (CRTC) T

[Intel-gfx] [RFC 05/10] drm/i915/config: Add init-time configuration of DP max link rate.

If the sink does not provide a maximum link rate, then check the connector configuration before defaulting to the lowest allowed link rate. Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/intel_dp.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/g

Re: [Intel-gfx] [PATCH] drm: Make integer overflow checking cover universal cursor updates (v2)

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6187 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -8

[Intel-gfx] ns2501 DVO - success at last

Hi Daniel, hi Ville, some success at last. I couldn't stop myself playing with the NatSemi 2501 DVO in my Fujitsu S6010 and I believe I finally got a hang on this chip. I believe I understand now most of the undocumented registers. There are also a couple of additional features that are, appa

Re: [Intel-gfx] Kernel panic every other reboot/poweroff since 3.19.3 ( commit 9a6f5130143 )

On 2 April 2015 at 12:02, Jani Nikula wrote: > On Tue, 31 Mar 2015, Steven Honeyman wrote: >> On 31 March 2015 at 17:50, Matt Roper wrote: >>> On Tue, Mar 31, 2015 at 08:54:19AM +0200, Daniel Vetter wrote: Adding mailing lists (and hooray for me mixing up addresses, so now there's a di

Re: [Intel-gfx] [PATCH] drm/i915: Move drm_framebuffer_unreference out of struct_mutex for takeover

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6186 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -4

Re: [Intel-gfx] [PATCH 13/14] drm/i915: skylake primary plane scaling using shared scalers

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter > Sent: Monday, April 13, 2015 11:13 AM > To: Konduru, Chandra > Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander; Vetter, > Daniel > Subject: Re: [Intel-gfx] [PATCH 13/

Re: [Intel-gfx] [PATCH 13/14] drm/i915: skylake primary plane scaling using shared scalers

On Tue, Apr 07, 2015 at 03:28:46PM -0700, Chandra Konduru wrote: > This patch enables skylake primary plane scaling using shared > scalers atomic desgin. > > v2: > -use single copy of scaler limits (Matt) > > v3: > -move detach_scalers to crtc commit path (Matt) > -use values in plane_state->src

[Intel-gfx] [PATCH] drm: Make integer overflow checking cover universal cursor updates (v2)

Our legacy SetPlane updates perform integer overflow checking on a plane's destination rectangle in drm_mode_setplane(), and atomic updates handled as part of a drm_atomic_state transaction do the same checking in drm_atomic_plane_check(). However legacy cursor updates that get routed through univ

Re: [Intel-gfx] [PATCH v3 3/8] drm/i915/skl: Add DC5 Trigger Sequence

On Mon, Apr 13, 2015 at 03:56:23PM +0530, Animesh Manna wrote: > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 90e47a9..8d6deaa 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -667,6 +667,12 @@ struct intel_uncore

Re: [Intel-gfx] [PATCH v3 3/8] drm/i915/skl: Add DC5 Trigger Sequence

On Mon, Apr 13, 2015 at 02:33:50PM +0300, Imre Deak wrote: > > @@ -424,6 +434,25 @@ static void skl_set_power_well(struct drm_i915_private > > *dev_priv, > > I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); > > POSTING_READ(HSW_PWR_WELL_DRIVER); > >

Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add automated testing support for Displayport compliance testing

2015-04-10 13:12 GMT-03:00 Todd Previte : > Add the skeleton framework for supporting automation for Displayport > compliance > testing. This patch adds the necessary framework for the source device to > appropriately respond to test automation requests from a sink device. > > V2: > - Addressed pr

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/skl: Add support to load SKL CSR firmware

On Mon, Apr 13, 2015 at 08:15:29PM +0300, Imre Deak wrote: > Ok, I haven't seen that. One question is if we need to support multiple > interface versions or just the latest one. I would say only the latest > one (for each platform) and so I915_CSR_SKL should be this latest > firmware image filename

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/skl: Add support to load SKL CSR firmware

On Mon, 2015-04-13 at 18:02 +0100, Damien Lespiau wrote: > On Mon, Apr 13, 2015 at 07:52:54PM +0300, Imre Deak wrote: > > On Mon, 2015-04-13 at 17:34 +0100, Damien Lespiau wrote: > > > On Mon, Apr 13, 2015 at 03:54:02PM +0530, Animesh Manna wrote: > > > > diff --git a/drivers/gpu/drm/i915/intel_csr

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/skl: Add support to load SKL CSR firmware

On Mon, Apr 13, 2015 at 07:52:54PM +0300, Imre Deak wrote: > On Mon, 2015-04-13 at 17:34 +0100, Damien Lespiau wrote: > > On Mon, Apr 13, 2015 at 03:54:02PM +0530, Animesh Manna wrote: > > > diff --git a/drivers/gpu/drm/i915/intel_csr.h > > > b/drivers/gpu/drm/i915/intel_csr.h > > > new file mode

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/skl: Add support to load SKL CSR firmware

On Mon, 2015-04-13 at 17:34 +0100, Damien Lespiau wrote: > On Mon, Apr 13, 2015 at 03:54:02PM +0530, Animesh Manna wrote: > > diff --git a/drivers/gpu/drm/i915/intel_csr.h > > b/drivers/gpu/drm/i915/intel_csr.h > > new file mode 100644 > > index 000..c2a5a53 > > --- /dev/null > > +++ b/drivers

[Intel-gfx] [PATCH i-g-t 1/2] lib: use a critical warning when unable to open a data file

Signed-off-by: Thomas Wood --- lib/igt_core.c | 5 + tests/testdisplay.c | 5 + 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/lib/igt_core.c b/lib/igt_core.c index daef8c6..700604f 100644 --- a/lib/igt_core.c +++ b/lib/igt_core.c @@ -1751,5 +1751,10 @@ FILE *__igt_fo

[Intel-gfx] [PATCH i-g-t 2/2] lib: load images from the data directory in igt_paint_image

Update igt_paint_image so that it can read images from the package data directory. Signed-off-by: Thomas Wood --- lib/Android.mk | 2 +- lib/Makefile.am | 3 ++- lib/igt_fb.c| 23 +-- tests/testdisplay.c | 35 ++- 4 files cha

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/skl: Add support to load SKL CSR firmware

On Mon, Apr 13, 2015 at 03:54:02PM +0530, Animesh Manna wrote: > diff --git a/drivers/gpu/drm/i915/intel_csr.h > b/drivers/gpu/drm/i915/intel_csr.h > new file mode 100644 > index 000..c2a5a53 > --- /dev/null > +++ b/drivers/gpu/drm/i915/intel_csr.h > + [...] > +#define I915_CSR_SKL "i915/dmc

Re: [Intel-gfx] [PATCH] drm/i915: Disable execlists by default for gen8

On 04/11/2015 01:41 AM, Chris Wilson wrote: > Bug reports are still coming in for late 4.0-rcX that indicate that > execlists causes GPU hangs following resume. > > Fixes regression from > commit d7f621e50704306c348ccb192f17047f1499f9bc > Author: Oscar Mateo > Date: Thu Jul 24 17:04:49 2014 +01

Re: [Intel-gfx] [PATCH v3 3/8] drm/i915/skl: Add DC5 Trigger Sequence

On Mon, Apr 13, 2015 at 03:56:23PM +0530, Animesh Manna wrote: > @@ -71,6 +90,8 @@ void intel_csr_load_program(struct drm_device *dev) > I915_WRITE(dev_priv->csr.mmioaddr[i], > dev_priv->csr.mmiodata[i]); > } > + > + intel_csr_load_status_set(dev_priv,

[Intel-gfx] [PATCH] drm/i915: Move drm_framebuffer_unreference out of struct_mutex for takeover

From: Tvrtko Ursulin intel_user_framebuffer_destroy() requires the struct_mutex for its object bookkeeping, so this means that all calls to drm_framebuffer_unreference must be held without that lock. This is a simplified version of the identically named patch by Chris Wilson. Regression fro

Re: [Intel-gfx] [PATCH 04/11] drm/i915: Add EDID read in intel_dp_check_link_status() for Link CTS 4.2.2.1

On 4/13/15 7:10 AM, Paulo Zanoni wrote: 2015-04-10 13:12 GMT-03:00 Todd Previte : Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for all HPD plug events. To reduce the amount of code, this EDID r

[Intel-gfx] [PATCH 06/13] drm: Add supporting structure for Displayport Link CTS test 4.2.2.6

Displayport compliance test 4.2.2.6 requires that a source device be capable of detecting a corrupt EDID. The test specification states that the sink device sets up the EDID with an invalid checksum. To do this, the sink sets up an invalid EDID header, expecting the source device to generate the ch

[Intel-gfx] [PATCH 04/13] drm/i915: Add EDID read in intel_dp_check_link_status() for Link CTS 4.2.2.1

Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for all HPD plug events. To reduce the amount of code, this EDID read is also used for Link CTS tests 4.2.2.3, 4.2.2.4, 4.2.2.5 and 4.2.2.6. Actual suppo

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_mmap_gtt: add huge BO test

On 04/13/2015 03:22 PM, Joonas Lahtinen wrote: On ma, 2015-04-13 at 12:32 +0100, Tvrtko Ursulin wrote: Hi, On 04/07/2015 01:23 PM, Joonas Lahtinen wrote: Add a straightforward test that allocates a BO that is bigger than (by 1 page currently) the mappable aperture, tests mmap access to it by

[Intel-gfx] [PATCH v3 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

From: Shashank Sharma This patch adds conditional checks in gen8_irq functions to support BXT. Most of the checks just look for PCH split availability, and block the call to PCH interrupt functions if not available. v2: (jani) - drop redundant TODO comment about PCH IRQ flags on BXT - check HAS_

Re: [Intel-gfx] [PATCH] Remove illogical/bogus "Automatic" mode from "Broadcast RGB" property

On Mon, Apr 13, 2015 at 03:13:12PM +0100, Damien Lespiau wrote: > On Wed, Apr 08, 2015 at 07:18:06PM +0800, Tom Yan wrote: > > https://bugzilla.kernel.org/show_bug.cgi?id=94921 > > > > As mentioned in the above bug report, switching output color range > > "Automatically" according to current mode

[Intel-gfx] [PATCH i-g-t v4 2/2] tests/gem_mmap_gtt: add huge BO test

Add a straightforward test that allocates a BO that is bigger than (by 1 page currently) the mappable aperture, tests mmap access to it by CPU directly and through GTT in sequence. Currently it is expected for the GTT access to gracefully fail as all objects are attempted to get pinned to GTT comp

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_mmap_gtt: add huge BO test

On ma, 2015-04-13 at 12:32 +0100, Tvrtko Ursulin wrote: > Hi, > > On 04/07/2015 01:23 PM, Joonas Lahtinen wrote: > > Add a straightforward test that allocates a BO that is bigger than > > (by 1 page currently) the mappable aperture, tests mmap access to it > > by CPU directly and through GTT in se

Re: [Intel-gfx] [PATCH] Remove illogical/bogus "Automatic" mode from "Broadcast RGB" property

On Wed, Apr 08, 2015 at 07:18:06PM +0800, Tom Yan wrote: > https://bugzilla.kernel.org/show_bug.cgi?id=94921 > > As mentioned in the above bug report, switching output color range > "Automatically" according to current mode does not make sense in > computer use case. Current code seems correct to

Re: [Intel-gfx] [PATCH 04/11] drm/i915: Add EDID read in intel_dp_check_link_status() for Link CTS 4.2.2.1

2015-04-10 13:12 GMT-03:00 Todd Previte : > Adds in an EDID read after the DPCD read to accommodate test 4.2.2.1 in the > Displayport Link CTS Core 1.2 rev1.1. This test requires an EDID read for > all HPD plug events. To reduce the amount of code, this EDID read is also > used for Link CTS tests 4

Re: [Intel-gfx] [PATCH v2 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

On ma, 2015-04-13 at 16:51 +0300, Jani Nikula wrote: > On Fri, 10 Apr 2015, Imre Deak wrote: > > From: Shashank Sharma > > > > This patch adds conditional checks in gen8_irq functions > > to support BXT. Most of the checks just look for PCH split > > availability, and block the call to PCH interr

Re: [Intel-gfx] [PATCH] drm/i915: Move drm_framebuffer_unreference out of struct_mutex for takeover

On Mon, Apr 13, 2015 at 02:37:41PM +0100, Tvrtko Ursulin wrote: > > On 04/13/2015 01:09 PM, Jani Nikula wrote: > > On Thu, 26 Mar 2015, Tvrtko Ursulin wrote: > >> On 03/26/2015 01:30 PM, Ville Syrjälä wrote: > >>> On Thu, Mar 26, 2015 at 12:39:40PM +, Tvrtko Ursulin wrote: > From: Tvrtko

Re: [Intel-gfx] [PATCH 2/8] drm/i915/skl: Implement enable/disable for Display C5 sttate.

On ma, 2015-04-13 at 14:17 +0100, Damien Lespiau wrote: > On Thu, Apr 02, 2015 at 06:58:22PM +0300, Imre Deak wrote: > > On ke, 2015-04-01 at 16:22 +0530, Animesh Manna wrote: > > > From: "A.Sunil Kamath" > > > > > > This patch just implements the basic enable and disable > > > functions of DC5 s

Re: [Intel-gfx] [PATCH v4 27/49] drm/i915/bxt: Enable GMBUS IRQ

On Fri, 10 Apr 2015, Imre Deak wrote: > From: Shashank Sharma > > GMBUS interrupt has been moved to CPU side in BXT. > What this patch does is: > 1. Enable GMBUS IRQ in de_post_install function > 2. Handle this interrupt as a port interrupt in display irq >handler > > v2: Rebase on top of the

Re: [Intel-gfx] [PATCH v2 26/49] drm/i915/bxt: Add BXT support in gen8_irq functions

On Fri, 10 Apr 2015, Imre Deak wrote: > From: Shashank Sharma > > This patch adds conditional checks in gen8_irq functions > to support BXT. Most of the checks just look for PCH split > availability, and block the call to PCH interrupt functions if > not available. > > v2: (jani) > - drop redunda

Re: [Intel-gfx] [PATCH v2 25/49] drm/i915/bxt: Add DDI hpd handler

On Fri, 10 Apr 2015, Imre Deak wrote: > From: Shashank Sharma > > This patch adds a hot plug interrupt handler function for BXT. > What this function typically does is: > 1. Check if hot plug is enabled from hot plug control register. > 2. Call hpd_irq_handler with appropriate trigger to detect a

Re: [Intel-gfx] [PATCH v7 24/49] drm/i915/bxt: DDI Hotplug interrupt setup

On Fri, 10 Apr 2015, Imre Deak wrote: > From: Shashank Sharma > > In BXT, DDI hotplug control has been moved to CPU from PCH. > This patch adds a new IRQ setup function for BXT which: > 1. Checks which HPD ports are requested to be enabled by encoders. > 2. Enables those ports in the hot plug con

Re: [Intel-gfx] [PATCH] drm/i915: Move drm_framebuffer_unreference out of struct_mutex for takeover

On 04/13/2015 01:09 PM, Jani Nikula wrote: On Thu, 26 Mar 2015, Tvrtko Ursulin wrote: On 03/26/2015 01:30 PM, Ville Syrjälä wrote: On Thu, Mar 26, 2015 at 12:39:40PM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin intel_user_framebuffer_destroy() requires the struct_mutex for its object

Re: [Intel-gfx] [PATCH] vt: Don't check KD_GRAPHICS when binding/unbinding

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6185 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -4

Re: [Intel-gfx] [PATCH] drm/i915: Add missing MacBook Pro models with dual channel LVDS

[dunno what the distribution was originally; adding intel-gfx] On Sun, 12 Apr 2015, Lukas Wunner wrote: > All 17" models with i915 graphics had a resolution of 1920x1200, > necessitating dual channel LVDS. The 15" pre-retina models had > up to 1680x1050, hence used dual channel LVDS as well. I

Re: [Intel-gfx] [PATCH 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

On ma, 2015-04-13 at 14:21 +0100, Damien Lespiau wrote: > On Sun, Apr 12, 2015 at 03:52:12PM +0530, sagar.a.kam...@intel.com wrote: > > For patch at > > http://lists.freedesktop.org/archives/intel-gfx/2015-March/062169.html > > Reviewed-by: Sagar Kamble > > Usually reviews are done as a reply to

Re: [Intel-gfx] [PATCH 34/49] drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9

On Sun, Apr 12, 2015 at 03:52:12PM +0530, sagar.a.kam...@intel.com wrote: > For patch at > http://lists.freedesktop.org/archives/intel-gfx/2015-March/062169.html > Reviewed-by: Sagar Kamble Usually reviews are done as a reply to the patch, but maybe you didn't receive the earlier mail? -

Re: [Intel-gfx] [PATCH 2/8] drm/i915/skl: Implement enable/disable for Display C5 sttate.

On Thu, Apr 02, 2015 at 06:58:22PM +0300, Imre Deak wrote: > On ke, 2015-04-01 at 16:22 +0530, Animesh Manna wrote: > > From: "A.Sunil Kamath" > > > > This patch just implements the basic enable and disable > > functions of DC5 state which is needed for both SKL and BXT. > > Reviewed-by: Imre De

Re: [Intel-gfx] [PATCH v2 6/8] drm/i915/skl: Add DC6 Trigger sequence.

On pe, 2015-04-10 at 20:41 +0530, Animesh Manna wrote: > From: Suketu Shah > > Add triggers for DC6 as per details provided in skl_enable_dc6 > and skl_disable_dc6 implementations. > > Also Call POSTING_READ for every write to a register to ensure > it is written to immediately > > v1: Remove P

Re: [Intel-gfx] [PATCH v2 4/8] drm/i915/skl: Assert the requirements to enter or exit DC5.

On pe, 2015-04-10 at 20:41 +0530, Animesh Manna wrote: > From: Suketu Shah > > Warn if the conditions to enter or exit DC5 are not satisfied such > as support for runtime PM, state of power well, CSR loading etc. > > v2: Removed camelcase in functions and variables. > > v3: Do some minimal chec

Re: [Intel-gfx] [PATCH] lib: Implement gem_sync() using WAIT

On Mon, Apr 13, 2015 at 12:01:34PM +0100, Chris Wilson wrote: > When synchronising to rendering, we only want to wait for it to complete > and avoid the cache-domain side-effects of SET_DOMAIN if possible. This > has the advantage of speeding up a few tests (and thereby making the > actual test mor

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/skl: Add support to load SKL CSR firmware

On ma, 2015-04-13 at 18:37 +0530, Animesh Manna wrote: > > On 04/13/2015 04:33 PM, Imre Deak wrote: > > On ma, 2015-04-13 at 15:54 +0530, Animesh Manna wrote: > >> From: "A.Sunil Kamath" > >> > >> Display Context Save and Restore support is needed for > >> various SKL Display C states like DC5, D

Re: [Intel-gfx] [PATCH] drm/i915: Fix screen flickering on X

On Sat, 2015-04-11 at 19:17 -0300, Ismael Luceno wrote: > A bisect showed that commit 32b7eeec4d1e861230b09d437e95d76c86ff4a68 > introduced the issue. > > The issue starts as soon as X takes control of the screen, even if just > a plain X doing nothing, so based on the code touched by the commit I

Re: [Intel-gfx] [PATCH v2] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

On Mon, Apr 13, 2015 at 02:04:27PM +0300, Jani Nikula wrote: > On Sat, 11 Apr 2015, shuang...@intel.com wrote: > > Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: > > shuang...@intel.com) > > Task id: 6167 > > -Summary---

Re: [Intel-gfx] [PATCH 66/70] drm/i915: Remove obj->pin_mappable

On Mon, Apr 13, 2015 at 12:35:53PM +0100, Tvrtko Ursulin wrote: > > On 04/07/2015 05:28 PM, Chris Wilson wrote: > >The obj->pin_mappable flag only exists for debug purposes and is a > >hindrance that is mistreated with rotated GGTT views. For debug > >purposes, it suffices to mark objects with pin

Re: [Intel-gfx] [PATCH 17/70] drm/i915: Optimistically spin for the request completion

On Mon, Apr 13, 2015 at 12:34:19PM +0100, Tvrtko Ursulin wrote: > > Hi, > > On 04/07/2015 04:20 PM, Chris Wilson wrote: > >This provides a nice boost to mesa in swap bound scenarios (as mesa > >throttles itself to the previous frame and given the scenario that will > >complete shortly). It will a

[Intel-gfx] [PATCH] drm/i915: Add missing MacBook Pro models with dual channel LVDS

All 17" models with i915 graphics had a resolution of 1920x1200, necessitating dual channel LVDS. The 15" pre-retina models had up to 1680x1050, hence used dual channel LVDS as well. Reference for MacBookPro9,1 (also tested by myself): http://ubuntuforums.org/showthread.php?t=2224567 Reference fo

[Intel-gfx] [PATCH] drm/i915: Fix screen flickering on X

A bisect showed that commit 32b7eeec4d1e861230b09d437e95d76c86ff4a68 introduced the issue. The issue starts as soon as X takes control of the screen, even if just a plain X doing nothing, so based on the code touched by the commit I thought it had to be related to the so called "hardware cursor".

[Intel-gfx] [PATCH] Remove illogical/bogus "Automatic" mode from "Broadcast RGB" property

https://bugzilla.kernel.org/show_bug.cgi?id=94921 As mentioned in the above bug report, switching output color range "Automatically" according to current mode does not make sense in computer use case. --- drivers/gpu/drm/i915/i915_drv.h| 5 ++--- drivers/gpu/drm/i915/intel_dp.c| 23 ++-

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/skl: Add support to load SKL CSR firmware

On 04/13/2015 04:33 PM, Imre Deak wrote: On ma, 2015-04-13 at 15:54 +0530, Animesh Manna wrote: From: "A.Sunil Kamath" Display Context Save and Restore support is needed for various SKL Display C states like DC5, DC6. This implementation is added based on first version of DMC CSR program th

Re: [Intel-gfx] [PATCH] drm/i915: Remove wait for for punit to updates freq.

On Mon, Apr 13, 2015 at 02:55:12PM +0300, Jani Nikula wrote: > On Thu, 05 Mar 2015, deepa...@linux.intel.com wrote: > > From: Deepak S > > > > When GPU is idle on VLV, Request freq to punit should be good enough to > > get the voltage back to VNN. Also, make sure gfx clock force applies > > before

Re: [Intel-gfx] [PATCH] drm/i915: Move drm_framebuffer_unreference out of struct_mutex for takeover

On Thu, 26 Mar 2015, Tvrtko Ursulin wrote: > On 03/26/2015 01:30 PM, Ville Syrjälä wrote: >> On Thu, Mar 26, 2015 at 12:39:40PM +, Tvrtko Ursulin wrote: >>> From: Tvrtko Ursulin >>> >>> intel_user_framebuffer_destroy() requires the struct_mutex for its >>> object bookkeeping, so this means th

Re: [Intel-gfx] [PATCH] drm/i915: Disable WaGsvRC0ResidencyMethod for vlv

On Thu, 19 Mar 2015, Daniel Vetter wrote: > On Thu, Mar 19, 2015 at 03:38:19PM +0200, David Weinehall wrote: >> On Thu, Mar 19, 2015 at 06:17:00PM +0530, Deepak S wrote: >> > >> > >> > On Thursday 19 March 2015 05:14 PM, David Weinehall wrote: >> > >On Thu, Mar 19, 2015 at 04:09:44PM +0530, deep

Re: [Intel-gfx] [PATCH] drm/i915: Remove wait for for punit to updates freq.

On Thu, 05 Mar 2015, deepa...@linux.intel.com wrote: > From: Deepak S > > When GPU is idle on VLV, Request freq to punit should be good enough to > get the voltage back to VNN. Also, make sure gfx clock force applies > before requesting the freq fot vlv. > > Bugzilla: https://bugs.freedesktop.org/

Re: [Intel-gfx] [PATCH 66/70] drm/i915: Remove obj->pin_mappable

On 04/07/2015 05:28 PM, Chris Wilson wrote: The obj->pin_mappable flag only exists for debug purposes and is a hindrance that is mistreated with rotated GGTT views. For debug purposes, it suffices to mark objects with pin_display as being of note. Signed-off-by: Chris Wilson --- drivers/gpu/

Re: [Intel-gfx] [PATCH 17/70] drm/i915: Optimistically spin for the request completion

Hi, On 04/07/2015 04:20 PM, Chris Wilson wrote: This provides a nice boost to mesa in swap bound scenarios (as mesa throttles itself to the previous frame and given the scenario that will complete shortly). It will also provide a good boost to systems running with semaphores disabled and so fre

Re: [Intel-gfx] [PATCH v3 3/8] drm/i915/skl: Add DC5 Trigger Sequence

On ma, 2015-04-13 at 15:56 +0530, Animesh Manna wrote: > From: Suketu Shah > > Add triggers as per expectations mentioned in gen9_enable_dc5 > and gen9_disable_dc5 patch. > > Also call POSTING_READ for every write to a register to ensure that > its written immediately. > > v1: Remove POSTING_RE

Re: [Intel-gfx] [PATCH i-g-t] tests/gem_mmap_gtt: add huge BO test

Hi, On 04/07/2015 01:23 PM, Joonas Lahtinen wrote: Add a straightforward test that allocates a BO that is bigger than (by 1 page currently) the mappable aperture, tests mmap access to it by CPU directly and through GTT in sequence. Currently it is expected for the GTT access to gracefully fail

Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl: Support for 90/270 rotation

On Mon, Apr 13, 2015 at 03:53:22PM +0530, Jindal, Sonika wrote: > >>I never really got the to understand the need of reversing 90 and 270 :) > >>The last discussion was not concluded, AFAIR. > >>Things look correct to me and work fine with the testcase also. > >>Is there something completely differ

Re: [Intel-gfx] [PATCH] drm/i915: make drm_crtc_helper_funcs const data

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6184 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

Re: [Intel-gfx] [PATCH 03/11] drm/i915: Reset changed flags when duplicating crtc state

On Fri, 10 Apr 2015, Ander Conselvan de Oliveira wrote: > Otherwise, once we start doing atomic updates, the values from a > previous update might be used, leading to unnecessary changes. > > Signed-off-by: Ander Conselvan de Oliveira > > --- > drivers/gpu/drm/i915/intel_atomic.c | 6 +- >

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915/skl: Add support to load SKL CSR firmware

On ma, 2015-04-13 at 15:54 +0530, Animesh Manna wrote: > From: "A.Sunil Kamath" > > Display Context Save and Restore support is needed for > various SKL Display C states like DC5, DC6. > > This implementation is added based on first version of DMC CSR program > that we received from h/w team. >

Re: [Intel-gfx] [PATCH v2] drm/i915/chv: Remove DPIO force latency causing interpair skew issue

On Sat, 11 Apr 2015, shuang...@intel.com wrote: > Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: > shuang...@intel.com) > Task id: 6167 > -Summary- > Platform Delta drm-intel-nightly

Re: [Intel-gfx] [PATCH] drm/i915: Allow userptr backchannel for passing aroung GTT mappings

On 04/02/2015 05:27 PM, Chris Wilson wrote: On Thu, Apr 02, 2015 at 05:11:58PM +0100, Tvrtko Ursulin wrote: +static struct drm_i915_gem_object * +find_object_from_vma(struct drm_device *dev, +struct drm_i915_gem_userptr *args) +{ + struct drm_i915_gem_object *obj = NUL

[Intel-gfx] [PATCH] lib: Implement gem_sync() using WAIT

When synchronising to rendering, we only want to wait for it to complete and avoid the cache-domain side-effects of SET_DOMAIN if possible. This has the advantage of speeding up a few tests (and thereby making the actual test more explicit in terms of kernel operations). Of course some tests may be

[Intel-gfx] [PATCH v3] drm/i915: Simplify and fix object to display tracking

From: Tvrtko Ursulin Purpose of this tracking is to know when to flush the cache between the CPU and the non-coherent display engine. Prior to: commit 121920faf2ccce9aa66a7e2588415c9647b66104 Author: Tvrtko Ursulin Date: Mon Mar 23 11:10:37 2015 + drm/i915/skl: Query disp

Re: [Intel-gfx] [PATCH 2/2] drm/i915/skl: Support for 90/270 rotation

On Mon, Apr 13, 2015 at 03:53:22PM +0530, Jindal, Sonika wrote: > > > On 4/13/2015 3:40 PM, Ville Syrjälä wrote: > > On Mon, Apr 13, 2015 at 09:36:02AM +0530, Jindal, Sonika wrote: > >> > >> > >> On 4/10/2015 8:14 PM, Ville Syrjälä wrote: > >>> On Fri, Apr 10, 2015 at 04:17:17PM +0200, Daniel Vet

Re: [Intel-gfx] [PATCH 15/19] drm/i915: HSW cdclk support

On Mon, Apr 13, 2015 at 12:43:14PM +0300, Mika Kahola wrote: > On Fri, 2015-04-10 at 16:10 +0200, Takashi Iwai wrote: > > At Fri, 10 Apr 2015 16:27:39 +0300, > > Mika Kahola wrote: > > > > > > On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote: > > > > At Thu, 9 Apr 2015 15:51:27 +0200, > > > >

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